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SL28541BQCR

SL28541BQCR

  • 厂商:

    SILABS(芯科科技)

  • 封装:

    VFQFN-64

  • 描述:

    IC CLOCK CK505 MOBILE 64QFN

  • 数据手册
  • 价格&库存
SL28541BQCR 数据手册
SL28541 Clock Generator for Intel®Mobile Chipset Features • Intel® CK505 Rev. 1.0 Compliant • Low power push-pull type differential output buffers • Integrated voltage regulator • Integrated resistors on differential clocks • Scalable low voltage VDD_IO (1.05V to 3.3V) • 8-step programmable drive strength for single-ended clocks • Differential CPU clocks with selectable frequency • 100 MHz Differential SRC clocks • 100 MHz Differential LCD clock • 96 MHz Differential DOT clock • 48 MHz USB clock • 33 MHz PCI clocks • 27 MHz Video clocks • Buffered Reference Clock 14.318 MHz • 14.318 MHz Crystal Input or Clock Input • Low-voltage frequency select input • I2C support with readback capabilities • Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction • Industrial Temperature -40°C to 85°C • 3.3V Power supply • 64-pin QFN and TSSOP packages CPU SRC x2 / x3 x8/12 PCI REF DOT96 USB_48 LCD x6 x1 x1 x1 x1 Block Diagram ........................ DOC #: SP-AP-0063 (Rev. AA) Page 1 of 31 400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1+(512) 416-9669 www.silabs.com 27M x2 SL28541 VSS_SRC SRC7#/OE#_6 SRC7/OE#_8 VDD_SRC_IO SRC8#/ CPU2_ITP# SRC8/ CPU2_ITP NC VDD_CPU_IO CPU1# CPU1 VSS_CPU CPU#0 CPU0 VDD_CPU CKPWRGD/PD# 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VSS_REF 1 XOUT 2 48 SRC6 47 SRC# XIN/CLKIN 3 VDD_REF 4 46 VDD_SRC 45 PCI_STP# REF0/FSC/TEST_SEL 5 SDATA 6 44 CPU_STP# 43 VDD_SRC_IO SCLK 7 PCI0/OE#_0/2_A 8 42 SRC10# 41 SRC10 64 QFN VDD_PCI 9 PCI1/OE#_0/2_A 10 PCI2/TME 11 40 SRC11/OE#_10 39 SRC11#//OE#_9 38 SRC9# PCI3 12 37 SRC9 PCI4/GCLK_SEL 13 PCIF0/ITP_EN 14 ........................ DOC #: SP-AP-0063 (Rev. AA) Page 2 of 31 36 VSS_SRC 35 SRC4# VSS_PCI 15 34 SRC4 VDD_48 16 33 VDD_SRC_IO SRC3#/OE#_1/4_B SRC3/OE#_0/2_B VSS_SRC SRC2#/SATA# SRC2/SATA VDD_PLL3_IO VSS_PLL3 SRC1#/LCD100#/27M_SS SRC1/LCD100/27M_NSS VDD_PLL3 VSS_IO SRC0#/DOT96# 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SRC0/DOT96 SCLK SDATA REF0/FSC/TEST_SEL VDD_REF XIN/CLKIN XOUT VSS_REF FSB/TEST_MODE CKPWRGD/PD# VDD_CPU CPU0 CPU#0 VSS_CPU CPU1 CPU1# VDD_CPU_IO NC SRC8/ CPU2_ITP SRC8#/ CPU2_ITP# VDD_SRC_IO SRC7/OE#_8 SRC7#/OE#_6 VSS_SRC SRC6 SRC# VDD_SRC PCI_STP# CPU_STP# VDD_SRC_IO SRC10# SRC10 SRC11/OE#_10 VDD_IO 64 TSSOP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VSS_48 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 USB_48/ FSA PCI0/OE#_0/2_A VDD_PCI PCI1/OE#_0/2_A PCI2/TME PCI3 PCI4/GCLK_SEL PCIF0/ITP_EN VSS_PCI VDD_48 USB_48/ FSA VSS_48 VDD_IO SRC0/DOT96 SRC0#/DOT96# VSS_IO VDD_PLL3 SRC1/LCD100/27M_NSS SRC1#/LCD100#/27M_SS VSS_PLL3 VDD_PLL3_IO SRC2/SATA SRC2#/SATA# VSS_SRC SRC3/OE#_0/2_B SRC3#/OE#_1/4_B VDD_SRC_IO SRC4 SRC4# VSS_SRC SRC9 SRC9# SRC11#//OE#_9 FSB/TEST_MODE Pin Configurations SL28541 64 QFN Pin Definitions Pin No. 1 Name Type Description VSS_REF GND Ground for outputs. O, SE 14.318MHz Crystal output. (Float XOUT if using CLKIN) 2 XOUT 3 XIN/CLKIN I 4 VDD_REF PWR 5 REF0/FSC/TEST_SEL I/O 3.3V tolerant input for CPU frequency selection/fixed 14.318MHz clock output. Selects test mode if pulled to VIHFS_C when CKPWRGD is asserted HIGH. Refer to DC Electrical Specifications table for VILFS_C, VIMFS_C, VIHFS_C specifications. 6 SMB_DATA I/O SMBus compatible SDATA. I 14.318MHz Crystal input or 3.3V, 14.318MHz input clock signal. 3.3V Power supply for outputs and also maintains SMBUS registers during power-down. 7 SMB_CLK 8 PCI0/OE#_0/2_A SMBus compatible SCLOCK. 9 VDD_PCI 10 PCI1/OE#_1/4_A I/O, SE 3.3V, 33MHz clock/3.3V OE# Input mappable via I2C to control either SRC1 or SRC4. (Default PCI1, 33MHz clock) 11 PCI2/TME I/O, SE 3.3V tolerance input for overclocking enable pin/3.3V, 33MHz clock. (Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications) I/O, SE 3.3V, 33MHz clock/3.3V OE# Input mappable via I2C to control either SRC0 or SRC2. (Default PCI0, 33MHz clock) PWR 3.3V Power supply for PCI PLL. 12 PCI3 O, SE, 33 MHz clock. 13 PCI4 / GCLK_SEL I/O, SE 33 MHz clock output/3.3V-tolerant input for selecting graphic clock source on pin 13, 14, 17and 18 Sampled on CKPWRGD assertion GCLK_SEL 14 PCIF_0/ITP_EN Pin13 Pin14 Pin17 Pin 18 0 DOT96T DOT96C SRC1T/LCD_100T SRC1C/LCD_100C 1 SRCT0 SRCC0 27M_NSS 27M_SS I/O, SE 3.3V LVTTL input to enable SRC8 or CPU2_ITP/33 MHz clock output. (sampled on the CK_PWRGD assertion) 1 = CPU2_ITP, 0 = SRC8 15 VSS_PCI GND Ground for outputs. 16 VDD_48 PWR 3.3V Power supply for outputs and PLL. 17 USB_48/FSA 18 VSS_48 GND Ground for outputs. 19 VDD_IO PWR 0.7V Power supply for outputs. 20 SRC0/DOT96 O, DIF 100MHz Differential serial reference clocks/Fixed 96MHz clock output. (Selected via I2C default is SRC0) 21 SRC0#/DOT96# O, DIF 100MHz Differential serial reference clocks/Fixed 96MHz clock output. (Selected via I2C default is SRC0) 22 VSS_IO GND Ground for PLL2. 23 VDD_PLL3 PWR 3.3V Power supply for PLL3 24 SRC1/LCD100/27_NSS O, DIF, True 100 MHz differential serial reference clock output/True 100 MHz LCD video SE clock output / Non-spread 27-MHz video clock output. Selected via GCLK_SEL at CKPWRGD assertion. 25 SRC1#/LCD100#27_SS O, DIF, Complementary 100 MHz differential serial reference clock output/Complementary SE 100 MHz LCD video clock output /Spread 27 MHz video clock output. Selected via GCLK_SEL at CKPWRGD assertion. 26 VSS_PLL3 I/O GND 3.3V tolerant input for CPU frequency selection/fixed 3.3V, 48MHz clock output. (Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications) Ground for PLL3. ........................ DOC #: SP-AP-0063 (Rev. AA) Page 3 of 31 SL28541 64 QFN Pin Definitions (continued) Pin No. 27 Name Type Description VDD_PLL3_IO PWR 28 SRC2/SATA O, DIF 100MHz Differential serial reference clocks. 29 SRC2#/SATA# O, DIF 100MHz Differential serial reference clocks. GND IO Power supply for PLL3 outputs. 30 VSS_SRC 31 SRC3/OE#_0/2_B I/O, Dif 100MHz Differential serial reference clocks / 3.3V OE#_0/2_B, input, mappable via I2C to control either SRC0 or SRC2. (Default SRC3, 100MHz clock) 32 SRC3#OE#_1/4_B I/O, Dif 100MHz Differential serial reference clocks / 3.3V OE#_1/4_B input, mappable via I2C to control either SRC1 or SRC4. (Default SRC3, 100MHz clock) 33 VDD_SRC_IO PWR 34 SRC4 O, DIF 100MHz Differential serial reference clocks. 35 SRC4# O, DIF 100MHz Differential serial reference clocks. 36 VSS_SRC 37 SRC9 O, DIF 100MHz Differential serial reference clocks. 38 SRC9# O, DIF 100MHz Differential serial reference clocks. 39 SRC11#/OE#_9 I/O, Dif 100MHz Differential serial reference clocks/3.3V OE#9 Input controlling SRC9 (Default SRC11, 100MHz clock) 40 SRC11/OE#_10 I/O, Dif 100MHz Differential serial reference clocks/3.3V OE#10 Input controlling SRC10. (Default SRC11, 100MHz clock) 41 SRC10 O, DIF 100MHz Differential serial reference clocks. 42 SRC10# O, DIF 100MHz Differential serial reference clocks. 43 VDD_SRC_IO GND PWR Ground for outputs. IO power supply for SRC outputs. Ground for outputs. IO Power supply for SRC outputs. 44 CPU_STP# I 3.3V tolerant input for stopping CPU outputs 45 PCI_STP# I 3.3V tolerant input for stopping PCI and SRC outputs 46 VDD_SRC PWR 47 SRC6# O, DIF 100MHz Differential serial reference clocks. 48 SRC6 O, DIF 100MHz Differential serial reference clocks. 49 VSS_SRC 50 SRC7#/OE#_6 I/O, Dif 100MHz Differential serial reference clocks/3.3V OE#6 Input controlling SRC6. (Default SRC7, 100MHz clock). 51 SRC7/OE#_8 I/O, Dif 100MHz Differential serial reference clocks/3.3V OE#8 Input controlling SRC8. (Default SRC7, 100MHz clock). 52 VDD_SRC_IO 53 SRC8#/CPU2#_ITP# GND PWR 3.3V Power supply for SRC PLL. Ground for outputs. 0.7V power supply for SRC outputs. O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 at CKPWRGD assertion = SRC8 ITP_EN = 1 @ CKPWRGD assertion = CPU2 (Note: CPU2 is an iAMT clock in iAMT mode depending on the configuration set in Byte 11 Bit3:2) 54 SRC8/CPU2_ITP O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 at CKPWRGD assertion = SRC8 ITP_EN = 1 @ CKPWRGD assertion = CPU2 (Note: CPU2 is an iAMT clock in iAMT mode depending on the configuration set in Byte 11 Bit3:2) 55 NC 56 VDD_CPU_IO 57 CPU1# NC PWR No Connect IO Power supply for CPU outputs. O, DIF Differential CPU clock outputs. (Note: CPU1 is an iAMT clock in iAMT mode depending on the configuration set in Byte 11 Bit3:2) 58 CPU1 O, DIF Differential CPU clock outputs. (Note: CPU1 is an iAMT clock in iAMT mode depending on the configuration set in Byte 11 Bit3:2) 59 VSS_CPU GND Ground for outputs. ........................ DOC #: SP-AP-0063 (Rev. AA) Page 4 of 31 SL28541 64 QFN Pin Definitions (continued) Pin No. Name Type Description 60 CPU#0 O, DIF Differential CPU clock outputs. 61 CPU0 O, DIF Differential CPU clock outputs. 62 VDD_CPU 63 CKPWRGD/PD# I 3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A, FS_B, FS_C, FS_D, SRC5_SEL, and ITP_EN. After CKPWRGD (active HIGH) assertion, this pin becomes a real-time input for asserting power down (active LOW). 64 FSB/TEST_MODE I 3.3V tolerant input for CPU frequency selection. Selects Ref/N or Tri-state when in test mode 0 = Tri-state, 1 = Ref/N. Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. PWR 3.3V Power supply for CPU PLL. 64 TSSOP Pin Definition Pin No. Name 1 PCI0/OE#_0/2_A Type Description I/O, SE 3.3V, 33MHz clock/3.3V OE# Input mappable via I2C to control either SRC0 or SRC2. (Default PCI0, 33MHz clock) 2 VDD_PCI 3 PCI1/OE#_1/4_A I/O, SE 3.3V, 33MHz clock/3.3V OE# Input mappable via I2C to control either SRC1 or SRC4. (Default PCI1, 33MHz clock) PWR 3.3V Power supply for PCI PLL. 4 PCI2/TME I/O, SE 3.3V tolerance input for overclocking enable pin/3.3V, 33MHz clock. (Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications) 5 PCI3 O, SE, 33 MHz clock. 6 PCI4 / GCLK_SEL I/O, SE 33 MHz clock output/3.3V-tolerant input for selecting graphic clock source on pin 13, 14, 17and 18 Sampled on CKPWRGD assertion GCLK_SEL 7 PCIF_0/ITP_EN 8 VSS_PCI GND 9 VDD_48 PWR 10 USB_48/FSA 11 VSS_48 Pin13 Pin14 Pin17 Pin 18 0 DOT96T DOT96C SRC1T/LCD_100T SRC1C/LCD_100C 1 SRCT0 SRCC0 27M_NSS 27M_SS I/O, SE 3.3V LVTTL input to enable SRC8 or CPU2_ITP/33 MHz clock output. (sampled on the CK_PWRGD assertion) 1 = CPU2_ITP, 0 = SRC8 I/O Ground for outputs. 3.3V Power supply for outputs and PLL. 3.3V tolerant input for CPU frequency selection/fixed 3.3V, 48MHz clock output. (Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications) GND Ground for outputs. PWR 0.7V Power supply for outputs. 12 VDD_IO 13 SRC0/DOT96 O, DIF 100MHz Differential serial reference clocks/Fixed 96MHz clock output. (Selected via I2C default is SRC0) 14 SRC0#/DOT96# O, DIF 100MHz Differential serial reference clocks/Fixed 96MHz clock output. (Selected via I2C default is SRC0) 15 VSS_IO GND Ground for PLL2. 16 VDD_PLL3 PWR 3.3V Power supply for PLL3 ........................ DOC #: SP-AP-0063 (Rev. AA) Page 5 of 31 SL28541 64 TSSOP Pin Definition (continued) Pin No. Name 17 SRC1/LCD100/27_NSS Type Description O, DIF, True 100 MHz differential serial reference clock output/True 100 MHz LCD video SE clock output / Non-spread 27-MHz video clock output. Selected via GCLK_SEL at CKPWRGD assertion. 18 SRC1#/LCD100#/27_SS O, DIF, Complementary 100 MHz differential serial reference clock output/Complementary SE 100 MHz LCD video clock output /Spread 27 MHz video clock output. Selected via GCLK_SEL at CKPWRGD assertion. 19 VSS_PLL3 GND Ground for PLL3. 20 VDD_PLL3_IO PWR IO Power supply for PLL3 outputs. 21 SRC2/SATA O, DIF 100MHz Differential serial reference clocks. 22 SRC2#/SATA# O, DIF 100MHz Differential serial reference clocks. 23 VSS_SRC 24 SRC3/OE#_0/2_B GND I/O, Dif 100MHz Differential serial reference clocks / 3.3V OE#_0/2_B, input, mappable via I2C to control either SRC0 or SRC2. (Default SRC3, 100MHz clock) 25 SRC3#OE#_1/4_B I/O, Dif 100MHz Differential serial reference clocks / 3.3V OE#_1/4_B input, mappable via I2C to control either SRC1 or SRC4. (Default SRC3, 100MHz clock) 26 VDD_SRC_IO PWR 27 SRC4 O, DIF 100MHz Differential serial reference clocks. 28 SRC4# O, DIF 100MHz Differential serial reference clocks. 29 VSS_SRC 30 SRC9 O, DIF 100MHz Differential serial reference clocks. 31 SRC9# O, DIF 100MHz Differential serial reference clocks. 32 SRC11#/OE#_9 I/O, Dif 100MHz Differential serial reference clocks/3.3V OE#9 Input controlling SRC9 (Default SRC11, 100MHz clock) 33 SRC11/OE#_10 I/O, Dif 100MHz Differential serial reference clocks/3.3V OE#10 Input controlling SRC10. (Default SRC11, 100MHz clock) 34 SRC10 O, DIF 100MHz Differential serial reference clocks. 35 SRC10# O, DIF 100MHz Differential serial reference clocks. 36 VDD_SRC_IO GND PWR Ground for outputs. IO power supply for SRC outputs. Ground for outputs. IO Power supply for SRC outputs. 37 CPU_STP# I 3.3V tolerant input for stopping CPU outputs 38 PCI_STP# I 3.3V tolerant input for stopping PCI and SRC outputs 39 VDD_SRC PWR 40 SRC6# O, DIF 100MHz Differential serial reference clocks. 41 SRC6 O, DIF 100MHz Differential serial reference clocks. 42 VSS_SRC 43 SRC7#/OE#_6 I/O, Dif 100MHz Differential serial reference clocks/3.3V OE#6 Input controlling SRC6. (Default SRC7, 100MHz clock). 44 SRC7/OE#_8 I/O, Dif 100MHz Differential serial reference clocks/3.3V OE#8 Input controlling SRC8. (Default SRC7, 100MHz clock). 45 VDD_SRC_IO 46 SRC8#/CPU2#_ITP# GND PWR 3.3V Power supply for SRC PLL. Ground for outputs. 0.7V power supply for SRC outputs. O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 at CKPWRGD assertion = SRC8 ITP_EN = 1 @ CKPWRGD assertion = CPU2 (Note: CPU2 is an iAMT clock in iAMT mode depending on the configuration set in Byte 11 Bit3:2) 47 SRC8/CPU2_ITP O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 at CKPWRGD assertion = SRC8 ITP_EN = 1 @ CKPWRGD assertion = CPU2 (Note: CPU2 is an iAMT clock in iAMT mode depending on the configuration set in Byte 11 Bit3:2) ........................ DOC #: SP-AP-0063 (Rev. AA) Page 6 of 31 SL28541 64 TSSOP Pin Definition (continued) Pin No. 48 NC Name 49 VDD_CPU_IO 50 CPU1# Type NC No Connect Description PWR IO Power supply for CPU outputs. O, DIF Differential CPU clock outputs. (Note: CPU1 is an iAMT clock in iAMT mode depending on the configuration set in Byte 11 Bit3:2) 51 CPU1 O, DIF Differential CPU clock outputs. (Note: CPU1 is an iAMT clock in iAMT mode depending on the configuration set in Byte 11 Bit3:2) 52 VSS_CPU 53 CPU#0 O, DIF Differential CPU clock outputs. GND 54 CPU0 O, DIF Differential CPU clock outputs. 55 VDD_CPU 56 CKPWRGD/PD# I 3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A, FS_B, FS_C, FS_D, SRC5_SEL, and ITP_EN. After CKPWRGD (active HIGH) assertion, this pin becomes a real-time input for asserting power down (active LOW). 57 FSB/TEST_MODE I 3.3V tolerant input for CPU frequency selection. Selects Ref/N or Tri-state when in test mode 0 = Tri-state, 1 = Ref/N. Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. 58 VSS_REF GND 59 XOUT O, SE 14.318MHz Crystal output. (Float XOUT if using CLKIN) 60 XIN/CLKIN I 61 VDD_REF PWR 62 REF0/FSC/TEST_SEL I/O 3.3V tolerant input for CPU frequency selection/fixed 14.318MHz clock output. Selects test mode if pulled to VIHFS_C when CKPWRGD is asserted HIGH. Refer to DC Electrical Specifications table for VILFS_C, VIMFS_C, VIHFS_C specifications. 63 SMB_DATA I/O SMBus compatible SDATA. 64 SMB_CLK I PWR Ground for outputs. 3.3V Power supply for CPU PLL. Ground for outputs. 14.318MHz Crystal input or 3.3V, 14.318MHz input clock signal. 3.3V Power supply for outputs and also maintains SMBUS registers during power-down. SMBus compatible SCLOCK. Table 1. Frequency Select Pin (FSA, FSB and FSC) FSC FSB FSA CPU 0 0 0 266 MHz 0 0 1 133 MHz 0 1 0 200 MHz 0 1 1 166 MHz 1 0 0 333 MHz 1 0 1 100 MHz 1 1 0 400 MHz 1 1 1 Reserved SRC PCIF/PCI 27MHz REF DOT96 USB 100 MHz 33 MHz 27 MHz 14.318 MHz 96 MHz 48 MHz Reserved Reserved Reserved Reserved Reserved Reserved Frequency Select Pin (FSA, FSB and FSC) Apply the appropriate logic levels to FSA, FSB, and FSC inputs before CKPWRGD assertion to achieve host clock frequency selection. When the clock chip sampled HIGH on CKPWRGD and indicates that VTT voltage is stable then FSA, FSB, and FSC input values are sampled. This process ........................ DOC #: SP-AP-0063 (Rev. AA) Page 7 of 31 employs a one-shot functionality and once the CKPWRGD sampled a valid HIGH, all other FSA, FSB, FSC, and CKPWRGD transitions are ignored except in test mode. Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual SL28541 clock output buffers are individually enabled or disabled. The registers associated with the Serial Data Interface initialize to their default setting at power-up. The use of this interface is optional. Clock device register changes are normally made at system initialization, if any are required. The interface cannot be used during system operation for power management functions. Data Protocol block write/read operation, access the bytes in sequential order from lowest to highest (most significant bit first) with the ability to stop after any complete byte is transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code described in Table 2. The block write and block read protocol is outlined in Table 3 while Table 4 outlines byte write and byte read protocol. The slave receiver address is 11010010 (D2h). The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For . Table 2. Command Code Definition Bit 7 Description 0 = Block read or block write operation, 1 = Byte read or byte write operation (6:0) Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000' Table 3. Block Read and Block Write Protocol Block Write Protocol Bit 1 8:2 Description Start Block Read Protocol Bit 1 Slave address–7 bits 8:2 Description Start Slave address–7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 18:11 19 27:20 28 36:29 37 45:38 46 Command Code–8 bits Acknowledge from slave Byte Count–8 bits 18:11 19 20 Acknowledge from slave 27:21 Command Code–8 bits Acknowledge from slave Repeat start Slave address–7 bits Data byte 1–8 bits 28 Read = 1 Acknowledge from slave 29 Acknowledge from slave Data byte 2–8 bits 37:30 Acknowledge from slave .... Data Byte /Slave Acknowledges .... Data Byte N–8 bits 38 46:39 47 .... Acknowledge from slave .... Stop 55:48 Byte Count from slave–8 bits Acknowledge Data byte 1 from slave–8 bits Acknowledge Data byte 2 from slave–8 bits 56 Acknowledge .... Data bytes from slave / Acknowledge .... Data Byte N from slave–8 bits .... NOT Acknowledge .... Stop Table 4. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 8:2 9 10 18:11 19 Description Start Slave address–7 bits Write Acknowledge from slave Command Code–8 bits Acknowledge from slave ........................ DOC #: SP-AP-0063 (Rev. AA) Page 8 of 31 Byte Read Protocol Bit 1 8:2 9 10 18:11 19 Description Start Slave address–7 bits Write Acknowledge from slave Command Code–8 bits Acknowledge from slave SL28541 Table 4. Byte Read and Byte Write Protocol 27:20 Data byte–8 bits 20 28 Acknowledge from slave 29 Stop 27:21 28 29 37:30 Repeated start Slave address–7 bits Read Acknowledge from slave Data from slave–8 bits 38 NOT Acknowledge 39 Stop Control Registers Byte 0: Control Register 0 Bit @Pup Name Description 7 HW FS_C CPU Frequency Select Bit, set by HW 6 HW FS_B CPU Frequency Select Bit, set by HW 5 HW FS_A 4 0 iAMT_EN Set via SMBus or by combination of PWRDWN, CPU_STP, and PCI_STP 0 = Legacy Mode, 1 = iAMT Enabled 3 0 Reserved Reserved 2 0 SRC_Main_SEL 1 0 SATA_SEL Select source of SATA clock 0 = SATA = SRC_MAIN, 1= SATA = PLL2 0 1 PD_Restore Save configuration when PD# is asserted 0 = Config. cleared, 1 = Config. saved CPU Frequency Select Bit, set by HW Select source for SRC clock 0 = SRC_MAIN = PLL1, PLL3_CFG Table applies 1 = SRC_MAIN = PLL3, PLL3_CFG Table does not apply Byte 1: Control Register 1 Bit @Pup Name 7 0 SRC0_SEL Description 6 0 PLL1_SS_DC Select for down or center SS 0 = Down spread, 1 = Center spread 5 0 PLL3_SS_DC Select for down or center SS 0 = Down spread, 1 = Center spread 4 0 PLL3_CFB3 3 0 PLL3_CFB2 2 1 PLL3_CFB1 1 0 PLL3_CFB0 0 1 Reserved Select for SRC0 or DOT96 0 = SRC0, 1 = DOT96 When GCLK_SEL=0, this bit is 1. When GCLK_SEL=1, this bit is 0 Bit 4:1 only applies when SRC_Main_SEL = 0 SeeTable 8: PLL3 / SE configuration table Reserved Byte 2: Control Register 2 Bit @Pup Name Description 7 1 REF Output enable for REF 0 = Output Disabled, 1 = Output Enabled 6 1 USB Output enable for USB 0 = Output Disabled, 1 = Output Enabled 5 1 PCIF0 Output enable for PCIF0 0 = Output Disabled, 1 = Output Enabled ........................ DOC #: SP-AP-0063 (Rev. AA) Page 9 of 31 SL28541 Byte 2: Control Register 2 (continued) Bit @Pup Name Description 4 1 PCI4 Output enable for PCI4 0 = Output Disabled, 1 = Output Enabled 3 1 PCI3 Output enable for PCI3 0 = Output Disabled, 1 = Output Enabled 2 1 PCI2 Output enable for PCI2 0 = Output Disabled, 1 = Output Enabled 1 1 PCI1 Output enable for PCI1 0 = Output Disabled, 1 = Output Enabled 0 1 PCI0 Output enable for PCI0 0 = Output Disabled, 1 = Output Enabled Byte 3: Control Register 3 Bit @Pup Name Description 7 1 SRC[T/C]11 Output enable for SRC11 0 = Output Disabled, 1 = Output Enabled 6 1 SRC[T/C]10 Output enable for SRC10 0 = Output Disabled, 1 = Output Enabled 5 1 SRC[T/C]9 Output enable for SRC9 0 = Output Disabled, 1 = Output Enabled 4 1 SRC[T/C]8/CPU2_ITP Output enable for SRC8 or CPU2_ITP 0 = Output Disabled, 1 = Output Enabled 3 1 SRC[T/C]7 Output enable for SRC7 0 = Output Disabled, 1 = Output Enabled 2 1 SRC[T/C]6 Output enable for SRC6 0 = Output Disabled, 1 = Output Enabled 1 1 Reserved Reserved 0 1 SRC[T/C]4 Output enable for SRC4 0 = Output Disabled, 1 = Output Enabled Byte 4: Control Register 4 Bit @Pup Name Description 7 1 SRC[T/C]3 Output enable for SRC3 0 = Output Disabled, 1 = Output Enabled 6 1 SRC[T/C]2/SATA Output enable for SRC2/SATA 0 = Output Disabled, 1 = Output Enabled 5 1 4 1 SRC[T/C]0/DOT96[T/C] Output enable for SRC0/DOT96 0 = Output Disabled, 1 = Output Enabled 3 1 CPU[T/C]1 Output enable for CPU1 0 = Output Disabled, 1 = Output Enabled 2 1 CPU[T/C]0 Output enable for CPU0 0 = Output Disabled, 1 = Output Enabled 1 1 PLL1_SS_EN Enable PLL1s spread modulation, 0 = Spread Disabled, 1 = Spread Enabled 0 1 PLL3_SS_EN Enable PLL3s spread modulation 0 = Spread Disabled, 1 = Spread Enabled SRC[T/C]1/LCD_100M[T/C] Output enable for SRC1/LCD_100M 0 = Output Disabled, 1 = Output Enabled ...................... DOC #: SP-AP-0063 (Rev. AA) Page 10 of 31 SL28541 Byte 5: Control Register 5 Bit @Pup Name 7 0 CR#_A_EN Enable CR#_A (clk req) 0 = Disabled, 1 = Enabled, Description 6 0 CR#_A_SEL Set CR#_A  SRC0 or SRC2 0 = CR#_ASRC0, 1 = CR#_ASRC2 5 0 CR#_B_EN Enable CR#_B(clk req) 0 = Disabled, 1 = Enabled, 4 0 CR#_B_SEL Set CR#_B  SRC1 or SRC4 0 = CR#_BSRC1, 1 = CR#_BSRC4 3 0 CR#_C_EN Enable CR#_C (clk req) 0 = Disabled, 1 = Enabled 2 0 CR#_C_SEL Set CR#_C  SRC0 or SRC2 0 = CR#_CSRC0, 1 = CR#_CSRC2 1 0 CR#_D_EN Enable CR#_D (clk req) 0 = Disabled, 1 = Enabled 0 0 CR#_D_SEL Set CR#_D SRC1 or SRC4 0 = CR#_DSRC1, 1 = CR#_DSRC4 Byte 6: Control Register 6 Bit @Pup Name 7 0 CR#_E_EN Enable CR#_E (clk req)  SRC6 0 = Disabled, 1 = Enabled Description 6 0 CR#_F_EN Enable CR#_F (clk req)  SRC8 0 = Disabled, 1 = Enabled 5 0 CR#_G_EN Enable CR#_G (clk req)  SRC9 0 = Disabled, 1 = Enabled 4 0 CR#_H_EN Enable CR#_H (clk req)  SRC10 0 = Disabled, 1 = Enabled 3 0 Reserved Reserved 2 0 Reserved Reserved 1 0 LCD_100_STP_CTRL If set, LCD_100 stop with PCI_STP# 0 = Free running, 1 = PCI_STP# stoppable 0 0 SRC_STP_CTRL If set, SRCs stop with PCI_STP# 0 = Free running, 1 = PCI_STP# stoppable Byte 7: Vendor ID Bit @Pup Name Description 7 0 Rev Code Bit 3 Revision Code Bit 3 6 0 Rev Code Bit 2 Revision Code Bit 2 5 0 Rev Code Bit 1 Revision Code Bit 1 4 1 Rev Code Bit 0 Revision Code Bit 0 3 1 Vendor ID bit 3 Vendor ID Bit 3 2 0 Vendor ID bit 2 Vendor ID Bit 2 1 0 Vendor ID bit 1 Vendor ID Bit 1 0 0 Vendor ID bit 0 Vendor ID Bit 0 ...................... DOC #: SP-AP-0063 (Rev. AA) Page 11 of 31 SL28541 Byte 8: Control Register 8 Bit @Pup Name 7 1 Device_ID3 Description 6 0 Device_ID2 5 0 Device_ID1 4 0 Device_ID0 3 0 Reserved Reserved 2 0 Reserved Reserved 1 1 27M_NSS_OE Output enable for 27M_NSS 0 = Output Disabled, 1 = Output Enabled 0 1 27M_SS_OE Output enable for 27M_SS 0 = Output Disabled, 1 = Output Enabled 0000 = CK505 Yellow Cover Device, 56-pin TSSOP 0001 = CK505 Yellow Cover Device, 64-pin TSSOP 0010 = CK505 Yellow Cover Device, 48-pin QFN (Reserved) 0011 = CK505 Yellow Cover Device, 56-pin QFN (Reserved) 0100 = CK505 Yellow Cover Device, 64-pin QFN 0101 = CK505 Yellow Cover Device, 72-pin QFN (Reserved) 0110 = CK505 Yellow Cover Device, 48-pin SSOP (Reserved) 0111 = CK505 Yellow Cover Device, 48-pin SSOP (Reserved) 1000 = Reserved 1001 = CY28548 1010 = Reserved 1011 = Reserved 1100 = Reserved 1101 = Reserved 1110 = Reserved 1111 = Reserved Byte 9: Control Register 9 Bit @Pup Name 7 0 PCIF_0_with PCI_STP# Description 6 HW TME_STRAP 5 1 REF_DSC1 4 0 TEST_MODE_SEL Mode select either REF/N or tri-state 0 = All output tri-state, 1 = All output REF/N 3 0 TEST_MODE_ENTRY Allow entry into test mode 0 = Normal operation, 1 = Enter test mode 2 1 I2C_VOUT 1 0 I2C_VOUT 0 1 I2C_VOUT Allows control of PCIF_0 with assertion of PCI_STP# 0 = Free running PCIF, 1 = Stopped with PCI_STP# Trusted mode enable strap status 0 = Normal, 1 = No overclocking REF drive strength 1 of 2 (See Byte 17 and 18 for more setting) 0 = Low, 1 = High Differential Amplitude Configuration I2C_VOUT[2,1,0] 000 = 0.63V 001 = 0.71V 010 = 0.77V 011 = 082V 100 = 0.86V 101 = 0.90V (default) 110 = 0.93V 111 = unused Byte 10: Control Register 10 Bit @Pup Name 7 HW GCLK_SEL latch 6 1 PLL3_EN Description Readback of GCLK_SEL latch 0 = DOT96/LCD_100, 1 = SRC0/27 MHz PLL3 power down 0 = Power down, 1 = Power up ...................... DOC #: SP-AP-0063 (Rev. AA) Page 12 of 31 SL28541 Byte 10: Control Register 10 (continued) Bit @Pup Name Description 5 1 PLL2_EN 4 1 SRC_DIV_EN SRC divider disable 0 = Disabled, 1 = Enabled 3 1 PCI_DIV_EN PCI divider disable 0 = Disabled, 1 = Enabled 2 1 CPU_DIV_EN CPU divider disable 0 = Disabled, 1 = Enabled 1 1 CPU1 Stop Enable Enable CPU_STP# control of CPU1 0 = Free running, 1= Stoppable 0 1 CPU0 Stop Enable Enable CPU_STP# control of CPU0 0 = Free running, 1= Stoppable PLL2 power down 0 = Power down, 1 = Power up Byte 11: Control Register 11 Bit @Pup Name Description 7 0 Reserved Reserved 6 0 Reserved Reserved 5 0 Reserved Reserved 4 0 Reserved Reserved 3 0 Reserved Reserved 2 0 Reserved Reserved 1 0 Reserved Reserved 0 0 Reserved Reserved Byte 12: Byte Count Bit @Pup Name 7 0 Reserved 6 0 Reserved 5 0 BC5 4 1 BC4 3 0 BC3 2 0 BC2 1 1 BC1 0 1 BC0 Description Reserved Reserved Byte count register for block read operation. The default value for Byte count is 19. In order to read beyond Byte 19, the user should change the byte count limit.to or beyond the byte that is desired to be read. Byte 13: Control Register 13 Bit @Pup Name 7 1 USB_BIT1 Description 6 1 PCI/ PCIF_BIT1 5 0 PLL1_Spread Select percentage of spread for PLL1 0 = 0.5%, 1=1% 4 1 SATA_SS_EN Enable SATA spread modulation, 0 = Spread Disabled, 1 = Spread Enabled 3 1 CPU[T/C]2 USB drive strength 1 of 3(See Byte 17 for more setting) 0 = Low, 1= High PCI drive strength 1 of 3(See Byte 17 & 18 for more setting) 0 = Low, 1 = High Allow control of CPU2 with assertion of CPU_STP# 0 = Free running, 1 = Stopped with CPU_STP# ...................... DOC #: SP-AP-0063 (Rev. AA) Page 13 of 31 SL28541 Byte 13: Control Register 13 (continued) Bit @Pup Name Description 2 1 SE1/SE2_BIT_1 SE1 and SE2 Drive Strength Setting 1 of 3 (See Byte 17 and 18 for more setting) 0 = Low, 1= High 1 1 Reserved Reserved 0 1 SW_PCI SW PCI_STP# Function 0 = SW PCI_STP assert, 1 = SW PCI_STP deassert When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs are stopped in a synchronous manner with no short pulses. When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs are resumed in a synchronous manner with no short pulses. Byte 14: Control Register 14 Bit @Pup Name Description 7 0 CPU_DAF_N7 6 0 CPU_DAF_N6 If Prog_CPU_EN is set, the values programmed in CPU_DAF_N[8:0] and CPU_DAF_M[6:0] are used to determine the CPU output frequency. 5 0 CPU_DAF_N5 4 0 CPU_DAF_N4 3 0 CPU_DAF_N3 2 0 CPU_DAF_N2 1 0 CPU_DAF_N1 0 0 CPU_DAF_N0 Byte 15: Control Register 15 Bit @Pup Name Description 7 0 CPU_DAF_N8 See Byte 14 for description 6 0 CPU_DAF_M6 5 0 CPU_DAF_M5 If Prog_CPU_EN is set, the values programmed in CPU_DAF_N[8:0] and CPU_DAF_M[6:0] are used to determine the CPU output frequency. 4 0 CPU_DAF_M4 3 0 CPU_DAF_M3 2 0 CPU_DAF_M2 1 0 CPU_DAF_M1 0 0 CPU_DAF_M0 Byte 16: Control Register 16 Bit @Pup Name Description Dial-A-Frequency® 7 0 PCI-E_N7 PCI-E 6 0 PCI-E_N6 PCI-E Dial-A-Frequency Bit N6 5 0 PCI-E_N5 PCI-E Dial-A-Frequency Bit N5 4 0 PCI-E_N4 PCI-E Dial-A-Frequency Bit N4 3 0 PCI-E_N3 PCI-E Dial-A-Frequency Bit N3 2 0 PCI-E_N2 PCI-E Dial-A-Frequency Bit N2 1 0 PCI-E_N1 PCI-E Dial-A-Frequency Bit N1 0 0 PCI-E_N0 PCI-E Dial-A-Frequency Bit N0 ...................... DOC #: SP-AP-0063 (Rev. AA) Page 14 of 31 Bit N7 SL28541 Byte 17: Control Register 17 Bit @Pup Name 7 0 SMSW_EN Enable Smooth Switching 0 = Disabled, 1= Enabled Description 6 0 SMSW_SEL Smooth switch select 0 = CPU_PLL, 1 = SRC_PLL 5 0 SE1/SE2_BIT0 SE1 and SE2 drive strength Setting 2 of 3(see Byte 18 for more setting) 0 = Low, 1= High 4 0 Prog_PCI-E_EN Programmable PCI-E frequency enable 0 = Disabled, 1= Enabled 3 0 Prog_CPU_EN Programmable CPU frequency enable 0 = Disabled, 1= Enabled 2 0 REF_BIT0 REFdrive strength strength Setting 2 of 3(see Byte 18 for more setting) 0 = Low, 1= High 1 0 USB_BIT0 USB drive strength strength Setting 2 of 3(see Byte 18 for more setting) 0 = Low, 1= High 0 0 PCI/ PCIF_BIT0 PCI drive strength strength Setting 2 of 3(see Byte 18 for more setting) 0 = Low, 1= High Byte 18: Control Register 18 7 0 REF_BIT2 6 0 RESERVED 5 1 RESERVED 4 0 RESERVED Drive Strength Control 3 0 USB_BIT2 1 BIT_0 (Byte 17) 1 2 0 PCI/PCIF_BIT2 1 1 0 1 0 SE1/SE2_BIT2 1 0 1 RESERVED 1 0 0 0 1 1 0 1 0 0 0 1 0 0 Def ault BIT_2 (Byte18) 1 (Vario us B ytes ) BIT_1 Buf f er Strength Strongest Table 5. Output Driver Status during PCI-STP# and CPU-STP# PCI_STP# Asserted Single-ended Clocks Stoppable Differential Clocks CPU_STP# Asserted Driven low Running Non stoppable Running Running Stoppable Clock driven high Clock driven high Non stoppable Clock# driven low Clock# driven low Running Running SMBus OE Disabled Driven low Clock driven Low or 20K pulldown Table 6. Output Driver Status All Single-ended Clocks w/o Strap All Differential Clocks except CPU1 w/ Strap Clock Clock# CPU1 Clock Clock# Latches Open State Low Hi-z Low or 20K pulldown Low Low or 20K pulldown Low Powerdown Low Hi-z Low or 20K pulldown Low Low or 20K pulldown Low M1 Low Hi-z Low or 20K pulldown Low Running ...................... DOC #: SP-AP-0063 (Rev. AA) Page 15 of 31 Running SL28541 Table 7. PLL3/SE Configuration Table GCLK_SEL B1b4 B1b3 B1b2 B1b1 0 0 0 0 0 Pin 24 (17) MHz Pin 25 (18) MHz Spread (%) 0 0 0 0 1 100 100 0.5 SRC1 from SRC_Main 0 0 0 1 0 100 100 0.5 LCD_100 from PLL3 0 0 0 1 1 100 100 1 LCD_100 from PLL3 0 0 1 0 0 100 100 1.5 LCD_100 from PLL3 0 0 1 0 1 100 100 2 LCD_100 from PLL3 0 0 1 1 0 N/A N/A N/A N/A 0 0 1 1 1 N/A N/A N/A N/A 0 1 0 0 0 N/A N/A N/A N/A 0 1 0 0 1 N/A N/A N/A N/A 0 1 0 1 0 N/A N/A N/A N/A 0 1 0 1 1 N/A N/A N/A N/A 0 1 1 0 0 N/A N/A none N/A 0 1 1 0 1 N/A N/A N/A N/A 0 1 1 1 0 N/A N/A N/A N/A 0 1 1 1 1 N/A N/A N/A N/A 1 0 0 0 0 N/A N/A N/A 1 0 0 0 1 27M_NSS 27M_SS 0.5 1 0 0 1 0 27M_NSS 27M_SS 0.5 27M_SS from PLL3 1 0 0 1 1 27M_NSS 27M_SS 1 27M_SS from PLL3 1 0 1 0 0 27M_NSS 27M_SS 1.5 27M_SS from PLL3 1 0 1 0 1 27M_NSS 27M_SS 2 27M_SS from PLL3 1 0 1 1 0 N/A N/A N/A 1 0 1 1 1 N/A N/A N/A 1 1 0 0 0 N/A N/A N/A 1 1 0 0 1 N/A N/A N/A 1 1 0 1 0 N/A N/A N/A 1 1 0 1 1 N/A N/A N/A 1 1 1 0 0 N/A N/A N/A 1 1 1 0 1 N/A N/A N/A Dial-A-Frequency® (CPU and SRC Clocks) This feature allows the user to over-clock their system by slowly stepping up the CPU or SRC frequency. When the programmable output frequency feature is enabled, the CPU and SRC frequencies are determined by the following equation: Fcpu = G * N/M or Fcpu=G2 * N, where G2 = G / M. • “N” and “M” are the values programmed in Programmable Frequency Select N-Value Register and M-Value Register, respectively. • “G” stands for the PLL Gear Constant, which is determined by the programmed value of FS[E:A]. See Table 1, Frequency Select Table for the Gear Constant for each Frequency selection. The PCI Express only allows user ...................... DOC #: SP-AP-0063 (Rev. AA) Page 16 of 31 Comment PLL3 Disabled 27M_SS from PLL3 control of the N register, the M value is fixed and documented in Table 1, Frequency Select Table. In this mode, the user writes the desired N and M values into the DAF I2C registers. The user cannot change only the M value and must change both the M and the N values at the same time, if they require a change to the M value. The user may change only the N value. Associated Register Bits • CPU_DAF Enable – This bit enables CPU DAF mode. By default, it is not set. When set, the operating frequency is determined by the values entered into the CPU_DAF_N register. Note that the CPU_DAF_N and M register must contain valid values before CPU_DAF is set. Default = 0, (No DAF). • CPU_DAF_N – There are nine bits (for 512 values) to linearly change the CPU frequency (limited by VCO range). SL28541 Default = 0, (0000). The allowable values for N are detailed in Table 1, Frequency Select Table. • CPU DAF M – There are 7 bits (for 128 values) to linearly change the CPU frequency (limited by VCO range). Default = 0, the allowable values for M are detailed in Table 1, Frequency Select Table • SRC_DAF Enable – This bit enables SRC DAF mode. By default, it is not set. When set, the operating frequency is determined by the values entered into the SRC_DAF_N register. Note that the SRC_DAF_N register must contain valid values before SRC_DAF is set. Default = 0, (No DAF). • SRC_DAF_N – There are nine bits (for 512 values) to linearly change the CPU frequency (limited by VCO range). Default = 0, (0000). The allowable values for N are detailed in Table 1, Frequency Select Table. Smooth Switching The device contains one smooth switch circuit that is shared by the CPU PLL and SRC PLL. The smooth switch circuit ensures that when the output frequency changes by overclocking, the transition from the old frequency to the new frequency is a slow, smooth transition containing no glitches. The rate of change of output frequency when using the smooth switch circuit is less than 1 MHz/0.667 s. The frequency overshoot and undershoot is less than 2%. The Smooth Switch circuit assigns auto or manual. In Auto mode, clock generator assigns smooth switch automatically when the PLL does overclocking. For manual mode, assign the smooth switch circuit to PLL via Smbus. By default the smooth switch circuit is set to auto mode. PLL can be over-clocked when it does not have control of the smooth switch circuit but it is not guaranteed to transition to the new frequency without large frequency glitches. Do not enable over-clocking and change the N values of both PLLs in the same SMBUS block write and use smooth switch mechanism on spread spectrum on/off. PD_RESTORE If a ‘0’ is set for Byte 0 bit 0 then, upon assertion of PD# LOW, the SL28541 initiates a full reset. The result of this is that the clock chip emulates a cold power on start and goes to the “Latches Open” state. If the PD_RESTORE bit is set to a ‘1’ then the configuration is stored upon PD# asserted LOW. Note that if the iAMT bit, Byte 0 bit 3, is set to a ‘1’ then the PD_RESTORE bit must be ignored. In other words, in Intel iAMT mode, PD# reset is not allowed. PD# (Power down) Clarification The CKPWRGD/PD# pin is a dual-function pin. During initial power up, the pin functions as CKPWRGD. Once CKPWRGD has been sampled HIGH by the clock chip, the pin assumes PD# functionality. The PD# pin is an asynchronous active LOW input used to shut off all clocks cleanly before shutting off power to the device. This signal is synchronized internally to the device before powering down the clock synthesizer. PD# is also an asynchronous input for powering up the system. When PD# is asserted LOW, clocks are driven to a LOW value and held before turning off the VCOs and the crystal oscillator. PD# (Power down) Assertion When PD is sampled HIGH by two consecutive rising edges of CPUC, all single-ended outputs will be held LOW on their next HIGH-to-LOW transition and differential clocks must held LOW. When PD mode is desired as the initial power on state, PD must be asserted HIGH in less than 10 s after asserting CKPWRGD. PD# Deassertion The power up latency is less than 1.8 ms. This is the time from the deassertion of the PD# pin or the ramping of the power supply until the time that stable clocks are generated from the clock chip. All differential outputs stopped in a three-state condition, resulting from power down are driven high in less than 300 s of PD# deassertion to a voltage greater than 200 mV. After the clock chip’s internal PLL is powered up and locked, all outputs are enabled within a few clock cycles of each clock. Figure 2 is an example showing the relationship of clocks coming up. PD# CPUT, 133MHz CPUC, 133MHz SRCT 100MHz SRCC 100MHz USB, 48MHz DOT96T DOT96C PCI, 33 MHz REF Figure 1. Power down Assertion Timing Waveform ...................... DOC #: SP-AP-0063 (Rev. AA) Page 17 of 31 SL28541 Ts ta b le < 1 .8 m s PD# C P U T , 1 3 3 MH z C P U C , 1 3 3 MH z S R C T 1 0 0 MH z S R C C 1 0 0 MH z U S B , 4 8 MH z D OT 9 6 T D OT 9 6 C P C I, 3 3 MH z Td r iv e _ PW R D N # 2 00m V REF Figure 2. Power down Deassertion Timing Waveform FS _A, FS _B ,FS_C ,FS _D CKPWRGD P W R G D _V R M 0.2-0.3 m s D elay V D D C lock G en C lock S tate C lock O utputs C lock V C O S tate 0 W ait for V TT_PW R G D # S tate 1 D evice is not affected, V TT_P W R G D # is ignored S am ple S els State 2 O ff State 3 On On O ff Figure 3. CKPWRGD Timing Diagram CPU_STP# Assertion The CPU_STP# signal is an active LOW input used for synchronous stopping and starting the CPU output clocks while the rest of the clock generator continues to function. When the CPU_STP# pin is asserted, all CPU outputs that are set with the SMBus configuration to be stoppable are stopped within two to six CPU clock periods after sampled by two rising edges of the internal CPUC clock. The final states of the stopped CPU signals are CPUT = HIGH and CPUC = LOW. CPU_STP# Deassertion The deassertion of the CPU_STP# signal causes all stopped CPU outputs to resume normal operation in a synchronous manner. No short or stretched clock pulses are produced when the clock resumes. The maximum latency from the deassertion to active outputs is no more than two CPU clock cycles. CPU_STP# CPUT CPUC Figure 4. CPU_STP# Assertion Waveform ...................... DOC #: SP-AP-0063 (Rev. AA) Page 18 of 31 SL28541 CPU_STP# CPUT CPUC CPUT Internal CPUC Internal Tdrive_CPU_STP#,10 ns>200 mV Figure 5. CPU_STP# Deassertion Waveform PCI_STP# Assertion The PCI_STP# signal is an active LOW input used for synchronously stopping and starting the PCI outputs while the rest of the clock generator continues to function. The set-up time for capturing PCI_STP# going LOW is 10 ns (tSU). (See Figure 6.) The PCIF clocks are affected by this pin if their corresponding control bit in the SMBus register is set to allow them to be free running. T su PC I_STP# PC I_F PC I SR C 100M H z Figure 6. PCI_STP# Assertion Waveform . PCI_STP# Deassertion The deassertion of the PCI_STP# signal causes all PCI and stoppable PCIF clocks to resume running in a synchronous manner within two PCI clock periods, after PCI_STP# transitions to a HIGH level. T su T drive_ S R C P C I_S T P # P C I_F PCI SR C 100 M H z Figure 7. PCI_STP# Deassertion Waveform . . ...................... DOC #: SP-AP-0063 (Rev. AA) Page 19 of 31 SL28541 Figure 8. Clock Generator Power up/Run State Diagram Clock Off to M 1 3.3V Vcc 2.0V FSC T_delay t CPU_STP# FSB FSA PCI_STP# CKPWRGD/PD# Off CK505 SMBUS CK505 State Latches Open Off M1 BSEL[0..2] CK505 Core Logic Off PLL1 Locked CPU1 PLL2 & PLL3 All Other Clocks REF Oscillator T_delay2 T_delay3 Figure 9. BSEL Serial Latching ...................... DOC #: SP-AP-0063 (Rev. AA) Page 20 of 31 SL28541 Absolute Maximum Conditions Parameter Description Condition VDD_3.3V Supply Voltage Functional VDD_IO IO Supply Voltage Functional VIN Input Voltage Relative to VSS TS Temperature, Storage Non-functional TA Commercial Temperature, Operating Ambient Functional Min. Max. – Industrial Temperature, Operating Ambient Unit 4.6 V 3.465 V –0.5 4.6 VDC –65 150 °C 0 85 °C -40 +85 °C TJ Temperature, Junction Functional – 150 °C ØJC Dissipation, Junction to Case JEDEC (JESD 51) – 20 °C/W ØJA Dissipation, Junction to Ambient JEDEC (JESD 51) – 60 °C/ W ESDHBM ESD Protection (Human Body Model) JEDEC (JESD 22-A114) 2000 – V UL-94 Flammability Rating UL (CLASS) MSL Moisture Sensitivity Level V–0 1 Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. DC Electrical Specifications Parameter Description VDD core 3.3V Operating Voltage Condition 3.3 ± 5% Min. Max. Unit 3.135 3.465 V VIH 3.3V Input High Voltage (SE) 2.0 VDD + 0.3 V VIL 3.3V Input Low Voltage (SE) VSS – 0.3 0.8 V VIHI2C Input High Voltage SDATA, SCLK 2.2 – V VILI2C Input Low Voltage SDATA, SCLK – 1.0 V VIH_FS FS_[A,B] Input High Voltage 0.7 1.5 V VIL_FS FS_[A,B] Input Low Voltage VSS – 0.3 0.35 V VIHFS_C_TEST FS_C Input High Voltage VIMFS_C_NORMAL FS_C Input Middle Voltage VILFS_C_NORMAL FS_C Input Low Voltage IIH Input High Leakage Current Except internal pull-down resistors, 0 < VIN < VDD Except internal pull-up resistors, 0 < VIN < VDD IIL Input Low Leakage Current VOH 3.3V Output High Voltage (SE) IOH = –1 mA VOL 3.3V Output Low Voltage (SE) VDD IO Low Voltage IO Supply Voltage IOZ IOL = 1 mA 2 VDD + 0.3 V 0.7 1.5 V VSS – 0.3 0.35 V – 5 A –5 – A 2.4 – V – 0.4 V 1 3.465 V High-impedance Output Current –10 10 A CIN Input Pin Capacitance 1.5 5 pF COUT Output Pin Capacitance 6 pF LIN Pin Inductance – 7 nH VXIH Xin High Voltage 0.7VDD VDD V VXIL Xin Low Voltage 0 0.3VDD V IDDPWRDWN Power Down Current 1 mA IDD Dynamic Supply Current 250 mA ...................... DOC #: SP-AP-0063 (Rev. AA) Page 21 of 31 – SL28541 AC Electrical Specifications Parameter Description Condition Min. Max. Unit – 300 ppm Crystal LACC Long-term Accuracy Clock Input TDC CLKIN Duty Cycle Measured at VDD/2 47 53 % TR/TF CLKIN Rise and Fall Times Measured between 0.2VDD and 0.8VDD 0.5 4.0 V/ns TCCJ CLKIN Cycle to Cycle Jitter Measured at VDD/2 – 250 ps TLTJ CLKIN Long Term Jitter Measured at VDD/2 – 350 ps VIL Input Low Voltage XIN / CLKIN pin – 0.8 V VIH Input High Voltage XIN / CLKIN pin 2 VDD+0.3 V IIL Input LowCurrent XIN / CLKIN pin, 0 < VIN
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