SL28610
Low Power Clock Generator for Intel® Ultra Mobile Platform
Features
• Supports intel's Moorestown and Menlow clocking
requirements
®
• Buffered Reference Clock 14.318MHz
• Compliant to Intel CK610
• 14.318 MHz Crystal Input or Clock Input
• Low power push-pull type differential output buffers
• Low-voltage frequency select input
• Integrated voltage regulator
• I2C support with readback capabilities
• Integrated resistors on differential clocks
• Triangular Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• Differential CPU clocks with selectable frequency
• 100MHz Differential PCIe clocks
• 100MHz LCD Video Clock
• 96MHz Differential DOT clock
• Industrial Temperature -40°C to 85°C
• 48-pin QFN package
CPU
PCIe
DOT96
LCD
REF
x3
x3
x1
x1
x1
Block Diagram
Pin Configuration
* 100K-ohm Internal pull down
** 10K-ohm Internal pull-up
........................ DOC #: SP-AP-0078 (Rev. 1.0) Page 1 of 23
400 West Cesar Chavez, Austin, TX 78701
1+(512) 416-8500
1+(512) 416-9669
www.silabs.com
SL28610
Pin Definitions
Pin No.
Name
Type
Description
1
CPU_STP#
I, SE
3.3V input for CPU_STP# (active low) functionality
2
CKPWRGD#/PD
I, SE
3.3V LVTTL input (active low)
3
XOUT
O, SE 3.3V, 14.31818MHz crystal output (When used a clock input, float XOUT)
4
XIN/CLKIN
I, SE
3.3V, 14.31818MHz crystal input, 3.3V Clock Input.
5
VDD3.3V
PWR
3.3V power supply for single-ended clock
6
REF / PCIe_SEL
7
VSS
GND
8
VDD1.5_CORE
PWR
1.5V power supply for core
9
FSC
I, SE
1.05V Frequency Select C
10
TEST_MODE
I, SE
3.3V-tolerant input to selects Ref/N or Tri-state when in test mode.
0 = Tri-state, 1 = Ref/N
11
TEST_SEL
I, SE
3.3V-tolerant input to selects TEST_SEL
0 = Normal, 1 = Test Entry
12
SCLK
I, SE
3.3V SMBus Clock Line
13
SDATA
IO, PD, 3.3V, 14.31818MHz output / 1.5V input active high signal latched on CKPWRGD#
SE
signal to select PCIe from PLL3 (share with LCD PLL; 100K-ohm internal pull-down)
Ground
I/O, SE 3.3V SMBus Data Line
14
VDD1.5_CORE
PWR
1.5V power supply for core
15
VDD1.5_IO
PWR
1.5V power supply for differential outputs
16
DOT96#
O, DIFF Fixed complimentary 96MHz clock output
17
DOT96
O, DIFF Fixed true 96MHz clock output
18
VSS
GND
Ground
19
VSS
GND
Ground
20
LCD_SSC#
O, DIF Complementary 100MHz Differential clock
21
LCD_SSC
O, DIF True 100MHz Differential clock
22
VDD1.5_IO
PWR
1.5V power supply for differential outputs
23
VDD1.5_CORE
PWR
1.5V power supply for core
24
OE_0#
I, SE
Output enable for PCIe0, (10K-ohm internal pull-up)
0 =enable, 1=disable
25
VSS
GND
Ground
26
PCIe0#
O, DIF Complementary 100MHz Differential clock
27
PCIe0
O, DIF True 100MHz Differential clock
28
OE_1#
I, SE
Output enable for PCIe1, (10K-ohm internal pull-up)
0 =enable, 1=disable
29
VDD1.5_CORE
PWR
1.5V Power Supply for core
30
VDD1.5_IO
PWR
1.5V Power Supply for differential output
31
PCIe1#
O, DIF Complementary 100MHz Differential clock
32
PCIe1
O, DIF True 100MHz Differential clock
33
VSS
GND
Ground
34
PCIe2#
O, DIF Complementary 100MHz Differential clock
35
PCIe2
O, DIF True 100MHz Differential clock
36
OE_2#
I, SE
Output enable for PCIe2, (10K-ohm internal pull-up)
0 =enable, 1=disable
I, SE
1.05V Frequency Select B
37
FSB
38
CPU0#
O, DIF Complementary Host Differential clock
39
CPU0
O, DIF True Host Differential clock
........................ DOC #: SP-AP-0078 (Rev. 1.0) Page 2 of 23
SL28610
Pin Definitions (continued)
Pin No.
Name
Type
Description
40
VSS
GND
Ground
41
VDD1.5_IO
PWR
1.5V Power Supply for differential output
42
VDD1.5_CORE
PWR
1.5V Power Supply for core
43
CPU1#
O, DIF Complementary Host Differential clock
44
CPU1
O, DIF True Host Differential clock
45
VSS_CPU
GND
Ground
46
VDD1.5_IO
PWR
1.5V Power Supply for differential output
47
CPU2#
O, DIF Complementary Host Differential clock
48
CPU2
O, DIF True Host Differential clock
Table 1. Frequency Select Pin (FSB and FSC)
FSC
FSB
CPU
PCIe
LCD
DOT96
REF
1
0
100 MHz
100 MHz
100 MHz
96 MHz
14.318 MHz
0
0
133 MHz
100 MHz
100 MHz
96 MHz
14.318 MHz
0
1
166 MHz
100 MHz
100 MHz
96 MHz
14.318 MHz
1
1
200 MHz
100 MHz
100 MHz
96 MHz
14.318 MHz
Frequency Select Pin (FSB and FSC)
Apply the appropriate logic levels to FSB and FSC inputs
before CKPWRGD assertion to achieve host clock frequency
selection. When the clock chip sampled LOW on CKPWRGD
and indicates that VTT voltage is stable then FSB and FSC
input values are sampled. This process employs a one-shot
functionality and once the CKPWRGD sampled a valid LOW,
all other FSB, FSC, and CKPWRGD transitions are ignored
except in test mode.
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers are individually enabled or disabled. The
registers associated with the Serial Data Interface initialize to
their default setting at power-up. The use of this interface is
optional. Clock device register changes are normally made at
system initialization, if any are required. The interface cannot
be used during system operation for power management
functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, access the bytes in sequential
order from lowest to highest (most significant bit first) with the
ability to stop after any complete byte is transferred. For byte
write and byte read operations, the system controller can
access individually indexed bytes. The offset of the indexed
byte is encoded in the command code described in Table 2.
The block write and block read protocol is outlined in Table 3
while Table 4 outlines byte write and byte read protocol. The
slave receiver address is 11010010 (D2h).
.
Table 2. Command Code Definition
Bit
7
Description
0 = Block read or block write operation, 1 = Byte read or byte write operation
(6:0)
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
Table 3. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
8:2
Description
Start
Slave address–7 bits
Block Read Protocol
Bit
1
8:2
Description
Start
Slave address–7 bits
9
Write
9
Write
10
Acknowledge from slave
10
Acknowledge from slave
18:11
19
Command Code–8 bits
Acknowledge from slave
........................ DOC #: SP-AP-0078 (Rev. 1.0) Page 3 of 23
18:11
19
Command Code–8 bits
Acknowledge from slave
SL28610
Table 3. Block Read and Block Write Protocol (continued)
Block Write Protocol
Bit
27:20
28
36:29
37
45:38
46
Block Read Protocol
Description
Bit
Byte Count–8 bits
(Skip this step if I2C_EN bit set)
20
Acknowledge from slave
27:21
Description
Repeat start
Slave address–7 bits
Data byte 1–8 bits
28
Read = 1
Acknowledge from slave
29
Acknowledge from slave
Data byte 2–8 bits
37:30
Acknowledge from slave
....
Data Byte /Slave Acknowledges
....
Data Byte N–8 bits
38
46:39
47
....
Acknowledge from slave
....
Stop
55:48
Byte Count from slave–8 bits
Acknowledge
Data byte 1 from slave–8 bits
Acknowledge
Data byte 2 from slave–8 bits
56
Acknowledge
....
Data bytes from slave / Acknowledge
....
Data Byte N from slave–8 bits
....
NOT Acknowledge
....
Stop
Table 4. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
8:2
Description
Start
Slave address–7 bits
Byte Read Protocol
Bit
1
8:2
Description
Start
Slave address–7 bits
9
Write
9
Write
10
Acknowledge from slave
10
Acknowledge from slave
18:11
19
27:20
Command Code–8 bits
Acknowledge from slave
Data byte–8 bits
28
Acknowledge from slave
29
Stop
18:11
19
20
27:21
Acknowledge from slave
Repeated start
Slave address–7 bits
28
Read
29
Acknowledge from slave
37:30
........................ DOC #: SP-AP-0078 (Rev. 1.0) Page 4 of 23
Command Code–8 bits
Data from slave–8 bits
38
NOT Acknowledge
39
Stop
SL28610
Control Registers
Byte 0: Control Register 0
Bit
@Pup
Name
Description
7
1
PLL1_EN
PLL1 Enable
0 = Disabled, 1 = Enabled
6
1
PLL2_EN
PLL2 Enable
0 = Disabled, 1 = Enabled
5
1
PLL3_EN
PLL3 Enable
0 = Disabled, 1 = Enabled
4
0
RESERVED
3
1
CPU_DIV
CPU Output Divider Enable
0 = Disabled, 1 = Enabled
2
1
PCIe_DIV
PCIe Output Divider Enable
0 = Disabled, 1 = Enabled
1
1
LCD_DIV
LCD Output Divider Enable
0 = Disabled, 1 = Enabled
0
1
DOT96_DIV
RESERVED
DOT96 Output Divider Enable
0 = Disabled, 1 = Enabled
Byte 1: Control Register 1
Bit
@Pup
Name
7
1
PLL1_Spread _EN
PLL1 Spread Enable
0 = Disabled, 1 = Enabled
Description
6
1
PLL3_Spread _EN
PLL3 Spread Enable
0 = Disabled, 1 = Enabled
5
0
PLL3_CFB2
4
0
PLL3_CFB1
3
0
PLL3_CFB0
2
0
RESERVED
RESERVED
1
0
RESERVED
RESERVED
0
0
RESERVED
RESERVED
Description
PLL3 Spread Spectrum Select
PLL3_CFB[2:0]
000 = -%0.5 (Down Spread) - Default
001 = -%1.0, DS
010 = -%1.5, DS
011 = -% 2.0, DS
100 = %+0.30 (Center Spread)
101 = %+0.50, CS
110 = %+1.00, CS
111 = %+1.25, CS
Byte 2: Control Register 2
Bit
@Pup
Name
7
1
CPU0_OE
Output enable for CPU0
0 = Output Disabled, 1 = Output Enabled
6
1
CPU1_OE
Output enable for CPU1
0 = Output Disabled, 1 = Output Enabled
5
1
CPU2_OE
Output enable for CPU2
0 = Output Disabled, 1 = Output Enabled
4
1
PCIe0_OE
Output enable for PCIe0
0 = Output Disabled, 1 = Output Enabled
3
1
PCIe1_OE
Output enable for PCIe1
0 = Output Disabled, 1 = Output Enabled
........................ DOC #: SP-AP-0078 (Rev. 1.0) Page 5 of 23
SL28610
Byte 2: Control Register 2 (continued)
Bit
@Pup
Name
Description
2
1
PCIe2_OE
Output enable for SCR2
0 = Output Disabled, 1 = Output Enabled
1
1
DOT96_OE
Output enable for DOT96
0 = Output Disabled, 1 = Output Enabled
0
1
LCD_OE
Output enable for LCD
0 = Output Disabled, 1 = Output Enabled
Byte 3: Control Register 3
Bit
@Pup
Name
Description
7
1
RESERVED
RESERVED
6
1
RESERVED
RESERVED
5
1
REF_OE
Output enable for REF
0 = Output Disabled, 1 = Output Enabled
4
1
REF_Bit1
REF Slew Rate Control Bit2(see Byte 16 Bit [7:6] for Slew Rate REF_Bit0 & REF_Bit2)
0 = 1 load, 1 = 2 loads
3
0
RESERVED
RESERVED
2
0
CPU0_STP#
CPU0 CPU_STP# Control
0 = Free Running, 1 = Stopped with CPU_STP#
1
0
CPU1_STP#
CPU1 CPU_STP# Control
0 = Free Running, 1 = Stopped with CPU_STP#
0
0
CPU2_STP#
CPU2 CPU_STP# Control
0 = Free Running, 1 = Stopped with CPU_STP#
Byte 4: Control Register 4
Bit
@Pup
Name
7
HW
PLL1 M DIV 7
6
HW
PLL1 M DIV 6
5
HW
PLL1 M DIV 5
4
HW
PLL1 M DIV 4
3
HW
PLL1 M DIV 3
2
HW
PLL1 M DIV 2
1
HW
PLL1 M DIV 1
0
HW
PLL1 M DIV 0
Description
This is a read only register of the multiplier used for PLL1 M Divider
HW= Read Only
Byte 5: Control Register 5
Bit
@Pup
Name
7
HW
PLL1 N DIV 7
6
HW
PLL1 N DIV 6
5
HW
PLL1 N DIV 5
4
HW
PLL1 N DIV 4
3
HW
PLL1 N DIV 3
2
HW
PLL1 N DIV 2
1
HW
PLL1 N DIV 1
0
HW
PLL1 N DIV 0
Description
This is a read only register of the multiplier used for PLL1 N Divider
HW= Read Only
........................ DOC #: SP-AP-0078 (Rev. 1.0) Page 6 of 23
SL28610
Byte 6: Control Register 6
Bit
@Pup
Name
Description
7
HW
PLL2 N DIV 8
6
HW
PLL2 N DIV 9
This is a read only register of the multiplier used for PLL2 M and N Dividers
HW= Read Only
5
HW
PLL2 M DIV 5
4
HW
PLL2 M DIV 4
3
HW
PLL2 M DIV 3
2
HW
PLL2 M DIV 2
1
HW
PLL2 M DIV 1
0
HW
PLL2 M DIV 0
Byte 7: Control Register 7
Bit
@Pup
Name
7
HW
PLL2 N DIV 7
6
HW
PLL2 N DIV 6
5
HW
PLL2 N DIV 5
4
HW
PLL2 N DIV 4
3
HW
PLL2 N DIV 3
2
HW
PLL2 N DIV 2
1
HW
PLL2 N DIV 1
0
HW
PLL2 N DIV 0
Description
This is a read only register of the multiplier used for PLL2 N Divider
HW= Read Only
Byte 8: Control Register 8
Bit
@Pup
Name
7
HW
PLL3 M DIV 7
6
HW
PLL3 M DIV 6
5
HW
PLL3 M DIV 5
4
HW
PLL3 M DIV 4
3
HW
PLL3 M DIV 3
2
HW
PLL3 M DIV 2
1
HW
PLL3 M DIV 1
0
HW
PLL3 M DIV 0
Description
This is a read only register of the multiplier used for PLL3 M Divider
HW= Read Only
Byte 9: Control Register 9
Bit
@Pup
Name
7
HW
PLL3 N DIV 7
6
HW
PLL3 N DIV 6
5
HW
PLL3 N DIV 5
4
HW
PLL3 N DIV 4
3
HW
PLL3 N DIV 3
2
HW
PLL3 N DIV 2
1
HW
PLL3 N DIV 1
0
HW
PLL3 N DIV 0
Description
This is a read only register of the multiplier used for PLL3 N Divider
HW= Read Only
........................ DOC #: SP-AP-0078 (Rev. 1.0) Page 7 of 23
SL28610
Byte 10: Control Register 10
Bit
@Pup
Name
7
HW
FSB
Description
FSB status bit, CPU Frequency Select Bit, read only
6
HW
FSC
5
HW
OE#_0
OE#_0 status bit, PCIe0 enable status, read only
0 = PCIe0 disabled, 1 = PCIe0 enabled
FSC status bit, CPU Frequency Select Bit, read only
4
HW
OE#_1
OE#_0 status bit, PCIe1 enable status, read only
0 = PCIe1 disabled, 1 = PCIe1 enabled
3
HW
OE#_2
OE#_0 status bit, PCIe2 enable status, read only
0 = PCIe2 disabled, 1 = PCIe2 enabled
2
0
RESERVED
RESERVED
1
0
RESERVED
RESERVED
0
0
RESERVED
RESERVED
Description
Byte 11: Control Register 11
Bit
@Pup
Name
7
1
Vendor ID bit 3
Vendor ID Bit 3
6
0
Vendor ID bit 2
Vendor ID Bit 2
5
0
Vendor ID bit 1
Vendor ID Bit 1
4
0
Vendor ID bit 0
Vendor ID Bit 0
3
0
Rev Code Bit 3
Revision Code Bit 3
2
0
Rev Code Bit 2
Revision Code Bit 2
1
0
Rev Code Bit 1
Revision Code Bit 1
0
1
Rev Code Bit 0
Revision Code Bit 0
Byte 12: Byte Count 12
Bit
@Pup
Name
7
1
Device_ID3
Description
6
0
Device_ID2
5
1
Device_ID1
4
0
Device_ID0
7
0
RESERVED
RESERVED
2
0
RESERVED
RESERVED
1
0
RESERVED
RESERVED
0
0
RESERVED
RESERVED
0000 = Reserved
0001 = Reserved
0010 = Reserved
0011 = Reserved
0100 = Reserved
0101 = Reserved
0110 = Reserved
0111 = Reserved
1000 = Reserved
1001 = Reserved
1010 = CK610 Yellow Cover Device, 48-pin QFN
1011 = Reserved
1100 = Reserved
1101 = Reserved
1110 = Reserved
1111 = Reserved
........................ DOC #: SP-AP-0078 (Rev. 1.0) Page 8 of 23
SL28610
Byte 13: Control Register 13
Bit
@Pup
Name
Description
7
0
RESERVED
RESERVED
6
0
RESERVED
RESERVED
5
0
RESERVED
RESERVED
4
0
RESERVED
RESERVED
3
0
RESERVED
RESERVED
2
0
RESERVED
RESERVED
1
0
RESERVED
RESERVED
0
0
RESERVED
RESERVED
Byte 14: Control Register 14
Bit
@Pup
Name
Description
7
0
RESERVED
RESERVED
6
0
RESERVED
RESERVED
5
0
RESERVED
RESERVED
4
0
RESERVED
RESERVED
7
0
RESERVED
RESERVED
2
0
RESERVED
RESERVED
1
0
RESERVED
RESERVED
0
0
RESERVED
RESERVED
Description
Byte 15: Control Register 15
Bit
@Pup
Name
7
0
BC7
Byte count 7
6
0
BC6
Byte count 6
5
0
BC5
Byte count 5
4
1
BC4
Byte count 4
3
0
BC3
Byte count 3
2
1
BC2
Byte count 2
1
1
BC1
Byte count 1
0
0
BC0
Byte count 0
Byte 16: Control Register 16
Bit
@Pup
Name
7
0
REF_Bit2
6
1
REF_Bit0
5:0
0
RESERVED
Description
REF Slew Rate Control Bit2 & Bit0 (see Byte 3 Bit 4 for Slew Rate REF_Bit1)
........................ DOC #: SP-AP-0078 (Rev. 1.0) Page 9 of 23
RESERVED
SL28610
Byte 17: Control Register 17
Bit
@Pup
Name
Description
7
0
PLL1_DAF_N7
6
0
PLL1_DAF_N6
If Prog_PLL1_EN is set, the values programmed in PLL1_DAF_N[7:0] and
PLL1_DAF_M[7:0] are used to determine the PLL1 output frequency.
5
0
PLL1_DAF_N5
4
0
PLL1_DAF_N4
7
0
PLL1_DAF_N3
2
0
PLL1_DAF_N2
1
0
PLL1_DAF_N1
0
0
PLL1_DAF_N0
Byte 18: Control Register 18
Bit
@Pup
Name
Description
If Prog_PLL1_EN is set, the values programmed in PLL1_DAF_N[7:0] and
PLL1_DAF_M[7:0] are used to determine the PLL1 output frequency.
7
0
PLL1_DAF_M7
6
0
PLL1_DAF_M6
5
0
PLL1_DAF_M5
4
0
PLL1_DAF_M4
7
0
PLL1_DAF_M3
2
0
PLL1_DAF_M2
1
0
PLL1_DAF_M1
0
0
PLL1_DAF_M0
Byte 19: Control Register 19
Bit
@Pup
Name
Description
7
0
RESERVED
RESERVED
6
0
RESERVED
RESERVED
5
0
Prog_PLL1_EN
Programmable PLL1 frequency enable
0 = Disabled, 1= Enabled
4
0
Prog_PLL3_EN
Programmable PLL3 frequency enable
0 = Disabled, 1= Enabled
3
0
CPU_OEB_DRIVE _Mode Controls CPU Output Drive States
1 = OUT=LOW and OUT#=LOW
0= OUT=HIGH and OUT#=LOW
2
0
PCIe_OEB_DRIVE _Mode Controls PCIe Output Drive States
1 = OUT=LOW and OUT#=LOW
0= OUT=HIGH and OUT#=LOW
1
0
LVDS_OEB_DRIVE _Mode Controls LVDS Output Drive States
1 = OUT=LOW and OUT#=LOW
0= OUT=HIGH and OUT#=LOW
0
0
DOT_OEB_DRIVE _Mode Controls DOT Output Drive States
1 = OUT=LOW and OUT#=LOW
0= OUT=HIGH and OUT#=LOW
...................... DOC #: SP-AP-0078 (Rev. 1.0) Page 10 of 23
SL28610
Byte 20: Control Register 20
Bit
@Pup
Name
Description
7
0
PLL3_DAF_N7
6
0
PLL3_DAF_N6
If Prog_PLL3_EN is set, the values programmed in PLL3_DAF_N[7:0] and
PLL3_DAF_M[7:0] are used to determine the PLL3 output frequency.
5
0
PLL3_DAF_N5
4
0
PLL3_DAF_N4
7
0
PLL3_DAF_N3
2
0
PLL3_DAF_N2
1
0
PLL3_DAF_N1
0
0
PLL3_DAF_N0
Byte 21: Control Register 21
Bit
@Pup
Name
Description
If Prog_PLL3_EN is set, the values programmed in PLL3_DAF_N[7:0] and
PLL3_DAF_M[7:0] are used to determine the PLL3 output frequency.
7
0
PLL3_DAF_M7
6
0
PLL3_DAF_M6
5
0
PLL3_DAF_M5
4
0
PLL3_DAF_M4
7
0
PLL3_DAF_M3
2
0
PLL3_DAF_M2
1
0
PLL3_DAF_M1
0
0
PLL3_DAF_M0
CKPWRGD#/PD (Power down) Clarification
The CKPWRGD#/PD pin is a dual-function pin. During initial
power up, the pin functions as CKPWRGD#. Once
CKPWRGD# has been sampled HIGH by the clock chip, the
pin assumes PD functionality. The PD pin is an asynchronous
active HIGH input used to shut off all clocks cleanly before
shutting off power to the device. This signal is synchronized
internally to the device before powering down the clock
synthesizer. PD is also an asynchronous input for powering up
the system. When PD is asserted HIGH, clocks are driven to
a LOW value and held before turning off the VCOs and the
crystal oscillator.
CKPWRGD#/PD (Power down) Assertion
When PD is sampled HIGH by two consecutive rising edges
of CPUC, all single-ended outputs will be held HIGH on their
...................... DOC #: SP-AP-0078 (Rev. 1.0) Page 11 of 23
next HIGH-to-LOW transition and differential clocks must held
HIGH. When PD mode is desired as the initial power on state,
PD must be asserted HIGH in less than 10 s after asserting
CKPWRGD.
CKPWRGD#/PD (Power Down) Deassertion
The power up latency is less than 1.8 ms. This is the time from
the deassertion of the PD pin or the ramping of the power
supply until the time that stable clocks are generated from the
clock chip. All differential outputs stopped in a three-state
condition, resulting from power down are driven high in less
than 300 s of PD deassertion to a voltage greater than
200 mV. After the clock chip’s internal PLL is powered up and
locked, all outputs are enabled within a few clock cycles of
each clock. Figure 2 is an example showing the relationship of
clocks coming up.
SL28610
Figure 1. Power down Assertion Timing Waveform
Figure 2. Power down Deassertion Timing Waveform
...................... DOC #: SP-AP-0078 (Rev. 1.0) Page 12 of 23
SL28610
Figure 3. CKPWRGD# Timing Diagram
...................... DOC #: SP-AP-0078 (Rev. 1.0) Page 13 of 23
SL28610
CPU_STP# Assertion
CPU_STP# Deassertion
The CPU_STP# signal is an active LOW input used for
synchronous stopping and starting the CPU output clocks
while the rest of the clock generator continues to function.
When the CPU_STP# pin is asserted, all CPU outputs that are
set with the SMBus configuration to be stoppable are stopped
within two to six CPU clock periods after sampled by two rising
edges of the internal CPUC clock. The final states of the
stopped CPU signals are CPUT = HIGH and CPUC = LOW.
The deassertion of the CPU_STP# signal causes all stopped
CPU outputs to resume normal operation in a synchronous
manner. No short or stretched clock pulses are produced when
the clock resumes. The maximum latency from the
deassertion to active outputs is no more than two CPU clock
cycles.
CPU_STP#
CPUT
CPUC
Figure 4. CPU_STP# Assertion Waveform
CPU_STP#
CPUT
CPUC
CPUT Internal
CPUC Internal
Tdrive_CPU_STP#,10 ns>200 mV
Figure 5. CPU_STP# Deassertion Waveform
.
.
Table 1. Output Driver Status during PCI_STPPCI_STP# and CPU_STP#
CPU_STP# Asserted
Single-ended Clocks Stoppable
Differential Clocks
OE# Pins Disabled
Running
Non stoppable
Running
Stoppable
Clock driven high
Clock# driven low
Non stoppable
SMBus Disabled
Driven low
Clock driven high*
Driven Low
Running
Note: *Differential clocks output state can be configured through Byte 19 bits 3:.0
...................... DOC #: SP-AP-0078 (Rev. 1.0) Page 14 of 23
Driven low
Clock# driven low*
SL28610
Absolute Maximum Conditions
Parameter
Min.
Max.
Unit
3.3V Supply Voltage
Functional
–0.5
4.6
V
1.5V_VDD_CORE 1.5V Supply Voltage
Functional
–0.5
2.1
V
1.5V_VDD_IO
DIFF I/O Supply Voltage
Functional
–0.5
2.1
V
VIN
Input Voltage
Relative to VSS
–0.5
4.6
VDC
TS
Temperature, Storage
Non-functional
–65
150
°C
TA
Commercial Temperature,
Operating Ambient
Functional
0
85
°C
-40
+85
°C
–
150
°C
3.3V_VDD
Description
Condition
Industrial Temperature, Operating
Ambient
TJ
Temperature, Junction
Functional
ØJC
Dissipation, Junction to Case
JEDEC (JESD 51)
–
20
°C/W
ØJA
Dissipation, Junction to Ambient
JEDEC (JESD 51)
–
60
°C/W
ESDHBM
ESD Protection (Human Body
Model)
JEDEC (JESD 22-A114)
2000
–
V
UL-94
Flammability Rating
UL (CLASS)
V–0
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
DC Electrical Specifications
Parameter
Description
Condition
Min.
Max.
Unit
1.5V_VDD_CORE 1.5V Operating Voltage
1.5V ± 5%
1.425
1.575
V
1.5V_VDD_IO
1.5V Differential I/O Supply
Voltage
1.5V ± 5%
1.425
1.575
V
3.3V_VDD
3.3V Operating Voltage
3.3 ± 5%
3.135
3.465
V
3.3V_VIH
3.3V Input High Voltage (SE)
3.3V_VDD
2
3.3V_CORE+ 0.3
V
3.3V_VIL
3.3V Input Low Voltage (SE)
VSS – 0.3
0.8
V
VIHI2C
Input High Voltage
SDATA, SCLK
2.2
–
V
VILI2C
Input Low Voltage
SDATA, SCLK
–
1.0
V
VIH_FS
FS_[C,B] Input High Voltage
1.05V_CORE
VIL_FS
FS_[C,B] Input Low Voltage
VIH
OE# Input High Voltage
VIL
OE# Input Low Voltage
VIH
PCIe_SEL Input High Voltage
VIL
PCIe_SEL Input Low Voltage
IIH
Input High Leakage Current
IIL
Input Low Leakage Current
VOH
3.3V Output High Voltage (SE) IOH = –1 mA
VOL
3.3V Output Low Voltage (SE)
1.5V_CORE
3.3V_CORE
0.9
1.5V_CORE + 0.3
V
GND-0.3
0.25
V
1.2
1.5V_CORE + 0.3
V
GND-0.3
0.3
V
2.0
VDD+0.3
V
GND-0.3
0.8
V
Except internal pull-down resistors,
0 < VIN < VDD
–
5
A
Except internal pull-up resistors, 0
< VIN < VDD
–5
–
A
IOL = 1 mA
2.4
–
V
–
0.4
V
VDD IO
Low Voltage IO Supply Voltage
0.72
0.88
IOZ
High-impedance Output
Current
–10
10
A
CIN
Input Pin Capacitance
1.5
5
pF
...................... DOC #: SP-AP-0078 (Rev. 1.0) Page 15 of 23
SL28610
DC Electrical Specifications (continued)
Parameter
Description
COUT
Output Pin Capacitance
LIN
Pin Inductance
VXIH
Xin High Voltage
VXIL
Power
Condition
Min.
Max.
Unit
6
pF
–
7
nH
0.7VDD
VDD
V
Xin Low Voltage
0
0.3VDD
V
Power Consumption
–
100
mW
AC Electrical Specifications
Parameter
Description
Condition
Min.
Max.
Unit
47.5
52.5
%
69.841
71.0
ns
–
10.0
ns
Crystal
TDC
XIN Duty Cycle
The device operates reliably with input
duty cycles up to 30/70 but the REF clock
duty cycle will not be within specification
TPERIOD
XIN Period
When XIN is driven from an external
clock source
TR/TF
XIN Rise and Fall Times
Measured between 0.3VDD and 0.7VDD
TCCJ
XIN Cycle to Cycle Jitter
As an average over 1-s duration
–
500
ps
LACC
Long-term Accuracy
Measured at VDD/2 differential
–
250
ppm
TDC
CLKIN Duty Cycle
Measured at VDD/2
47
53
%
Clock Input
TR/TF
CLKIN Rise and Fall Times
Measured between 0.2VDD and 0.8VDD
0.5
4.0
V/ns
TCCJ
CLKIN Cycle to Cycle Jitter
Measured at VDD/2
–
250
ps
TLTJ
CLKIN Long Term Jitter
Measured at VDD/2
–
350
ps
VIL
Input Low Voltage
XIN / CLKIN pin
–
0.8
V
VIH
Input High Voltage
XIN / CLKIN pin
2
VDD+0.3
V
IIL
Input LowCurrent
XIN / CLKIN pin, 0 < VIN