SL28773
EProClock® Generator for Intel Calpella Chipset
Features
• 100MHz Differential SATA clocks
• Intel CK505 Clock Revision 1.0 Compliant
• Hybrid Video Support - Simultaneous DOT96,
27MHz_SS and 27MHz_NSS video clocks
• 96MHz Differential DOT clock
• 27MHz Video clock
• 48MHz USB clock
• PCI-Express Gen 2 Compliant
• Buffered Reference Clock 14.318MHz
• Low power push-pull type differential output buffers
• PC EProClock® Programmable Technology
• Integrated voltage regulator
• I2C support with readback capabilities
• Integrated resistors on differential clocks
• Triangular Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
CPU
SRC
x2
x1
x1
x1
x1
x1
x2
CKPWRGD/ PD#
VSS_REF
XTAL_OUT
Pin Configuration
SCLK
Block Diagram
SATA DOT96 USB_48 REF 27M
XTAL_IN
• 100MHz Differential SRC clocks
• 32-pin QFN package
VDD_REF
• Differential CPU clocks with selectable frequency
• 3.3V Power supply
REF0/ FS**
• Wireless friendly 3-bits slew rate control on
single-ended clocks.
SDATA
• Scalable low voltage VDD_IO (3.3V to 1.05V)
32 31 30 29 28 27 26 25
24 VDD_CPU
VDD_DOT 1
VSS_DOT 2
23 CPU0
22 CPU#0
DOT96 3
DOT96# 4
21 VSS_CPU
SL28773
USB_48 5
VDD_27 6
20 CPU1
19 CPU#1
18 VDD_CPU_IO
27_NSS 7
27_SS 8
17 VDD_SRC
CPU_STP#
VDD_SRC_IO
SRC#1
SRC1
VSS_SRC
SRC0# / SATA#
VSS_27
SRC0 / SATA
9 10 11 12 13 14 15 16
** Internal 100K-ohm Pull-Down Resistor
........................ Document #: 001-08400 Rev ** Page 1 of 21
400 West Cesar Chavez, Austin, TX 78701
1+(512) 416-8500
1+(512) 416-9669
www.silabs.com
SL28773
32-QFN Pin Definitions
Pin No.
1
Name
VDD_DOT
Type
PWR
Description
3.3V Power supply for outputs and PLL
2
VSS_DOT
3
DOT96
O, DIF Fixed true 96MHz clock output
GND
Ground for outputs
4
DOT96#
O, DIF Fixed complement 96MHz clock output
5
USB_48
O,SE
6
VDD_27
PWR
3.3V Power supply for 27MHz PLL
7
27M_NSS
O,SE
Non-spread 27MHz video clock output
8
27M_SS
O, SE Spread 27MHz video clock output
9
VSS_27
GND
Non-spread 48MHz video clock output
Ground for 27MHz PLL
10
SRC0 / SATA
O, DIF 100MHz True differential serial reference clock
11
SRC0# / SATA#
O, DIF 100MHz Complement differential serial reference clock
12
VSS_SRC
13
SRC1
O, DIF 100MHz True differential serial reference clock
GND
14
SRC1#
O, DIF 100MHz Complement differential serial reference clock
15
VDD_SRC_IO
16
CPU_STP#
I
17
VDD_SRC
PWR
3.3V Power supply for PLL
18
VDD_CPU_IO
PWR
Scalable 3.3V to 1.05V power supply for output buffer
19
CPU1#
O, DIF Complement differential CPU clock output
20
CPU1
O, DIF True differential CPU clock output
21
VSS_CPU
22
CPU0#
O, DIF Complement differential CPU clock output
23
CPU0
O, DIF True differential CPU clock output
24
VDD_CPU
25
CKPWRGD/PD#
PWR
GND
PWR
I
Ground for PLL
Scalable 3.3V to 1.05V power supply for output buffer
3.3V tolerance input to stop the CPU clock
Ground for PLL
3.3V Power supply for CPU PLL
3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS.
After CKPWRGD (active HIGH) assertion, this pin becomes a real-time input for
asserting power down (active LOW)
26
VSS_REF
GND
27
XOUT
O, SE 14.318MHz Crystal output
28
XIN
29
VDD_REF
30
REF/FS**
I
PWR
Ground for outputs
14.318MHz Crystal input
3.3V Power supply for outputs and also maintains SMBUS registers during
power-down
PD, I/O 3.3V tolerant input for Graphic clock selection/fixed 14.318MHz clock output.
(Internal 100K-ohm pull-down resistor on FS pin)
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications
31
SDATA
I/O
32
SCLK
I
SMBus compatible SDATA
SMBus compatible SCLOCK
........................Document #: 001-08400 Rev ** Page 2 of 21
SL28773
PC EProClock® Programmable Technology
PC EProClock® is the world’s first non-volatile programmable
PC clock. The PC EProClock® technology allows board
designer to promptly achieve optimum compliance and clock
signal integrity; historically, attainable typically through device
and/or board redesigns.
PC EProClock® technology can be configured through SMBus
or hard coded.
- Differential skew control on true or compliment or both
- Differential duty cycle control on true or compliment or both
- Differential amplitude control
- Differential and single-ended slew rate control
Features:
- Program Internal or External series resistor on single-ended
clocks
- > 4000 bits of configurations
- Program different spread profiles
- Can be configured through SMBus or hard coded
- Program different spread modulation rate
- Custom frequency sets
- For more information: Please refer to Application Note #25
Frequency Select Pin (FS)
FS
CPU
Power On
0
133MHz
Default
1
100MHz
SRC
SATA
DOT96
USB_48
27MHz
REF
100MHz
100MHz
96MHz
48MHz
27MHz
14.318MHz
Frequency Select Pin FS
Apply the appropriate logic levels to FS inputs before
CKPWRGD assertion to achieve host clock frequency
selection. When the clock chip sampled HIGH on CKPWRGD
and indicates that VTT voltage is stable then FS input values
are sampled. This process employs a one-shot functionality
and once the CKPWRGD sampled a valid HIGH, all other FS,
and CKPWRGD transitions are ignored except in test mode.
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers are individually enabled or disabled. The
registers associated with the Serial Data Interface initialize to
their default setting at power-up. The use of this interface is
optional. Clock device register changes are normally made at
system initialization, if any are required. The interface cannot
be used during system operation for power management
functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, access the bytes in sequential
order from lowest to highest (most significant bit first) with the
ability to stop after any complete byte is transferred. For byte
write and byte read operations, the system controller can
access individually indexed bytes. The offset of the indexed
byte is encoded in the command code described in Table 1.
The block write and block read protocol is outlined in Table 2
while Table 3 outlines byte write and byte read protocol. The
slave receiver address is 11010010 (D2h).
.
Table 1. Command Code Definition
Bit
7
Description
0 = Block read or block write operation, 1 = Byte read or byte write operation
(6:0)
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
8:2
9
10
18:11
19
27:20
28
Description
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Block Read Protocol
Bit
1
8:2
9
10
18:11
Description
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
19
Acknowledge from slave
Byte Count–8 bits
20
Repeat start
Acknowledge from slave
........................Document #: 001-08400 Rev ** Page 3 of 21
27:21
Slave address–7 bits
SL28773
Table 2. Block Read and Block Write Protocol (continued)
Block Write Protocol
Bit
36:29
37
45:38
Description
Data byte 1–8 bits
Acknowledge from slave
Data byte 2–8 bits
Block Read Protocol
Bit
Read = 1
29
Acknowledge from slave
37:30
46
Acknowledge from slave
....
Data Byte /Slave Acknowledges
....
Data Byte N–8 bits
....
Acknowledge from slave
....
Stop
Description
28
38
46:39
47
55:48
Byte Count from slave–8 bits
Acknowledge
Data byte 1 from slave–8 bits
Acknowledge
Data byte 2 from slave–8 bits
56
Acknowledge
....
Data bytes from slave / Acknowledge
....
Data Byte N from slave–8 bits
....
NOT Acknowledge
....
Stop
Table 3. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
8:2
9
10
18:11
19
27:20
Description
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Byte Read Protocol
Bit
1
8:2
9
10
18:11
Description
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
19
Acknowledge from slave
Data byte–8 bits
20
Repeated start
28
Acknowledge from slave
29
Stop
27:21
28
29
37:30
........................Document #: 001-08400 Rev ** Page 4 of 21
Slave address–7 bits
Read
Acknowledge from slave
Data from slave–8 bits
38
NOT Acknowledge
39
Stop
SL28773
Control Registers
Byte 0: Control Register 0
Bit
@Pup
Name
Description
7
HW
FS
6
0
RESERVED
RESERVED
5
1
RESERVED
RESERVED
4
0
iAMT_EN
3
0
RESERVED
2
0
SRC_Main_SEL
1
0
SATA_SEL
Select source of SATA clock
0 = SATA = SRC_MAIN, 1= SATA = PLL4
0
1
PD_Restore
Save configuration when PD# is asserted
0 = Config. cleared, 1 = Config. saved
CPU Frequency Select Bit, set by HW
0 = 133MHz, 1= 100MHz
iAMT Enable
0 = Legacy Mode, 1 = iAMT Enabled
RESERVED
Select source for SRC clock
0 = SRC_MAIN = PLL1, PLL3_CFG Table applies
1 = SRC_MAIN = PLL3, PLL3_CFG Table does not apply
Byte 1: Control Register 1
Bit
@Pup
Name
7
1
RESERVED
6
0
PLL1_SS_DC
Select for down or center SS
0 = Down spread, 1 = Center spread
5
0
PLL3_SS_DC
Select for down or center SS
0 = Down spread, 1 = Center spread
4
0
PLL3_CFB3
3
0
PLL3_CFB2
2
1
PLL3_CFB1
1
0
PLL3_CFB0
0
1
RESERVED
Description
RESERVED
CFB Bit [4:1] only applies when SRC_Main_SEL = 0 (Byte 0, bit 2 =0)
See Table 4 on page 9 for Configuration.
RESERVED
Byte 2: Control Register 2
Bit
@Pup
Name
7
1
REF_OE
Output enable for REF
0 = Output Disabled, 1 = Output Enabled
Description
6
1
USB_48_OE
Output enable for USB_48
0 = Output Disabled, 1 = Output Enabled
5
1
RESERVED
RESERVED
4
1
RESERVED
RESERVED
3
1
RESERVED
RESERVED
2
1
RESERVED
RESERVED
1
1
RESERVED
RESERVED
0
1
RESERVED
RESERVED
Byte 3: Control Register 3
Bit
@Pup
Name
7
1
RESERVED
RESERVED
Description
6
1
RESERVED
RESERVED
........................Document #: 001-08400 Rev ** Page 5 of 21
SL28773
Byte 3: Control Register 3
5
1
RESERVED
RESERVED
4
1
RESERVED
RESERVED
3
1
RESERVED
RESERVED
2
1
RESERVED
RESERVED
1
1
RESERVED
RESERVED
0
1
RESERVED
RESERVED
Byte 4: Control Register 4
Bit
@Pup
Name
7
1
RESERVED
Description
6
1
SATA_OE
Output enable for SATA
0 = Output Disabled, 1 = Output Enabled
5
1
SRC_OE
Output enable for SRC
0 = Output Disabled, 1 = Output Enabled
4
1
DOT96_OE
Output enable for DOT96
0 = Output Disabled, 1 = Output Enabled
3
1
CPU1_OE
Output enable for CPU1
0 = Output Disabled, 1 = Output Enabled
2
1
CPU0_OE
Output enable for CPU0
0 = Output Disabled, 1 = Output Enabled
1
1
PLL1_SS_EN
Enable PLL1s spread modulation,
0 = Spread Disabled, 1 = Spread Enabled
0
1
PLL3_SS_EN
Enable PLL3s spread modulation
0 = Spread Disabled, 1 = Spread Enabled
RESERVED
Byte 5: Control Register 5
Bit
@Pup
Name
7
0
RESERVED
RESERVED
Description
6
0
RESERVED
RESERVED
5
0
RESERVED
RESERVED
4
0
RESERVED
RESERVED
3
0
RESERVED
RESERVED
2
0
RESERVED
RESERVED
1
0
RESERVED
RESERVED
0
0
RESERVED
RESERVED
Byte 6: Control Register 6
Bit
@Pup
Name
7
0
RESERVED
RESERVED
Description
6
0
RESERVED
RESERVED
5
0
REF Bit1
4
0
RESERVED
RESERVED
3
0
27MHz Bit 1
27MHz slew rate control (see Byte 13 for Slew Rate Bit 0 and Bit 2)
0 = High, 1 = Low
2
0
RESERVED
RESERVED
1
0
RESERVED
RESERVED
REF slew rate control (see Byte 13 for Slew Rate Bit 0 and Bit 2)
0 = High, 1 = Low
........................Document #: 001-08400 Rev ** Page 6 of 21
SL28773
Byte 6: Control Register 6
0
0
RESERVED
RESERVED
Byte 7: Vendor ID
Bit
@Pup
Name
Description
7
0
Rev Code Bit 3
Revision Code Bit 3
6
1
Rev Code Bit 2
Revision Code Bit 2
5
0
Rev Code Bit 1
Revision Code Bit 1
4
0
Rev Code Bit 0
Revision Code Bit 0
3
1
Vendor ID bit 3
Vendor ID Bit 3
2
0
Vendor ID bit 2
Vendor ID Bit 2
1
0
Vendor ID bit 1
Vendor ID Bit 1
0
0
Vendor ID bit 0
Vendor ID Bit 0
Byte 8: Control Register 8
Bit
@Pup
Name
7
1
Device_ID3
RESERVED
Description
6
0
Device_ID2
RESERVED
5
0
Device_ID1
RESERVED
4
0
Device_ID0
RESERVED
3
0
RESERVED
RESERVED
2
0
RESERVED
RESERVED
1
1
27M_non-SS_OE
Output enable for 27M_non-SS
0 = Output Disabled, 1 = Output Enabled
0
1
27M_SS_OE
Output enable for 27M_SS
0 = Output Disabled, 1 = Output Enabled
Byte 9: Control Register 9
Bit
@Pup
Name
7
0
RESERVED
RESERVED
Description
6
0
RESERVED
RESERVED
5
1
RESERVED
RESERVED
4
0
TEST _MODE_SEL
Test mode select either REF/N or tri-state
0 = All outputs tri-state, 1 = All output REF/N
3
0
TEST_MODE_ENTRY
Allows entry into test mode
0 = Normal Operation, 1 = Enter test mode(s)
2
1
I2C_VOUT
1
0
I2C_VOUT
0
1
I2C_VOUT
Amplitude configurations differential clocks
I2C_VOUT[2:0]
000 = 0.30V
001 = 0.40V
010 = 0.50V
011 = 0.60V
100 = 0.70V
101 = 0.80V (default)
110 = 0.90V
111 = 1.00V
........................Document #: 001-08400 Rev ** Page 7 of 21
SL28773
Byte 10: Control Register 10
Bit
@Pup
Name
Description
7
0
RESERVED
RESERVED
6
0
RESERVED
RESERVED
5
0
RESERVED
RESERVED
4
0
RESERVED
RESERVED
3
0
RESERVED
RESERVED
2
0
RESERVED
RESERVED
1
1
CPU1_STP_CTRL
Enable CPU_STP# control of CPU1
0 = Free running, 1= Stoppable
0
1
CPU0_STP_CTRL
Enable CPU_STP# control of CPU0
0 = Free running, 1= Stoppable
Byte 11: Control Register 11
Bit
@Pup
Name
Description
7
0
RESERVED
RESERVED
6
0
RESERVED
RESERVED
5
0
RESERVED
RESERVED
4
0
RESERVED
RESERVED
3
0
RESERVED
2
1
CPU1_iAMT_EN
1
1
PCI-e_GEN2
PCI-e_Gen2 Compliant
0 = non Gen2, 1= Gen2 Compliant
0
1
RESERVED
RESERVED
RESERVED
CPU1 iAMT Clock Enabled
0 = Disabled, 1 = Enabled
Byte 12: Byte Count
Bit
@Pup
Name
7
0
BC7
6
0
BC6
5
0
BC5
4
0
BC4
3
1
BC3
2
1
BC2
1
1
BC1
0
1
BC0
Description
Byte count register for block read operation.
The default value for Byte count is 15.
In order to read beyond Byte 15, the user should change the byte count
limit.to or beyond the byte that is desired to be read.
Byte 13: Control Register 13
Bit
@Pup
Name
........................Document #: 001-08400 Rev ** Page 8 of 21
Description
SL28773
7
1
REF_Bit2
Drive Strength Control - Bit[2:0], Note: See Byte 6 Bit 5 for REF Slew Rate Bit 1 and
6
1
REF_Bit0
Byte 6 Bit 3 for 27MHz Slew Rate Bit 1
5
1
27MHz_NSS_Bit2
4
1
27MHz_NSS_Bit0
3
1
27MHz_SS_Bit2
2
1
27MHz_SS_Bit0
1
0
RESERVED
0
0
Wireless Friendly mode
Normal mode default ‘101’
Wireless Friendly Mode default to ‘111’
RESERVED
Wireless Friendly Mode
0 = Disabled, Default all single-ended clocks slew rate config bits to ‘101’
1 = Enabled, Default all single-ended clocks slew rate config bits to ‘111’
Byte 14: Control Register 14
Bit
@Pup
Name
Description
7
1
USB_48_Bit2
Drive Strength Control - Bit[2:0] , Note: REF Bit 1is located in Byte 6 Bit 5 and 27MHz
6
0
USB_48_Bit1
5
1
USB_48_Bit0
4
0
OTP_4
3
0
OTP_3
2
0
OTP_2
1
0
OTP_1
0
0
OTP_0
Bit 1 is located in Byte 6 Bit 3
Normal mode default ‘101’
Wireless Friendly Mode default to ‘111’
OTP_ID
Identification for programmed device
Table 4. Pin 6 and 7 Configuration Table
B1b4
B1b3
B1b2
B1b1
Pin7
Pin 8
Spread
(%)
0
0
0
0
N/A
N/A
N/A
0
0
0
1
N/A
N/A
N/A
0
0
1
0
27M_NSS
27M_SS
-0.5%
0
0
1
1
27M_NSS
27M_SS
-1%
0
1
0
0
27M_NSS
27M_SS
-1.5%
0
1
0
1
27M_NSS
27M_SS
-2%
0
1
1
0
27M_NSS
27M_SS
-0.75V
0
1
1
1
27M_NSS
27M_SS
-1.25%
........................Document #: 001-08400 Rev ** Page 9 of 21
SL28773
B1b4
B1b3
B1b2
B1b1
Pin7
Pin 8
Spread
(%)
1
0
0
0
27M_NSS
27M_SS
-1.75%
1
0
0
1
27M_NSS
27M_SS
+/-0.5%
1
0
1
0
27M_NSS
27M_SS
+/-0.75%
1
0
1
1
N/A
N/A
N/A
1
1
0
0
N/A
N/A
N/A
1
1
0
1
N/A
N/A
N/A
1
1
1
0
N/A
N/A
N/A
1
1
1
1
N/A
N/A
N/A
.
.
Table 5. Output Driver Status during CPU_STP#
CPU_STP# Asserted
Single-ended Clocks Stoppable
Differential Clocks
SMBus OE Disabled
Running
Driven low
Non stoppable
Running
Stoppable
Clock driven high
Clock driven low
Clock# driven low
Non stoppable
Running
Table 6. Output Driver Status
All Single-ended Clocks
All Differential Clocks
w/o Strap
w/ Strap
Clock
Clock#
Low
Hi-z
Low
Low
PD# = 0 (Power down)
Table 7. Crystal Recommendations
Frequency
(Fund)
Cut
Loading Load Cap
Drive
(max.)
Shunt Cap
(max.)
Motional
(max.)
Tolerance
(max.)
Stability
(max.)
Aging
(max.)
14.31818 MHz
AT
Parallel
0.1 mW
5 pF
0.016 pF
35 ppm
30 ppm
5 ppm
20 pF
The SL28773 requires a Parallel Resonance Crystal. Substituting a series resonance crystal causes the SL28773 to
operate at the wrong frequency and violates the ppm specification. For most applications there is a 300-ppm frequency
shift between series and parallel crystals due to incorrect
loading.
Crystal Loading
Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, use the total capacitance the crystal sees to calculate the appropriate capacitive
loading (CL).
Figure 1 shows a typical crystal configuration using the two
trim capacitors. It is important that the trim capacitors are in
series with the crystal. It is not true that load capacitors are in
parallel with the crystal and are approximately equal to the
load capacitance of the crystal.
......................Document #: 001-08400 Rev ** Page 10 of 21
Figure 1. Crystal Capacitive Clarification
Calculating Load Capacitors
In addition to the standard external trim capacitors, consider
the trace capacitance and pin capacitance to calculate the
crystal loading correctly. Again, the capacitance on each side
is in series with the crystal. The total capacitance on both side
is twice the specified crystal load capacitance (CL). Trim
capacitors are calculated to provide equal capacitive loading
on both sides.
SL28773
PD# (Power down) Clarification
The CKPWRGD/PD# pin is a dual-function pin. During initial
power up, the pin functions as CKPWRGD. Once CKPWRGD
has been sampled HIGH by the clock chip, the pin assumes
PD# functionality. The PD# pin is an asynchronous active
LOW input used to shut off all clocks cleanly before shutting
off power to the device. This signal is synchronized internally
to the device before powering down the clock synthesizer. PD#
is also an asynchronous input for powering up the system.
When PD# is asserted LOW, clocks are driven to a LOW value
and held before turning off the VCOs and the crystal oscillator.
PD# (Power down) Assertion
Figure 2. Crystal Loading Example
,
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2.
Load Capacitance (each side)
Ce = 2 * CL – (Cs + Ci)
PD# Deassertion
Total Capacitance (as seen by the crystal)
CLe
=
1
1
( Ce1 + Cs1
+ Ci1 +
1
Ce2 + Cs2 + Ci2
When PD# is sampled LOW by two consecutive rising edges
of CPU clocks, all single-ended outputs will be held LOW on
their next HIGH-to-LOW transition and differential clocks must
held LOW. When PD# mode is desired as the initial power on
state, PD# must be asserted LOW in less than 10 s after
asserting CKPWRGD.
)
CL ................................................... Crystal load capacitance
CLe .........................................Actual loading seen by crystal
using standard value trim capacitors
The power up latency is less than 1.8 ms. This is the time from
the deassertion of the PD# pin or the ramping of the power
supply until the time that stable clocks are generated from the
clock chip. All differential outputs stopped in a three-state
condition, resulting from are driven high in less than 300 s of
PD# deassertion to a voltage greater than 200 mV. After the
clock chip’s internal PLL is powered up and locked, all outputs
are enabled within a few clock cycles of each clock. Figure 4
is an example showing the relationship of clocks coming up.
Ce .....................................................External trim capacitors
Cs ............................................. Stray capacitance (terraced)
Ci .......................................................... Internal capacitance
(lead frame, bond wires, etc.)
Figure 3. Power Down Assertion Timing Waveform
......................Document #: 001-08400 Rev ** Page 11 of 21
SL28773
Figure 4. Power Down Deassertion Timing Waveform
Figure 5. CKPWRGD Timing Diagram
CPU_STP# Assertion
CPU_STP# Deassertion
The CPU_STP# signal is an active LOW input used for
synchronous stopping and starting the CPU output clocks
while the rest of the clock generator continues to function.
When the CPU_STP# pin is asserted, all CPU outputs that are
set with the SMBus configuration to be stoppable are stopped
within two to six CPU clock periods after sampled by two rising
edges of the internal CPUC clock. The final states of the
stopped CPU signals are CPUT = HIGH and CPUC = LOW.
The deassertion of the CPU_STP# signal causes all stopped
CPU outputs to resume normal operation in a synchronous
manner. No short or stretched clock pulses are produced when
the clock resumes. The maximum latency from the
deassertion to active outputs is no more than two CPU clock
cycles.
CPU_STP#
CPUT
CPUC
Figure 6. CPU_STP# Assertion Waveform
......................Document #: 001-08400 Rev ** Page 12 of 21
SL28773
CPU_STP#
CPUT
CPUC
CPUT Internal
CPUC Internal
Tdrive_CPU_STP#,10 ns>200 mV
Figure 7. CPU_STP# Deassertion Waveform
......................Document #: 001-08400 Rev ** Page 13 of 21
SL28773
Absolute Maximum Conditions
Parameter
Description
VDD_3.3V
Main Supply Voltage
VDD_IO
IO Supply Voltage
Condition
Min.
Max.
Unit
–
4.6
V
3.465
V
VIN
Input Voltage
Relative to VSS
–0.5
4.6
VDC
TS
Temperature, Storage
Non-functional
–65
150
°C
TA
Temperature, Operating
Ambient
Functional
0
85
°C
TJ
Temperature, Junction
Functional
–
150
°C
ØJC
Dissipation, Junction to Case
MIL-STD-883E Method 1012.1
–
20
°C/
W
ØJA
Dissipation, Junction to Ambient JEDEC (JESD 51)
–
60
°C/
W
ESDHBM
ESD Protection (Human Body
Model)
MIL-STD-883, Method 3015
2000
–
V
UL-94
Flammability Rating
At 1/8 in.
Max.
Unit
3.135
3.465
V
2.0
VDD + 0.3
V
VSS – 0.3
0.8
V
2.2
–
V
V–0
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
DC Electrical Specifications
Parameter
Description
VDD core
3.3V Operating Voltage
VIH
3.3V Input High Voltage (SE)
Condition
3.3 ± 5%
VIL
3.3V Input Low Voltage (SE)
VIHI2C
Input High Voltage
SDATA, SCLK
VILI2C
Input Low Voltage
SDATA, SCLK
VIH_FS
FS Input High Voltage
VIL_FS
FS Input Low Voltage
IIH
Input High Leakage Current
Except internal pull-down resistors, 0 < VIN < VDD
IIL
Input Low Leakage Current
Except internal pull-up resistors, 0 < VIN < VDD
VOH
VOL
3.3V Output High Voltage (SE) IOH = –1 mA
3.3V Output Low Voltage (SE) IOL = 1 mA
VDD IO
Low Voltage IO Supply Voltage
IOZ
Min.
–
1.0
V
0.7
VDD+0.3
V
VSS – 0.3
0.35
V
–
5
A
–5
–
A
2.4
–
V
–
0.4
V
1
3.465
V
High-impedance Output
Current
–10
10
A
CIN
Input Pin Capacitance
1.5
5
pF
COUT
Output Pin Capacitance
6
pF
LIN
Pin Inductance
–
7
nH
VXIH
Xin High Voltage
0.7VDD
VDD
V
VXIL
Xin Low Voltage
0
0.3VDD
V
IDD_PD
Power Down Current
–
1
mA
IDD_3.3V
Dynamic Supply Current
All outputs enabled. SE clocks with 8” traces.
Differential clocks with 7” traces. Loading per
CK505 spec.
–
65
mA
IDD_VDD_IO
Dynamic Supply Current
All outputs enabled. SE clocks with 8” traces.
Differential clocks with 7” traces. Loading per
CK505 spec.
–
25
mA
......................Document #: 001-08400 Rev ** Page 14 of 21
SL28773
AC Electrical Specifications
Parameter
Description
Condition
Min.
Max.
Unit
47.5
52.5
%
69.841
71.0
ns
Crystal
TDC
XIN Duty Cycle
The device operates reliably with input
duty cycles up to 30/70 but the REF clock
duty cycle will not be within specification
TPERIOD
XIN Period
When XIN is driven from an external
clock source
TR/TF
XIN Rise and Fall Times
Measured between 0.3VDD and 0.7VDD
–
10.0
ns
TCCJ
XIN Cycle to Cycle Jitter
As an average over 1-s duration
–
500
ps
TDC
CPUT and CPUC Duty Cycle
Measured at 0V differential
45
55
%
TPERIOD
100 MHz CPUT and CPUC Period
Measured at 0V differential at 0.1s
9.99900
10.00100
ns
TPERIOD
133 MHz CPUT and CPUC Period
Measured at 0V differential at 0.1s
7.49925
7.50075
ns
TPERIODSS
100 MHz CPUT and CPUC Period, SSC Measured at 0V differential at 0.1s
10.02406
10.02607
ns
TPERIODSS
133 MHz CPUT and CPUC Period, SSC Measured at 0V differential at 0.1s
7.51804
7.51955
ns
TPERIODAbs
100 MHz CPUT and CPUC Absolute
period
Measured at 0V differential at 1 clock
9.91400
10.0860
ns
TPERIODAbs
133 MHz CPUT and CPUC Absolute
period
Measured at 0V differential at 1 clock
7.41425
7.58575
ns
TPERIODSSAbs 100 MHz CPUT and CPUC Absolute
period, SSC
Measured at 0V differential at1 clock
9.914063
10.1362
ns
TPERIODSSAbs 133 MHz CPUT and CPUC Absolute
period, SSC
Measured at 0V differential at1 clock
7.41430
7.62340
ns
–
85
ps
CPU at 0.7V
TCCJ
CPU Cycle to Cycle Jitter
Measured at 0V differential
Skew
CPU0 to CPU1 skew
Measured at 0V differential
–
100
ps
LACC
Long-term Accuracy
Measured at 0V differential
–
100
ppm
T R / TF
CPU Rising/Falling Slew rate
Measured differentially from ±150 mV
2.5
8
V/ns
TRFM
Rise/Fall Matching
Measured single-endedly from ±75 mV
–
20
%
VHIGH
Voltage High
1.15
V
VLOW
Voltage Low
–0.3
–
V
VOX
Crossing Point Voltage at 0.7V Swing
300
550
mV
SRC at 0.7V
TDC
SRC Duty Cycle
Measured at 0V differential
45
55
%
TPERIOD
100 MHz SRC Period
Measured at 0V differential at 0.1s
9.99900
10.0010
ns
TPERIODSS
100 MHz SRC Period, SSC
Measured at 0V differential at 0.1s
10.02406
10.02607
ns
TPERIODAbs
100 MHz SRC Absolute Period
Measured at 0V differential at 1 clock
9.87400
10.1260
ns
Measured at 0V differential at 1 clock
9.87406
10.1762
ns
–
3.0
ns
–
125
ps
TPERIODSSAbs 100 MHz SRC Absolute Period, SSC
TSKEW(window) Any SRC Clock Skew from the earliest Measured at 0V differential
bank to the latest bank
TCCJ
SRC Cycle to Cycle Jitter
Measured at 0V differential
LACC
SRC Long Term Accuracy
Measured at 0V differential
–
100
ppm
T R / TF
SRC Rising/Falling Slew Rate
Measured differentially from ±150 mV
2.5
8
V/ns
TRFM
Rise/Fall Matching
Measured single-endedly from ±75 mV
–
20
%
VHIGH
Voltage High
1.15
V
VLOW
Voltage Low
–0.3
–
V
VOX
Crossing Point Voltage at 0.7V Swing
300
550
mV
DOT96 at 0.7V
......................Document #: 001-08400 Rev ** Page 15 of 21
SL28773
AC Electrical Specifications (continued)
Parameter
Description
Condition
TDC
DOT96 Duty Cycle
Measured at 0V differential
Min.
Max.
Unit
45
55
%
10.4177
ns
ns
TPERIOD
DOT96 Period
Measured at 0V differential at 0.1s
10.4156
TPERIODAbs
DOT96 Absolute Period
Measured at 0V differential at 0.1s
10.1656
10.6677
TCCJ
DOT96 Cycle to Cycle Jitter
Measured at 0V differential at 1 clock
–
250
ps
LACC
DOT96 Long Term Accuracy
Measured at 0V differential at 1 clock
–
100
ppm
T R / TF
DOT96 Rising/Falling Slew Rate
Measured differentially from ±150 mV
2.5
8
V/ns
TRFM
Rise/Fall Matching
Measured single-endedly from ±75 mV
–
20
%
VHIGH
Voltage High
1.15
V
VLOW
Voltage Low
–0.3
–
V
VOX
Crossing Point Voltage at 0.7V Swing
300
550
mV
USB_48 at 3.3V
TDC
Duty Cycle
Measurement at 1.5V
45
55
%
TPERIOD
Period
Measurement at 1.5V
20.83125
20.83542
ns
TPERIODAbs
Absolute Period
Measurement at 1.5V
20.48125
21.18542
ns
THIGH
48_M High time
Measurement at 2V
8.216563
11.15198
ns
TLOW
48_M Low time
Measurement at 0.8V
7.816563
10.95198
ns
T R / TF
Rising and Falling Edge Rate
Measured between 0.8V and 2.0V
1.0
2.0
V/ns
TCCJ
Cycle to Cycle Jitter
Measurement at 1.5V
–
350
ps
LACC
48M Long Term Accuracy
Measurement at 1.5V
–
100
ppm
Measurement at 1.5V
45
55
%
27M_NSS/27_SS at 3.3V
TDC
Duty Cycle
TPERIOD
Spread 27M Period
Measurement at 1.5V
37.03594
37.03813
ns
Spread Enabled 27M Period
Measurement at 1.5V
37.12986
37.13172
ns
T R / TF
Rising and Falling Edge Rate
Measured between 0.8V and 2.0V
1.0
4.0
V/ns
TCCJ
Cycle to Cycle Jitter
Measurement at 1.5V
–
300
ps
LACC
27_M Long Term Accuracy
Measured at crossing point VOX
–
50
ppm
REF
TDC
REF Duty Cycle
Measurement at 1.5V
45
55
%
TPERIOD
REF Period
Measurement at 1.5V
69.82033
69.86224
ns
TPERIODAbs
REF Absolute Period
Measurement at 1.5V
68.83429
70.84826
ns
THIGH
REF High time
Measurement at 2V
29.97543
38.46654
ns
TLOW
REF Low time
Measurement at 0.8V
29.57543
38.26654
ns
T R / TF
REF Rising and Falling Edge Rate
Measured between 0.8V and 2.0V
1.0
4.0
V/ns
TSKEW
REF Clock to REF Clock
Measurement at 1.5V
–
500
ps
TCCJ
REF Cycle to Cycle Jitter
Measurement at 1.5V
–
1000
ps
LACC
Long Term Accuracy
Measurement at 1.5V
–
100
ppm
–
1.8
ms
10.0
–
ns
ENABLE/DISABLE and SET-UP
TSTABLE
Clock Stabilization from Power-up
TSS
Stopclock Set-up Time
......................Document #: 001-08400 Rev ** Page 16 of 21
SL28773
Test and Measurement Set-up
For USB_48 and REF clocks
The following diagram shows the test load configurations for
the single-ended USB_48 and REF output signals.
Figure 8. Single-ended USB_48 Clock Double Load Configuration
.
Figure 9. Single-ended REF Triple Load Configuration
Figure 10. Single-ended Output Signals (for AC Parameters Measurement)
......................Document #: 001-08400 Rev ** Page 17 of 21
SL28773
For Differential Clock Signals
This diagram shows the test load configuration for the differential clock signals
Figure 11. 0.7V Differential Load Configuration
Figure 12. Differential Measurement for Differential Output Signals (for AC Parameters Measurement)
......................Document #: 001-08400 Rev ** Page 18 of 21
SL28773
Figure 13. Single-ended Measurement for Differential Output Signals (for AC Parameters Measurement)
......................Document #: 001-08400 Rev ** Page 19 of 21
SL28773
Ordering Information
Part Number
Package Type
Product Flow
Lead-free
SL28773ELC
32-pin QFN
Commercial, 0 to 85C
SL28773ELCT
32-pin QFN–Tape and Reel
Commercial, 0 to 85C
SL 28 773 ELC - T
Packaging Designator for Tape and Reel
Temperature Designator
Package Designator
L : QFN
Revision Number
A = 1st Silicon
Generic Part Number
Designated Family Number
Company Initials
This device is Pb free and RoHS compliant.
Package Diagrams
32-Lead QFN 5x 5mm (Saw Version)
......................Document #: 001-08400 Rev ** Page 20 of 21
SL28773
Document History Page
Document Title: SL28773 PC EProClock® Generator for Intel Calpella Chipset
REV.
Issue Date
Orig. of
Change
1.0
10/9/08
JMA
Initial Release
1.1
10/23/08
JMA
1. Changed operating temperature to 0-85C
2. Re-aligned ordering part number description
1.2
1/27/09
JMA
1. Updated Rev. ID
2. Uddated definition of Byte 6 bit 5 and 3
3. Updated Byte 13 and single-ended slew rate table
4. Udated Byte 14
5. Updated Feature description
6. Added less than symbol in power consumption value
7. Updated ordering part number
8. Changed package information
9. Changed Wireless Friendly Mode to 111
1.3
3/16/09
JMA
1. Added PC EProClock® Programmed Technology in Feature section
2. Updated Block Diagram
3. Updated 27MHz slew rate measurement window
4. Updated power consumption
1.4
3/25/09
JMA
1. Updated Package information removed punch version with saw version
2. Updated TPeriod at 100MHz for CPU clocks
3. Updated Revision ID
4. Added Power down Spec
5. Added PC EProClock® Technology description
6. Added CPU Skew
7. Removed 3-bit differential slew rate
8. Change SATA PLL from PLL2 to PLL4.
1.5
9/8/09
JMA
1. Removed Preliminary word
1.6
01/05/10
JMA
1. Added Note in package diagram
2. Updated text content
3. Added information on trace length in Figure 8
4. Removed CPU Driven Figures
5. Updated VDD_IO spec to 4.6V maximum value
6. Edited CK_PWRGD to CKPWRGD
Description of Change
......................Document #: 001-08400 Rev ** Page 21 of 21
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"Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories reserves the right to
make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the
included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses
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