SL28EB740
EProClock® Generator for Intel Tunnel Creek & Top Cliff
Features
• Buffered Reference Clock 25MHz
• 25MHz Crystal Input or Clock input
• Compliant Intel CK505 Clock spec
• Support Wake-On-LAN (WOL)
• Low power push-pull type differential output buffers
• EProClock® Programmable Technology
• Integrated resistors on differential clocks
• I2C support with readback capabilities
• Wireless friendly 3-bits slew rate control on
single-ended clocks.
• Triangular Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• Differential CPU clocks with selectable frequency
• Industrial Temperature -40oC to 85oC
• 100MHz Differential SRC clocks
• 3.3V Power supply
• 75MHz Differential SATA clocks
• 56-pin TSSOP package
• 96MHz Differential DOT clock
• 48MHz USB clock
CPU
SRC
• Selectable 12 or 48MHz output
x2/x3
x4/x7
SATA75 DOT96
x0/x1
x1
48M
x1/2
48M/12M 33M
x1
x2
25M
14.318M
x1
x1
• 14.318MHz output
Block Diagram
XIN
XOUT
Crystal/
CLKIN
Pin Configuration
REF [1:0]
PLL 1
(SSC)
CPU
Divider
SRC
PCI
PLL 2
(SSC)
56 NC
55 GND_14M
CLKREQ#1** 3
54 14M / FSC**
CLKREQ#2** 4
53 VDD_14M
PCI0/ SEL_SATA75** 5
FS [ C:A]
CPU_STP#
NC 1
NC 2
51 VDD_SUSP
VDD_PCI 7
50 25M
8
49 GND
PCIF/ ITP_EN**
Divider
CLKREQ#3** 9
SATA75M / SRC0
ITP_EN
12M_48M/ SEL12_48* 10
VDD_48 11
PCI/SRC_STP#
PLL 3
(non-SSC)
DOT96
Divider
48M/ FSA** 12
GND_48 13
CLKREQ[3:1]
48M
DOT96 14
DOT96# 15
SEL_SATA75
PLL 4
(non-SSC)
12 / 48M
Divider
FSB** 16
GND_SATA 17
SATA75M / SRC0 18
SEL_12_48
SATA75M# / SRC0# 19
14.318M
VDD_SATA 20
SRC1 21
OTP
SRC1# 22
SCLK
SDATA
Logic Core
CKPWRGD/
PD#
VR
52 CKPWRGD / WOL_STP# / PD#
GND_PCI 6
48 XIN / CLKIN
47 XOUT
46 PCI/SRC_STP#*
45 CPU_STP#*
44 SDATA
43 SCLK
42 GND_CPU
41 CPU0
40 CPU0#
39 VDD_CPU
38 CPU1
37 CPU1#
36 CPU2_ITP / SRC6
35 CPU2#_ITP / SRC6#
SRC2 23
34 VDD_SRC
SRC2# 24
33 GND_SRC
SRC3 25
32 SRC5
SRC3# 26
31 SRC5#
GND_SRC 27
30 SRC4
VDD_SRC 28
29 SRC4#
* Internal 100K-ohm pull-up resistor
** Internal 100K-ohm pull down resistor
DOC#: SP-AP-0006 (Rev. AC)
400 West Cesar Chavez, Austin, TX 78701
1+(512) 416-8500
1+(512) 416-9669
Page 1 of 21
www.silabs.com
SL28EB740
56-TSSOP Pin Definitions
Pin No.
Name
1
NC
2
NC
3
CLKREQ#1**
4
CLKREQ#2**
5
PCI0 / SEL_SATA75**
Type
NC
NC
Description
No Connect.
No Connect.
I, PD
3.3V clock request input (internal 100K-ohm pull-down)
I, PD
3.3V clock request input (internal 100K-ohm pull-down)
I/O, SE 33MHz clock output/3.3V LVTTL input to enable 75MHz SATA (internal
PD
100K-ohm pull-down)
0 = SATA75/SRC0 = 100MHz, 1 = SATA75/SRC0 = 75MHz
6
GND_PCI
GND
Ground
7
VDD_PCI
PWR
3.3V Power supply
8
PCIF / ITP_EN**
9
CLKREQ#3**
10
12_48M / SEL12_48*
11
VDD_48
12
48M / FSA**
13
GND_48
14
DOT96
O, DIF Fixed true 96MHz clock output
15
DOT96#
O, DIF Fixed complement 96MHz clock output
16
FSB**
I/O, SE, 33 MHz free running clock output/3.3V LVTTL input to enable SRC6 or
PD
CPU2_ITP (sampled on the CKPWRGD assertion)
0= SRC6, 1= CPU2
I, PD
3.3V clock request input (internal 100K-ohm pull-down)
I/O, SE 12 MHz/ 48MHz Clock output/3.3V-tolerance input for 12MHz or 48MHz
PU
selection (Sampled at CKPWRGD assertion) (internal 100K-ohm pull-up)
0 = 48M, 1 = 12M
PWR
I/O
PD
GND
3.3V Power supply
Fixed 48 MHz clock output/3.3V-tolerant input for CPU frequency selection
(internal 100K-ohm pull-down)
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
Ground
I, PD
3.3V-tolerant input for CPU frequency selection (internal 100K-ohm pull-down)
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
GND
Ground
17
GND_SATA
18
SATA75M / SRC0
O, DIF 75MHz or 100MHz True differential serial reference clock
19
SATA75M# / SRC0#
O, DIF 75MHz or 100MHz Complement differential serial reference clock
20
VDD_SATA
21
SRC1
O, DIF 100MHz True differential serial reference clock
22
SRC1#
O, DIF 100MHz Complement differential serial reference clock
23
SRC2
O, DIF 100MHz True differential serial reference clock
24
SRC2#
O, DIF 100MHz Complement differential serial reference clock
25
SRC3
O, DIF 100MHz True differential serial reference clock
26
SRC3#
O, DIF 100MHz Complement differential serial reference clock
PWR
3.3V Power supply
27
GND_SRC
GND
Ground
28
VDD_SRC
PWR
3.3V Power supply
29
SRC4#
O, DIF 100MHz True differential serial reference clock
30
SRC4
O, DIF 100MHz Complement differential serial reference clock
31
SRC5#
O, DIF 100MHz True differential serial reference clock
32
SRC5
O, DIF 100MHz Complement differential serial reference clock
33
GND_SRC
GND
Ground
34
VDD_SRC
PWR
3.3V Power supply
35
SRC6# / CPU2#_ITP
DOC#: SP-AP-0006 (Rev. AC)
O, DIF Selectable complementary differential CPU or SRC clock output.
ITP_EN = 0 @ CKPWRGD assertion = SRC6
ITP_EN = 1 @ CKPWRGD assertion = CPU2
Page 2 of 21
SL28EB740
56-TSSOP Pin Definitions (continued)
Pin No.
36
Name
SRC6 / CPU2_ITP
Type
Description
O, DIF Selectable True differential CPU or SRC clock output.
ITP_EN = 0 @ CKPWRGD assertion = SRC6
ITP_EN = 1 @ CKPWRGD assertion = CPU2
37
CPU1#
O, DIF Complement differential CPU clock output
38
CPU1
O, DIF True differential CPU clock output
39
VDD_CPU
PWR
3.3V Power supply
40
CPU0#
O, DIF Complement differential CPU clock output
41
CPU0
O, DIF True differential CPU clock output
42
GND_CPU
43
SCLK
GND
I
SMBus compatible SCLOCK
44
SDATA
45
CPU_STP#*
I, PU
3.3V-tolerant input for stopping CPU outputs (internal 100K-ohm pull-up)
46
PCI/SRC_STP#*
I, PU
3.3V-tolerant input for stopping PCI and SRC outputs (internal 100K-ohm
pull-up)
47
XOUT
O
25.00MHz Crystal output, Float XOUT if using only CLKIN (Clock input)
48
XIN / CLKIN
I
25.00MHz Crystal input or 3.3V, 25MHzClock Input
49
GND_SUSPEND
50
25MHz
51
VDD_SUSPEND
52
CKPWRGD/WOL_STP#/PD#
53
VDD_14
54
14.318M / FSC**
55
GND_14
56
NC
I/O
Ground
GND
O
PWR
I
PWR
SMBus compatible SDATA
Ground for REF clock and WOL support
25MHz reference output clock
3.3V Power Supply for REF clock and power to support WOL
3.3V LVTTL input. This pin is a level sensitive strobe used to determine
when latch inputs are valid and are ready to be sampled /
Asynchronous active low input pin that stops all outputs except free running
25MHz when WOL_EN = “1” (Byte 1 bit 1)
This pin becomes a real-time active low input for asserting power down (PD#)
when WOL_EN = “0” (Byte 1 bit 1).
3.3V Power supply
I/O, PD Fixed 14.318MHz clock output/3.3V-tolerant input for CPU frequency selection
(internal 100K-ohm pull-down)
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
GND
NC
Ground
No Connect.
EProClock® Programmable Technology
EProClock® is the world’s first non-volatile programmable
clock. The EProClock® technology allows board designer to
promptly achieve optimum compliance and clock signal
integrity; historically, attainable typically through device and/or
board redesigns.
- Custom frequency sets
EProClock® technology can be configured through SMBus or
hard coded.
- Differential and single-ended slew rate control
- Differential skew control on true or compliment or both
- Differential duty cycle control on true or compliment or both
- Differential amplitude control
Features:
- Program Internal or External series resistor on single-ended
clocks
- > 4000 bits of configurations
- Program different spread profiles
- Can be configured through SMBus or hard coded
- Program different spread modulation rate
DOC#: SP-AP-0006 (Rev. AC)
Page 3 of 21
SL28EB740
Frequency Select Pin (FS)
SEL_SATA
FSC
FSB
FSA
CPU
SRC
SATA
PCI
0
0
0
0
100.00
100.00
100.00
33.33
0
0
0
1
100.00
100.00
100.00
33.33
0
0
1
0
83.33
100.00
100.00
33.33
0
0
1
1
83.33
100.00
100.00
33.33
0
1
0
0
133.33
100.00
100.00
33.33
0
1
0
1
133.33
100.00
100.00
33.33
0
1
1
0
166.67
100.00
100.00
33.33
0
1
1
1
166.67
100.00
100.00
33.33
1
0
0
0
100.00
100.00
75.00
33.33
1
0
0
1
100.00
100.00
75.00
33.33
1
0
1
0
83.33
100.00
75.00
33.33
1
0
1
1
83.33
100.00
75.00
33.33
1
1
0
0
133.33
100.00
75.00
33.33
1
1
0
1
133.33
100.00
75.00
33.33
1
1
1
0
166.67
100.00
75.00
33.33
1
1
1
1
166.67
100.00
75.00
33.33
Frequency Select Pin FS
Serial Data Interface
Apply the appropriate logic levels to FS inputs before
CKPWRGD assertion to achieve host clock frequency
selection. When the clock chip sampled HIGH on CKPWRGD
and indicates that VTT voltage is stable then FS input values
are sampled. This process employs a one-shot functionality
and once the CKPWRGD sampled a valid HIGH, all other FS,
and CKPWRGD transitions are ignored except in test mode.
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers are individually enabled or disabled. The
registers associated with the Serial Data Interface initialize to
their default setting at power-up. The use of this interface is
optional. Clock device register changes are normally made at
system initialization, if any are required. The interface cannot
be used during system operation for power management
functions.
Wake-On-LAN (WOL) Support
When power is applied to the VDD_SUSPEND pin, the 25MHz
reference clock output will be enabled under all conditions,
unless the WOL_EN bit, Byte 1 bit 1, is set to “0”. When the
WOL_EN bit Byte 1 bit 1, is set to “0”, the WOL_STP# pin will
function as a PD# pin. By default, the WOL_EN bit is enabled
and set to a “1”. The clock device will support “out-of-the-box”
WOL or after a power outage by enabling the 25MHz reference
clock output when the clock device powers up for the very first
time with only power applied to the VDD_SUSPEND pin and
all other VDD pins power have not been applied.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, access the bytes in sequential
order from lowest to highest (most significant bit first) with the
ability to stop after any complete byte is transferred. For byte
write and byte read operations, the system controller can
access individually indexed bytes. The offset of the indexed
byte is encoded in the command code described in Table 1.
The block write and block read protocol is outlined in Table 2
while Table 3 outlines byte write and byte read protocol. The
slave receiver address is 11010010 (D2h).
Table 1. Command Code Definition
Bit
7
(6:0)
Description
0 = Block read or block write operation, 1 = Byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
DOC#: SP-AP-0006 (Rev. AC)
Page 4 of 21
SL28EB740
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
8:2
9
10
18:11
19
27:20
28
36:29
37
45:38
Description
Start
Block Read Protocol
Bit
1
Slave address–7 bits
Write
8:2
9
Acknowledge from slave
Command Code–8 bits
10
18:11
Description
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
19
Acknowledge from slave
Byte Count–8 bits
20
Repeat start
Acknowledge from slave
Data byte 1–8 bits
Acknowledge from slave
Data byte 2–8 bits
27:21
Read = 1
29
Acknowledge from slave
37:30
46
Acknowledge from slave
....
Data Byte /Slave Acknowledges
....
Data Byte N–8 bits
....
Acknowledge from slave
....
Stop
Slave address–7 bits
28
38
46:39
47
55:48
Byte Count from slave–8 bits
Acknowledge
Data byte 1 from slave–8 bits
Acknowledge
Data byte 2 from slave–8 bits
56
Acknowledge
....
Data bytes from slave / Acknowledge
....
Data Byte N from slave–8 bits
....
NOT Acknowledge
....
Stop
Table 3. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
8:2
Description
Start
Slave address–7 bits
Byte Read Protocol
Bit
1
8:2
Description
Start
Slave address–7 bits
9
Write
9
Write
10
Acknowledge from slave
10
Acknowledge from slave
18:11
19
27:20
Command Code–8 bits
Acknowledge from slave
Data byte–8 bits
28
Acknowledge from slave
29
Stop
18:11
19
20
27:21
Acknowledge from slave
Repeated start
Slave address–7 bits
28
Read
29
Acknowledge from slave
37:30
DOC#: SP-AP-0006 (Rev. AC)
Command Code–8 bits
Data from slave–8 bits
38
NOT Acknowledge
39
Stop
Page 5 of 21
SL28EB740
Control Registers
Byte 0: Control Register 0
Bit
@Pup
Name
Description
7
0
RESERVED
RESERVED
6
0
RESERVED
RESERVED
5
0
Spread Enable
4
HW
SEL_SATA
See Table 1 for SATA/SRC selection.
3
0
RESERVED
RESERVED
2
HW
FSC
1
HW
FSB
0
HW
FSA
Enable spread for CPU/SRC/PCI outputs
0=Disable, 1= -0.5%
See Table 1 for CPU Frequency selection Table
Byte 1: Control Register 1
Bit
@Pup
Name
7
1
DOT96_OE
Output enable for DOT96
0 = Output Disabled, 1 = Output Enabled
Description
6
1
SATA75/SRC0_OE
Output enable for SATA75/SRC0
0 = Output Disabled, 1 = Output Enabled
5
1
CPU2/SRC6_OE
Output enable for CPU2/SRC6
0 = Output Disabled, 1 = Output Enabled
4
1
SRC2
Output enable for SRC2
0 = Output Disabled, 1 = Output Enabled
3
1
SRC1
Output enable for SRC1
0 = Output Disabled, 1 = Output Enabled
2
1
RESERVED
1
1
WOL_EN
0
0
RESERVED
RESERVED
Wake-On-LAN Enable bit
25MHz free running during VDD Suspend (S-states). If this bit is set to 0,
the XTAL OSC will also be powered down in the Suspend States)
RESERVED
Byte 2: Control Register 2
Bit
@Pup
Name
7
1
48M_OE
6
0
RESERVED
5
1
14M_OE
Output enable for 14M
0 = Output Disabled, 1 = Output Enabled
4
1
25M_OE
Output enable for 25M
0 = Output Disabled, 1 = Output Enabled
3
1
12_48M_OE
Output enable for 12_48M
0 = Output Disabled, 1 = Output Enabled
2
1
PCI0_OE
Output enable for PCI0
0 = Output Disabled, 1 = Output Enabled
1
1
PCIF_OE
Output enable for PCIF
0 = Output Disabled, 1 = Output Enabled
0
0
RESERVED
DOC#: SP-AP-0006 (Rev. AC)
Description
Output enable for 48M
0 = Output Disabled, 1 = Output Enabled
RESERVED
RESERVED
Page 6 of 21
SL28EB740
Byte 3: Control Register 3
Bit
@Pup
Name
7
1
CPU1_OE
Output enable for CPU1
0 = Output Disabled, 1 = Output Enabled
Description
6
1
CPU0_OE
Output enable for CPU0
0 = Output Disabled, 1 = Output Enabled
5
0
CLKREQ#_3
Clock request for SRC2
0=Not controlled, 1= Controlled
4
0
CLKREQ#_3
Clock request for SRC6 (does not apply to CPU clock)
0=Not controlled, 1= Controlled
3
0
CLKREQ#_2
Clock request for SRC2
0=Not controlled, 1= Controlled
2
0
CLKREQ#_2
Clock request for SATA75M/SRC0
0=Not controlled, 1= Controlled
1
0
CLKREQ#_1
Clock request for SRC1
0=Not controlled, 1= Controlled
0
0
CLKREQ#_1
Clock request for SATA75M/SRC0
0=Not controlled, 1= Controlled
Byte 4: Control Register 4
Bit
@Pup
Name
7
0
RESERVED
6
0
CPU1
5
HW
12_48M
4
0
CPU2
3
HW
ITP_EN
2
0
RESERVED
1
0
CPU0
0
0
RESERVED
Description
RESERVED
CPU1 Free Run Control
0= Free Running, 1= Stoppable
Selectable 12_48M status
0= 48M, 1=12M
CPU2 Free Run Control
0= Free Running, 1= Stoppable
SelectableCPUe_ITP/ SRC6 status
0= SRC6, 1=CPU2
RESERVED
CPU0 Free Run Control
0= Free Running, 1= Stoppable
RESERVED
Byte 5: Control Register 5
Bit
@Pup
Name
7
0
RESERVED
RESERVED
6
0
RESERVED
RESERVED
5
0
RESERVED
RESERVED
4
1
SATA75/SRC0
SATA75/SRC0 Free Run Control
0= Free Running, 1= Stoppable
3
0
SRC6
SRC6 Free Run Control
0= Free Running, 1= Stoppable
2
0
SRC2
SRC2 Free Run Control
0= Free Running, 1= Stoppable
1
0
SRC1
SRC1 Free Run Control
0= Free Running, 1= Stoppable
0
0
RESERVED
DOC#: SP-AP-0006 (Rev. AC)
Description
RESERVED
Page 7 of 21
SL28EB740
Byte 6: Control Register 6
Bit
@Pup
Name
7
0
CPU_AMP
6
1
CPU_AMP
5
0
SRC_AMP
4
1
SRC_AMP
3
0
DOT96_AMP
2
1
DOT96_AMP
1
0
SATA_AMP
0
1
SATA_AMP
Description
CPU amplitude adjustment
00= 700mV, 01=800mV, 10=900mV, 11= 1000mV
SRC amplitude adjustment
00= 700mV, 01=800mV, 10=900mV, 11= 1000mV
DOT96 amplitude adjustment
00= 700mV, 01=800mV, 10=900mV, 11= 1000mV
SATA75/SRC0 amplitude adjustment
00= 700mV, 01=800mV, 10=900mV, 11= 1000mV
Byte 7: Vendor ID
Bit
@Pup
Name
7
0
Rev Code Bit 3
Revision Code Bit 3
Description
6
0
Rev Code Bit 2
Revision Code Bit 2
5
0
Rev Code Bit 1
Revision Code Bit 1
4
1
Rev Code Bit 0
Revision Code Bit 0
3
1
Vendor ID bit 3
Vendor ID Bit 3
2
0
Vendor ID bit 2
Vendor ID Bit 2
1
0
Vendor ID bit 1
Vendor ID Bit 1
0
0
Vendor ID bit 0
Vendor ID Bit 0
Byte 8: Control Register 8
Bit
@Pup
Name
7
0
BC7
6
0
BC6
5
0
BC5
4
0
BC4
3
1
BC3
2
1
BC2
1
1
BC1
0
1
BC0
Description
Byte count register for block read operation.
The default value for Byte count is 15
In order to read beyond Byte 15, the user should change the byte count
limit.to or beyond the byte that is desired to be read.
Byte 9: Control Register 9
Bit
@Pup
Name
7
1
SRC5
Output enable for SRC5
0 = Output Disabled, 1 = Output Enabled
6
1
SRC4
Output enable for SRC4
0 = Output Disabled, 1 = Output Enabled
5
1
SRC3
Output enable for SRC3
0 = Output Disabled, 1 = Output Enabled
4
0
SRC5
SRC5 Free Run Control
0= Free Running, 1= Stoppable
3
0
SRC4
SRC4 Free Run Control
0= Free Running, 1= Stoppable
2
0
SRC3
SRC3 Free Run Control
0= Free Running, 1= Stoppable
DOC#: SP-AP-0006 (Rev. AC)
Description
Page 8 of 21
SL28EB740
Byte 9: Control Register 9 (continued)
1
0
PCI0
PCI0 Free Run Control
0= Free Running, 1= Stoppable
0
1
PCIF
PCIF Free Run Control
0= Free Running, 1= Stoppable
Byte 10: Control Register 10
Bit
@Pup
Name
Description
7
0
RESERVED
RESERVED
6
0
RESERVED
RESERVED
5
0
RESERVED
RESERVED
4
0
RESERVED
RESERVED
3
0
RESERVED
RESERVED
2
0
RESERVED
RESERVED
1
0
RESERVED
RESERVED
0
0
RESERVED
RESERVED
Byte 11: Control Register 11
Bit
@Pup
Name
7
1
14M_Bit2
6
0
14M_Bit1
5
1
14M_Bit0
4
1
25M_Bit2
3
0
25M_Bit1
2
1
25M_Bit0
1
1
12_48M_Bit2
0
1
12_48M_Bit0
Description
Drive Strength Control - Bit[2:0] Normal mode default ‘101’
Wireless Friendly Mode default to ‘111’
Byte 12: Byte Count
Bit
@Pup
Name
7
1
48M_Bit2
6
0
48M_Bit1
5
1
48M_Bit0
4
1
PCI0_Bit2
3
0
PCI0_Bit1
2
1
PCI0_Bit0
1
0
RESERVED
0
0
12_48M_Bit1
DOC#: SP-AP-0006 (Rev. AC)
Description
Drive Strength Control - Bit[2:0] Normal mode default ‘101’
Wireless Friendly Mode default to ‘111’
Page 9 of 21
SL28EB740
Byte 13: Control Register 13
Bit
@Pup
Name
Description
7
1
PCIF_Bit2
6
0
PCIF_Bit1
Drive Strength Control - Bit[2:0] Normal mode default ‘101’
Wireless Friendly Mode default to ‘111’
5
1
PCIF_Bit0
4
0
RESERVED
RESERVED
3
0
RESERVED
RESERVED
2
0
RESERVED
RESERVED
1
0
RESERVED
0
0
Wireless Friendly mode
RESERVED
Wireless Friendly Mode
0 = Disabled, Default all single-ended clocks slew rate config bits to ‘101’
1 = Enabled, Default all single-ended clocks slew rate config bits to ‘111’
Byte 14: Control Register 14
Bit
@Pup
Name
7
1
RESERVED
RESERVED
Description
6
0
RESERVED
RESERVED
5
1
RESERVED
RESERVED
4
0
OTP_4
3
0
OTP_3
2
0
OTP_2
1
0
OTP_1
0
0
OTP_0
OTP_ID
Idenification for programmed device
.
Table 4. Output Driver Status during CPU_STP# & PCIS_STP#
CPU_STP#
Asserted
Single-ended Clocks Stoppable
Differential Clocks
PCI_STP#
Asserted
CLKREQ#
Asserted
Running
Driven Low
Running
Non stoppable
Running
Running
Running
Stoppable
Clock driven high
Clock driven high
Clock driven low
Non stoppable
Clock# driven low
Clock# driven low
Clock# driven low
Running
Running
Running
SMBus OE Disabled
Driven low
Clock driven low
Table 5. Output Driver Status
All Single-ended Clocks
PD# = 0 (Power down)
All Differential Clocks
w/o Strap
w/ Strap
Clock
Low
Hi-z
Low
Clock#
Low
C
DOC#: SP-AP-0006 (Rev. AC)
Page 10 of 21
SL28EB740
PD# (Power down) Clarification
The CKPWRGD/PD# pin is a dual-function pin. During initial
power up, the pin functions as CKPWRGD. Once CKPWRGD
has been sampled HIGH by the clock chip, the pin assumes
PD# functionality. The PD# pin is an asynchronous active
LOW input used to shut off all clocks cleanly before shutting
off power to the device. This signal is synchronized internally
to the device before powering down the clock synthesizer. PD#
is also an asynchronous input for powering up the system.
When PD# is asserted LOW, clocks are driven to a LOW value
and held before turning off the VCOs and the crystal oscillator.
PD# (Power down) Assertion
When PD# is sampled LOW by two consecutive rising edges
of CPUC, all single-ended outputs will be held LOW on their
next HIGH-to-LOW transition and differential clocks must held
LOW. When power down mode is desired as the initial power
on state, PD# must be asserted LOW in less than 10 s after
asserting CKPWRGD.
PD# Deassertion
The power up latency is less than 1.8 ms. This is the time from
the deassertion of the PD# pin or the ramping of the power
supply until the time that stable clocks are generated from the
clock chip. All differential outputs stopped in a three-state
condition, resulting from power down are driven high in less
than 300 s of PD# deassertion to a voltage greater than
200 mV. After the clock chip’s internal PLL is powered up and
locked, all outputs are enabled within a few clock cycles of
each clock. Figure 2 is an example showing the relationship of
clocks coming up.
PD#
CPUT, 133MHz
CPUC, 133MHz
SRCT 100MHz
SRCC 100MHz
USB, 48MHz
DOT96T
DOT96C
PCI, 33 MHz
REF
Figure 1. Power down Assertion Timing Waveform
Ts ta b le
< 1 .8 m s
PD#
C P U T , 1 3 3 MH z
C P U C , 1 3 3 MH z
S R C T 1 0 0 MH z
S R C C 1 0 0 MH z
U S B , 4 8 MH z
D OT 9 6 T
D OT 9 6 C
P C I, 3 3 MH z
REF
Td r iv e _ PW R D N #
2 00m V
Figure 2. Power down Deassertion Timing Waveform
DOC#: SP-AP-0006 (Rev. AC)
Page 11 of 21
SL28EB740
FS _A, FS _B ,FS_C ,FS _D
CKPWRGD
P W R G D _V R M
0.2-0.3 m s
D elay
V D D C lock G en
C lock S tate
C lock O utputs
C lock V C O
S tate 0
W ait for
V TT_PW R G D #
D evice is not affected,
V TT_P W R G D # is ignored
S am ple S els
S tate 1
State 2
O ff
State 3
On
On
O ff
Figure 3. CKPWRGD Timing Diagram
CPU_STP# Assertion
CPU_STP# Deassertion
The CPU_STP# signal is an active LOW input used for
synchronous stopping and starting the CPU output clocks
while the rest of the clock generator continues to function.
When the CPU_STP# pin is asserted, all CPU outputs that are
set with the SMBus configuration to be stoppable are stopped
within two to six CPU clock periods after sampled by two rising
edges of the internal CPUC clock. The final states of the
stopped CPU signals are CPUT = HIGH and CPUC = LOW.
The deassertion of the CPU_STP# signal causes all stopped
CPU outputs to resume normal operation in a synchronous
manner. No short or stretched clock pulses are produced when
the clock resumes. The maximum latency from the
deassertion to active outputs is no more than two CPU clock
cycles.
CPU_STP#
CPUT
CPUC
Figure 4. CPU_STP# Assertion Waveform
CPU_STP#
CPUT
CPUC
CPUT Internal
CPUC Internal
Tdrive_CPU_STP#,10 ns>200 mV
Figure 5. CPU_STP# Deassertion Waveform
DOC#: SP-AP-0006 (Rev. AC)
Page 12 of 21
SL28EB740
PCI/SRC_STP# Assertion
The PCI/SRC_STP# signal is an active LOW input used for
synchronously stopping and starting the PCI outputs while the
rest of the clock generator continues to function. The set-up
time for capturing PCI/SRC_STP# going LOW is 10 ns (tSU).
(See Figure 6.) The PCIF and SRC clocks are affected by this
pin if their corresponding control bit in the SMBus register is
set to allow them to be free running. For SRC clocks assertion
description, please refer to CPU_STP# description.
.
Figure 6. PCI/SRC_STP# Assertion Waveform
PCI/SRC_STP# Deassertion
The deassertion of the PCI/SRC_STP# signal causes all PCI
and stoppable PCIF to resume running in a synchronous
manner within two PCI clock periods, after PCI/SRC_STP#
transitions to a HIGH level. Simlarly, PCI/SRC_STP#
deassertion will cause stoppable SRC clocks to resume
running. For SRC clocks deassertion description, please refer
to CPU_STP# description.
.
Figure 7. PCI/SRC_STP# Deassertion Waveform
.
.
DOC#: SP-AP-0006 (Rev. AC)
Page 13 of 21
SL28EB740
Absolute Maximum Conditions
Parameter
Description
Condition
VDD_3.3V
Main Supply Voltage
VIN
Input Voltage
Relative to VSS
TS
Temperature, Storage
Non-functional
TA
Temperature, Operating
Ambient
Functional
Functional
Min.
Max.
Unit
–
4.6
V
–0.5
4.6
VDC
–65
150
°C
–40
85
°C
TJ
Temperature, Junction
Functional
–
150
°C
ØJC
Dissipation, Junction to Case
JEDEC (JESD 51)
–
20
°C/
W
ØJA
Dissipation, Junction to Ambient JEDEC (JESD 51)
–
60
°C/
W
ESDHBM
ESD Protection (Human Body
Model)
JEDEC (JESD 22 - A114)
2000
–
V
UL-94
Flammability Rating
UL (Class)
V–0
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
DC Electrical Specifications
Parameter
Description
Min.
Max.
Unit
3.135
3.465
V
3.3V Input High Voltage (SE)
2.0
VDD + 0.3
V
3.3V Input Low Voltage (SE)
VSS – 0.3
0.8
V
VDD core
3.3V Operating Voltage
VIH
VIL
Condition
3.3 ± 5%
VIHI2C
Input High Voltage
SDATA, SCLK
2.2
–
V
VILI2C
Input Low Voltage
SDATA, SCLK
–
1.0
V
VIH_FS
FS Input High Voltage
0.7
VDD+0.3
V
VIL_FS
FS Input Low Voltage
VSS – 0.3
0.35
V
IIH
Input High Leakage Current
Except internal pull-down resistors, 0 < VIN <
VDD
–
5
A
IIL
Input Low Leakage Current
Except internal pull-up resistors, 0 < VIN < VDD
–5
–
A
VOH
3.3V Output High Voltage (SE) IOH = –1 mA
3.3V Output Low Voltage (SE) IOL = 1 mA
2.4
–
V
–
0.4
V
IOZ
High-impedance Output
Current
–10
10
A
CIN
Input Pin Capacitance
1.5
5
pF
COUT
Output Pin Capacitance
LIN
Pin Inductance
IDD_PD
Power Down Current
IDD_3.3V
Dynamic Supply Current
VOL
DOC#: SP-AP-0006 (Rev. AC)
–
All outputs enabled. SE clocks with 5” traces.
Differential clocks with 5” traces. Loading per
CK505 spec.
6
pF
7
nH
–
1
mA
–
115
mA
Page 14 of 21
SL28EB740
AC Electrical Specifications
Parameter
Description
Condition
Min.
Max.
Unit
–
250
ppm
Crystal
LACC
Long-term Accuracy
Measured at VDD/2 differential
Clock Input
TDC
CLKIN Duty Cycle
Measured at VDD/2
47
53
%
TR/TF
CLKIN Rise and Fall Times
Measured between 0.2VDD and 0.8VDD
0.5
4.0
V/ns
TCCJ
CLKIN Cycle to Cycle Jitter
Measured at VDD/2
–
250
ps
TLTJ
CLKIN Long Term Jitter
Measured at VDD/2
–
350
ps
VIH
Input High Voltage
XIN / CLKIN pin
2
VDD+0.3
V
VIL
Input Low Voltage
XIN / CLKIN pin
–
0.8
V
IIH
Input HighCurrent
XIN / CLKIN pin, VIN = VDD
–
35
uA
IIL
Input LowCurrent
XIN / CLKIN pin, 0 < VIN
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