SL28PCIE26ALC

SL28PCIe26 EProClock® PCI Express Gen 2 & Gen 3 Generator • EProClock® Programmable Technology Features • Optimized 100 MHz Operating Frequencies to Meet the Next Generation PCI-Express Gen 2 & Gen 3 • Low power push-pull type differential output buffers • Integrated voltage regulator • Four 100-MHz differential PCI-Express clocks Block Diagram DOC#: SP-AP-0774 (Rev. 0.2) 400 West Cesar Chavez, Austin, TX 78701 • Triangular Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction • 25MHz Crystal Input or Clock input • Industrial Temperature -40oC to 85oC • Integrated resistors on differential clocks • Low jitter ( 4000 bits of configurations To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers are individually enabled or disabled. The registers associated with the Serial Data Interface initialize to - Can be configured through SMBus or hard coded - Custom frequency sets - Differential skew control on true or compliment or both DOC#: SP-AP-0774 (Rev. 0.2) Page 2 of 14 SL28PCIe26 their default setting at power-up. The use of this interface is optional. Clock device register changes are normally made at system initialization, if any are required. The interface cannot be used during system operation for power management functions. Data Protocol The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, access the bytes in sequential order from lowest to highest (most significant bit first) with the ability to stop after any complete byte is transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code described in Table 1. The block write and block read protocol is outlined in Table 2 while Table 3 outlines byte write and byte read protocol. The slave receiver address is 11010010 (D2h). Table 1. Command Code Definition Bit 7 Description 0 = Block read or block write operation, 1 = Byte read or byte write operation (6:0) Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000' Table 2. Block Read and Block Write Protocol Block Write Protocol Bit 1 8:2 Description Start Block Read Protocol Bit 1 Slave address–7 bits 8:2 Description Start Slave address–7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 18:11 19 27:20 28 36:29 37 45:38 46 Command Code–8 bits Acknowledge from slave Byte Count–8 bits 18:11 19 20 Acknowledge from slave 27:21 Command Code–8 bits Acknowledge from slave Repeat start Slave address–7 bits Data byte 1–8 bits 28 Read = 1 Acknowledge from slave 29 Acknowledge from slave Data byte 2–8 bits 37:30 Acknowledge from slave .... Data Byte /Slave Acknowledges .... Data Byte N–8 bits 38 46:39 47 .... Acknowledge from slave .... Stop 55:48 Byte Count from slave–8 bits Acknowledge Data byte 1 from slave–8 bits Acknowledge Data byte 2 from slave–8 bits 56 Acknowledge .... Data bytes from slave / Acknowledge .... Data Byte N from slave–8 bits .... NOT Acknowledge .... Stop Table 3. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 8:2 9 10 18:11 19 27:20 Description Start Slave address–7 bits Write Acknowledge from slave Command Code–8 bits Byte Read Protocol Bit 1 8:2 9 10 18:11 Description Start Slave address–7 bits Write Acknowledge from slave Command Code–8 bits Acknowledge from slave 19 Acknowledge from slave Data byte–8 bits 20 Repeated start DOC#: SP-AP-0774 (Rev. 0.2) Page 3 of 14 SL28PCIe26 Table 3. Byte Read and Byte Write Protocol 28 Acknowledge from slave 29 Stop 27:21 Slave address–7 bits 28 Read 29 Acknowledge from slave 37:30 Data from slave–8 bits 38 NOT Acknowledge 39 Stop Control Registers Byte 0: Control Register 0 Bit @Pup Name Description 7 1 RESERVED RESERVED 6 0 RESERVED RESERVED 5 1 RESERVED RESERVED 4 0 RESERVED RESERVED 3 0 RESERVED RESERVED 2 0 RESERVED RESERVED 1 0 RESERVED RESERVED 0 1 PD_Restore Save configuration when PD# is asserted 0 = Config. cleared, 1 = Config. saved Byte 1: Control Register 1 Bit @Pup Name Description 7 1 RESERVED 6 0 PLL1_SS_DC 5 0 RESERVED RESERVED 4 0 RESERVED RESERVED 3 0 RESERVED RESERVED 2 1 RESERVED RESERVED 1 0 RESERVED RESERVED 0 1 RESERVED RESERVED RESERVED Select for down or center SS 0 = -0.5% Down spread, 1 = +/-0.5% Center spread Byte 2: Control Register 2 Bit @Pup Name 7 1 RESERVED RESERVED Description 6 1 RESERVED RESERVED 5 1 RESERVED RESERVED 4 1 RESERVED RESERVED 3 1 RESERVED RESERVED 2 1 RESERVED RESERVED 1 1 RESERVED RESERVED 0 1 RESERVED RESERVED Byte 3: Control Register 3 Bit @Pup DOC#: SP-AP-0774 (Rev. 0.2) Name Description Page 4 of 14 SL28PCIe26 Byte 3: Control Register 3 7 1 RESERVED RESERVED 6 1 RESERVED RESERVED 5 1 RESERVED RESERVED 4 1 RESERVED RESERVED 3 1 RESERVED RESERVED 2 1 RESERVED RESERVED 1 1 RESERVED RESERVED 0 1 RESERVED RESERVED Byte 4: Control Register 4 Bit @Pup Name 7 1 RESERVED Description 6 1 SRC0_OE Output enable for SRC0 0 = Output Disabled, 1 = Output Enabled 5 1 SRC1_OE Output enable for SRC1 0 = Output Disabled, 1 = Output Enabled 4 0 RESERVED 3 1 SRC3_OE Output enable for SRC3 0 = Output Disabled, 1 = Output Enabled 2 1 SRC2_OE Output enable for SRC2 0 = Output Disabled, 1 = Output Enabled 1 0 PLL1_SS_EN Enable PLL1s spread modulation, 0 = Spread Disabled, 1 = Spread Enabled 0 1 RESERVED RESERVED RESERVED RESERVED Byte 5: Control Register 5 Bit @Pup Name 7 0 RESERVED RESERVED Description 6 0 RESERVED RESERVED 5 0 RESERVED RESERVED 4 0 RESERVED RESERVED 3 0 RESERVED RESERVED 2 0 RESERVED RESERVED 1 0 RESERVED RESERVED 0 0 RESERVED RESERVED Byte 6: Control Register 6 Bit @Pup Name 7 0 RESERVED RESERVED 6 0 RESERVED RESERVED 5 0 RESERVED RESERVED 4 0 RESERVED RESERVED 3 0 RESERVED RESERVED 2 0 RESERVED RESERVED 1 0 RESERVED RESERVED 0 0 RESERVED RESERVED DOC#: SP-AP-0774 (Rev. 0.2) Description Page 5 of 14 SL28PCIe26 Byte 7: Vendor ID Bit @Pup Name 7 0 Rev Code Bit 3 Revision Code Bit 3 Description 6 1 Rev Code Bit 2 Revision Code Bit 2 5 0 Rev Code Bit 1 Revision Code Bit 1 4 0 Rev Code Bit 0 Revision Code Bit 0 3 1 Vendor ID bit 3 Vendor ID Bit 3 2 0 Vendor ID bit 2 Vendor ID Bit 2 1 0 Vendor ID bit 1 Vendor ID Bit 1 0 0 Vendor ID bit 0 Vendor ID Bit 0 Byte 8: Control Register 8 Bit @Pup Name 7 1 Device_ID3 RESERVED Description 6 0 Device_ID2 RESERVED 5 0 Device_ID1 RESERVED 4 0 Device_ID0 RESERVED 3 0 RESERVED RESERVED 2 0 RESERVED RESERVED 1 0 RESERVED RESERVED 0 0 RESERVED RESERVED Byte 9: Control Register 9 Bit @Pup Name 7 0 RESERVED RESERVED Description 6 0 RESERVED RESERVED 5 1 RESERVED RESERVED 4 0 TEST _MODE_SEL Test mode select either REF/N or tri-state 0 = All outputs tri-state, 1 = All output REF/N 3 0 TEST_MODE_ENTRY Allows entry into test mode 0 = Normal Operation, 1 = Enter test mode(s) 2 1 I2C_VOUT 1 0 I2C_VOUT 0 1 I2C_VOUT Amplitude configurations differential clocks I2C_VOUT[2:0] 000 = 0.30V 001 = 0.40V 010 = 0.50V 011 = 0.60V 100 = 0.70V 101 = 0.80V (default) 110 = 0.90V 111 = 1.00V Byte 10: Control Register 10 Bit @Pup Name 7 0 RESERVED RESERVED 6 0 RESERVED RESERVED 5 0 RESERVED RESERVED 4 0 RESERVED RESERVED 3 0 RESERVED RESERVED DOC#: SP-AP-0774 (Rev. 0.2) Description Page 6 of 14 SL28PCIe26 Byte 10: Control Register 10 Bit @Pup Name Description 2 0 RESERVED RESERVED 1 1 RESERVED RESERVED 0 1 RESERVED RESERVED Byte 11: Control Register 11 Bit @Pup Name Description 7 0 RESERVED RESERVED 6 0 RESERVED RESERVED 5 0 RESERVED RESERVED 4 0 RESERVED RESERVED 3 0 RESERVED RESERVED 2 1 RESERVED RESERVED 1 1 RESERVED RESERVED 0 1 RESERVED RESERVED Byte 12: Byte Count Bit @Pup Name 7 0 BC7 6 0 BC6 5 0 BC5 4 0 BC4 3 1 BC3 2 1 BC2 1 1 BC1 0 1 BC0 Description Byte count register for block read operation. The default value for Byte count is 15. In order to read beyond Byte 15, the user should change the byte count limit.to or beyond the byte that is desired to be read. Byte 13: Control Register 13 Bit @Pup Name 7 1 RESERVED RESERVED Description 6 1 RESERVED RESERVED 5 1 RESERVED RESERVED 4 1 RESERVED RESERVED 3 1 RESERVED RESERVED 2 1 RESERVED RESERVED 1 0 RESERVED RESERVED 0 0 RESERVED RESERVED Byte 14: Control Register 14 Bit @Pup Name 7 1 RESERVED RESERVED 6 0 RESERVED RESERVED 5 1 RESERVED RESERVED DOC#: SP-AP-0774 (Rev. 0.2) Description Page 7 of 14 SL28PCIe26 Bit @Pup Name 4 0 OTP_4 Description 3 0 OTP_3 2 1 OTP_2 1 0 OTP_1 0 1 OTP_0 OTP_ID Idenification for programmed device PD# (Power down) Assertion . Table 4. Output Driver Status All Differential Clocks PD# = 0 (Power down) Clock Clock# Low Low PD# (Power down) Clarification The CKPWRGD/PD# pin is a dual-function pin. During initial power up, the pin functions as CKPWRGD. Once CKPWRGD has been sampled HIGH by the clock chip, the pin assumes PD# functionality. The PD# pin is an asynchronous active LOW input used to shut off all clocks cleanly before shutting off power to the device. This signal is synchronized internally to the device before powering down the clock synthesizer. PD# is also an asynchronous input for powering up the system. When PD# is asserted LOW, clocks are driven to a LOW value and held before turning off the VCOs and the crystal oscillator. When PD is sampled HIGH by two consecutive rising edges of SRCC, differential clocks must held LOW. When PD mode is desired as the initial power on state, PD must be asserted HIGH in less than 10 s after asserting CKPWRGD. PD# Deassertion The power up latency is less than 1.8 ms. This is the time from the deassertion of the PD# pin or the ramping of the power supply until the time that stable clocks are generated from the clock chip. All differential outputs stopped in a three-state condition, resulting from power down are driven high in less than 300 s of PD# deassertion to a voltage greater than 200 mV. After the clock chip’s internal PLL is powered up and locked, all outputs are enabled within a few clock cycles of each clock. Figure 2 is an example showing the relationship of clocks coming up. Figure 1. Power down Assertion Timing Waveform Figure 2. Power down Deassertion Timing Waveform . DOC#: SP-AP-0774 (Rev. 0.2) Page 8 of 14 SL28PCIe26 Absolute Maximum Conditions Parameter Description Condition Min. Max. Unit – 4.6 V –0.5 4.6 VDC –65 150 °C Functional 0 85 °C Temperature, Operating Ambient, Industrial Functional –40 85 °C VDD_3.3V Main Supply Voltage Functional VIN Input Voltage Relative to VSS TS Temperature, Storage Non-functional TA Temperature, Operating Ambient, Commercial TA TJ Temperature, Junction Functional – 150 °C ØJC Dissipation, Junction to Case JEDEC (JESD 51) – 20 °C/ W ØJA Dissipation, Junction to Ambient JEDEC (JESD 51) – 60 °C/ W ESDHBM ESD Protection (Human Body Model) JEDEC (JESD 22 - A114) 2000 – V UL-94 Flammability Rating UL (Class) Max. Unit 3.135 3.465 V 2.0 VDD + 0.3 V VSS – 0.3 0.8 V 2.2 – V V–0 DC Electrical Specifications Parameter Description Condition VDD core 3.3V Operating Voltage VIH 3.3V Input High Voltage (SE) VIL 3.3V Input Low Voltage (SE) VIHI2C Input High Voltage VILI2C Input Low Voltage SDATA, SCLK – 1.0 V IIH Input High Leakage Current Except internal pull-down resistors, 0 < VIN < VDD – 5 A IIL Input Low Leakage Current Except internal pull-up resistors, 0 < VIN < VDD –5 – A IOZ High-impedance Output Current –10 10 A CIN Input Pin Capacitance 1.5 COUT Output Pin Capacitance LIN Pin Inductance – 7 nH IDD_PD Power Down Current – 1 mA IDD_3.3V Dynamic Supply Current – 50 mA DOC#: SP-AP-0774 (Rev. 0.2) 3.3 ± 5% Min. SDATA, SCLK All outputs enabled. Differential clocks with 7” traces 2pF load. Page 9 of 14 5 pF 6 pF SL28PCIe26 AC Electrical Specifications Parameter Description Condition Min. Max. Unit – 250 ppm Crystal LACC Long-term Accuracy Measured at VDD/2 differential Clock Input TDC CLKIN Duty Cycle Measured at VDD/2 47 53 % TR/TF CLKIN Rise and Fall Times Measured between 0.2VDD and 0.8VDD 0.5 4.0 V/ns TCCJ CLKIN Cycle to Cycle Jitter Measured at VDD/2 – 250 ps TLTJ CLKIN Long Term Jitter Measured at VDD/2 – 350 ps VIH Input High Voltage XIN / CLKIN pin 2 VDD+0.3 V VIL Input Low Voltage XIN / CLKIN pin – 0.8 V IIH Input HighCurrent XIN / CLKIN pin, VIN = VDD – 35 uA IIL Input LowCurrent XIN / CLKIN pin, 0 < VIN