SL38160AZC-17AH

SL38160-17AH SL38160-23AH Programmable Audio/Video CG with VCXO Key Features • • • • • • • • Audio + video clock generation Programmable on chip analog VCXO with typical pull range of +/-150ppm VCXO control voltage, 0V to 3V Uses 27MHz pullable crystal 3.3V +/-10% power supply range Available in both Commercial (0 to 70C)and Industrial (-40 to 85C) temperature grades Low power dissipation and low jitter Integrated internal voltage regulator Applications • • • • • Description The SL38160AZC-17AH and SL38160AZC-23AH are programmable low power VCXO Clock Generators designed to enable clock recovery and to synthesize the audio and video clocks required for advanced multimedia applications. The product is designed using SpectraLinear proprietary programmable EProClock™ technology to generate the output clocks. The product is offered in a space saving 16-pin TSSOP package. The two parts are identical except for IIC address, where the SL38160AZC-17AH uses D2(hex) while the SL38160AZC-23AH uses DA(hex). HDTV & SDTV Wireless HDMI Set Top Box Media Center DVR Block Diagram Rev AB January 16, 2011 Document Number: SP-AP-0826 2400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1+(512) 416-9669 Page 1 of 16 www.silabs.com SL38160-17AH SL38160-23AH Pin Configuration 16-Pin TSSOP Package Pin Description Pin Number Pin Name Pin Type 1 XIN Input 2 27M_REF1 Output 3 VIN Input 4, 5, 13, 15 VDD Power 3.3V +/-10% Positive Power Supply. 6, 10,12 VSS Power Power supply ground for VDD. 7 SDATA I/O 8 SCLK Input 9 VCLK Output Video clock output. (Default on) (Can be changed to off/high impedance state through I2C) 11 ACLK Output Audio clock output .(Default on) (Can be changed to off/synchronous stop, pulled low to VSS, through I2C) 14 27M_REF2 Output 27 MHz reference clock output 2. (Default on) (Can be changed to off/synchronous stop, pulled low to VSS, through I2C) 16 XOUT Output Crystal oscillator output. Use fundamental parallel mode 27MHz crystal. Rev AB January 16, 2011 Pin Description Crystal oscillator input. Use fundamental parallel mode 27MHz crystal. 27 MHz reference clock output 1. (Default on) (Can be changed to off/synchronous stop, pulled low to VSS, through I2C) VCXO frequency control voltage I2C Serial Data I2C Clock Document Number: SP-AP-0198 Page 2 of 16 SL38160-17AH SL38160-23AH Absolute Maximum Ratings Description Condition Min Max Unit Supply voltage, VDD -0.5 4.2 V All Inputs and Outputs -0.5 VDD+0.5 V 0 70 °C Ambient Operating Temperature In operation Ambient Operating Temperature Industrial grade, in operation -40 85 °C Storage Temperature No power is applied -65 150 °C Junction Temperature In operation, power is applied - 125 °C - 260 °C Soldering Temperature ESD Rating (Human Body Model) JEDEC22-A114D -4,000 4,000 V ESD Rating (Charge Device Model) JEDEC22-C101C -1,500 1,500 V ESD Rating (Machine Model) JEDEC22-A115D -250 250 V Moisture Sensitivity Level JEDEC (J-STD-020) 1 Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or other conditions beyond those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics Unless otherwise stated VDD= 3.3V+/-10%, VIN=1.65V, Output Load=15pF and Ambient Temperature range 0 to +70°C for Commercial or -40 to +85°C for Industrial temperature option. Description Symbol Condition 3.3V +/-10% Min Typ Max Unit 2.97 3.3 3.63 V Operating Voltage VDD Input High Voltage VIH 0.7xVDD - - V Input Low Voltage VIL - - 0.3xVDD V Output High Voltage VOH IOH=-6mA VDD-0.5 - - V Output Low Voltage VOL IOL=6mA - - 0.5 V Operating Supply Current IDD Output load = 0pF - 20 25 mA VIN Input Impedance VINR 1 - - MΩ - 250 - KΩ Input Pull-Down/Up Resistor Rev AB January 16, 2011 Document Number: SP-AP-0198 Page 3 of 16 SL38160-17AH SL38160-23AH AC Electrical Characteristics Unless otherwise stated VDD= 3.3V+/-10%, VIN=1.65V, Output Load=15pF for f200MHz and Ambient Temperature range 0 to +70°C for Commercial or -40 to +85°C for Industrial temperature option. Parameter Symbol Input Frequency Range FIN Condition Min Typ Max Unit Crystal input - 27 - MHz Output Rise Time Tr VCLK and ACLK, all frequencies - - 1.5 ns Output Rise Time Tr 27M_REF1,27M_ REF2 clocks - - 2.0 ns Output Fall Time Tf VCLK and ACLK, all frequencies - - 1.5 ns Output Fall Time Tf 27M_REF1,27M_ REF2 clocks - - 2.0 ns Output Duty Cycle - All outputs ,f≤100MHz 45 50 55 % Output Duty Cycle - All outputs, f>100MHz 40 50 60 % Output Frequency Synthesis Error FOUT All Frequencies except 193.16MHz, which has a +15ppm error - - 0 ppm Cycle to Cycle Jitter - 27M_REF1, 27M_REF2 outputs - 160 250 ps Cycle to Cycle Jitter - VCLK output - 175 350 ps Cycle to Cycle Jitter - ACLK output - 150 250 ps 1 - 27M_REF1, 27M_REF2 outputs - 85 120 ps-rms 1 - VCLK output - 250 700 ps-rms 1 - ACLK output - 550 950 ps-rms - Time before valid clock output after programming frequency via IIC - - 0.5 ms Time from VDD minimum to valid frequency output - - 5.5 ms Monotonic VCXO Crystal Pull Range - +/-150 - ppm Long Term Jitter Long Term Jitter Long Term Jitter Frequency Settling Time Power-up Time VCXO Pull Range TPUP ΔFVCXO 2 Recommended Crystal Specifications (for VCXO applications)2 Symbol Description Comments Typ Max Unit - 27 - MHz -20 - 20 ppm -20 - 20 ppm - 14 - pF FNOM Nominal frequency FDELTA25 Frequency tolerance at 25°C FDELTAT Temperature tolerance CLNOM Nominal load capacitance R1 Equivalent series resistance Fundamental mode (CL=series) - 20 50 Ω DL Drive level Nominal VDD @25°C over +/-150ppm Pull range - - 500 uW C0 Shunt capacitance - 3.0 7.0 pF 1 2 Fundamental mode Min 0 to 70°C (reference to 25°C ) Measured with 1000 samples at 10us delay on oscilloscope KDS 1C727000CC1K crystal Rev AB January 16, 2011 Document Number: SP-AP-0198 Page 4 of 16 SL38160-17AH SL38160-23AH C1 Motional capacitance C0/C1 Ratio of shunt to motional capacitance F3SEPHI F3SEPLO - 11.8 - fF 250 Third overtone separation, Mechanical third high side (High side of 3xFNOM) Third overtone separation, Mechanical third low side (Low side of 3xFNOM) 240 - - ppm - - -240 ppm Serial Data Interface To enhance the flexibility and function of the device, an I2C compatible interface is provided. Through the Serial Data Interface, various device functions, such as ACLK and VCLK frequency setting and individual clock output buffers can be individually enabled or disabled. The registers associated with the Serial Data Interface initialize to their default setting at power-up. Clock device register changes can be made after the device power up initialization process has completed. Data Protocol The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, Access the bytes in sequential order from lowest to highest (most significant bit first) with the ability to stop after any complete byte is transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code descried in the command code definition section. The block write and block read protocol is outlined in the block read and block write protocol section, while The byte read and byte write protocol section outlines byte read and byte write information. The slave receiver address is 11010010 (D2h) for the SL38160AZC-17AH. The slave receiver address is 11011010 (DAh) for the SL38160AZC-23AH. Rev AB January 16, 2011 Document Number: SP-AP-0198 Page 5 of 16 SL38160-17AH SL38160-23AH Command Code Definition Bit 7 (6:0) Description 0 = Block read or block write operation, 1 = Byte read or byte write operation Byte offset for byte read or byte write operation. For block read or block operations, these bits should be ‘0000000’ Block Read and Block Write Protocol Block Write Protocol Block Read Protocol Bit Description Bit Description 1 Start 1 Start 8:2 Slave address-7bits 8:2 Slave address-7bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 18:11 Command Code-8bits 18:11 Command Code-8bits 19 Acknowledge from slave 19 Acknowledge from slave 27:20 Byte Count-8bits 20 Repeat start 28 Acknowledge from slave 27:21 Slave address-7bits 36:29 Data byte 1-8bits 28 Read = 1 37 Acknowledge from slave 29 Acknowledge from slave 45:38 Data byte 2-8bits 37:30 Byte Count from slave 8bits 46 Acknowledge from slave 38 Acknowledge … Data Byte/Slave Acknowledges 46:39 Data byte 1 from slave-8bits … Data Byte N-8bits 47 Acknowledge … Acknowledge from slave 55:48 Data byte 2 from slave-8bits … Stop 56 Acknowledge … Data bytes from slave/Acknowledge … Data Byte N from slave-8bits … NOT Acknowledge … Stop Rev AB January 16, 2011 Document Number: SP-AP-0198 Page 6 of 16 SL38160-17AH SL38160-23AH Byte Read and Byte Write Protocol Byte Write Protocol Byte Read Protocol Bit Description Bit Description 1 Start 1 Start 8:2 Slave address-7bits 8:2 Slave address-7bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 18:11 Command Code-8bits 18:11 Command Code-8bits 19 Acknowledge from slave 19 Acknowledge from slave 27:20 Data byte-8bits 20 Repeat start 28 Acknowledge from slave 27:21 Slave address-7bits 29 Stop 28 Read 29 Acknowledge from slave 37:30 Byte Count from slave 8bits 38 NOT Acknowledge 39 Stop Note: When writing to any register bytes between 32d to 63d (20h to 40h), an additional byte outside this range must be written to immediately afterward for proper loading to the register bytes within this range. I2C-bus Timing Specification STANDARD-MODE PARAMETER FAST-MODE SYMBOL UNIT MIN. MAX. MIN. MAX. fSCL 0 100 0 400 KHz START hold time tHD;STA 4.0 - 0.6 - us SCLK LOW period tLOW 4.7 - 1.3 - us SCLK HIGH period tHIGH 4.0 - 0.6 - us START Set-up time tSU;DAT 4.7 - 0.6 - us SCL Clock Frequency Rev AB January 16, 2011 Document Number: SP-AP-0198 Page 7 of 16 SL38160-17AH SL38160-23AH STANDARD-MODE PARAMETER FAST-MODE SYMBOL UNIT MIN. MAX. MIN. MAX. SDA set-up time tSU;DAT 250 - 100 - ns SDA/SCLK rise time tR - 1000 - 300 ns SDA/SCLK fall time tF - 300 - 300 ns STOP set-up time tSU;STO 4.0 - 0.6 - ns Bus free time tBUF 4.7 - 1.3 - us SDATA tF tLOW tF tSU;DAT tR tR tHD;STA tBUF SCLK tHD;STA S Rev AB January 16, 2011 tHD;DAT tHIGH tSU;STO tSU;STA Sr Document Number: SP-AP-0198 P Page 8 of 16 S SL38160-17AH SL38160-23AH Table 1. Audio Clock Frequency Settings (pin 11) Audio Clk (MHz) Byte 40 Byte 41 Byte 42 Byte 43 Byte129 8.1920 04 02 1F 18 81 11.2896 0C 45 DE 78 81 12.2880 04 01 F6 38 81 04 01 F5 18 81 16.9344 09 33 E9 D8 81 18.4320 04 01 F5 78 81 36.8640 04 01 F4 B8 81 16.3840 08 03 85 D8 81 22.5792 0C 45 DD 38 81 49.1520 08 03 84 98 81 33.8688 06 21 F5 38 81 73.7280 04 01 F4 58 81 24.5760 Register Byte# DEC and Bit [7:0] HEX Setting 3 Table 2. Digital Television Video Clock Frequency Settings (pin 9) Video Clk (MHz) 13.50000 27.00000 54.00000 3 74.17582 74.25000 148.35170 148.50000 3 Register Byte# (DEC) and Bit [7:0] HEX, Setting Byte17 07 07 07 05 07 05 07 Byte18 80 80 80 80 00 80 80 Byte19 AB AB AB AB AB AB AB Byte22 C6 C6 C6 DE C6 DE C6 Byte48 04 04 04 1F 05 1F 05 Byte49 00 00 00 6D 80 6D 80 Byte 50 7E 5E 4E 86 86 82 82 Byte51 C7 C7 C7 C7 C7 C7 C7 Default output frequency on power up Rev AB January 16, 2011 Document Number: SP-AP-0198 Page 9 of 16 Byte128 34 34 34 36 34 36 34 SL38160-17AH SL38160-23AH Table 3. VGA Video Clock Settings (pin 9)4 Screen Resolution Register Byte# (DEC) and Bit [7:0] HEX, Setting Byte Byte Byte Byte Byte Byte Byte 48 49 50 51 68 69 114 3E 08 C0 D2 C7 03 83 640 x 350 Refresh Rate (Hz) 85 Video Clock (MHz) 31.500 Byte 17 07 Byte 18 00 Byte 19 AB Byte 22 C6 640 x 400 85 31.500 07 00 AB C6 08 C0 D2 C7 03 83 720 x 400 85 85.04 35.500 35.000 07 06 00 80 AB AB C6 C6 11 08 C1 C0 90 D0 C7 C7 03 03 83 83 60 72 25.175 31.500 09 07 00 00 6B AB 86 C6 FB 08 CF C0 22 D2 C7 C7 03 03 83 83 75 85 31.500 36.000 07 07 00 80 AB AB C6 66 08 03 C0 00 D2 50 C7 C7 03 03 83 83 56 38.100 05 80 AB C6 1F C2 52 C7 03 83 60 72 40.000 50.000 07 05 00 80 AB AB C6 C6 0A 19 00 02 D0 4A C7 C7 03 03 83 83 75 85 49.500 56.250 07 07 00 80 AB AB C6 C6 05 06 80 40 8A 8A C7 C7 03 03 83 83 640 x 480 800 x 600 1024 x 768 1152 x 864 1280x768 34 34 3E 3E 34 34 3E 3E 34 34 3E 34 3E 3E 34 34 3E 3E 34 34 3E 34 3E 3E 34 34 3E 3E 34 34 3E 3E 34 34 44.900 05 00 AB C6 70 46 D2 C7 03 83 60 70 65.000 75.000 05 07 80 00 AB AB C6 C6 20 0C 82 80 4A CA C7 C7 03 03 83 83 75 85 78.750 94.500 07 0B 00 80 AB AB C6 C6 08 03 C0 80 C6 46 C7 C7 03 03 83 83 75 60 108.000 68.250 0B 06 80 80 AB 6B C6 C6 03 16 00 C1 44 8A C7 C7 03 03 83 83 3E 34 60 75 79.500 06 80 6B C6 1A 82 46 C7 05 06 00 00 AB 6B C6 C6 7F 3A CB C4 44 84 C7 C7 83 83 3E 3E 34 102.200 117.500 03 03 85.500 108.000 06 0B 80 80 AB AB C6 C6 09 03 80 00 C6 44 C7 C7 03 03 83 83 3E 3E 03 83 3E 34 34 34 34 60 1280 x 960 3E 3E 43 85 60 1360 x 768 Byte 128 34 34 34 85 60 148.500 108.000 07 0B 00 80 AB AB C6 C6 05 03 80 00 82 44 C7 C7 03 03 83 83 3E 3E 1280x1024 75 135.000 07 80 AB C6 03 C0 44 C7 03 83 157.500 101.000 06 06 80 80 AB 6B C6 C6 08 19 C0 42 C2 44 C7 C7 00 00 6B 6B C6 C6 79 0D C6 00 C6 C4 C7 C7 3E 3E 75 05 07 83 83 83 34 121.750 156.000 03 03 03 34 34 1400x1050 85 60 60 3E 3E 03 83 3E 34 34 85 179.500 06 00 6B C6 59 C6 C2 C7 03 83 60 65 162.000 175.500 07 07 80 80 AB AB C6 C6 03 03 00 40 42 42 C7 C7 03 03 83 83 3E 3E 34 34 70 75 189.000 202.500 07 07 80 80 AB AB C6 C6 03 03 80 C0 42 42 C7 C7 03 03 83 83 3E 3E 34 34 3E 34 85 229.500 07 80 AB C6 04 40 42 C7 03 83 3E 34 1600x1200 4 Pin 9 is the video output clock used for both the Digital Television and VGA Video frequency settings Rev AB January 16, 2011 Document Number: SP-AP-0198 Page 10 of 16 SL38160-17AH SL38160-23AH Screen Resolution Refresh Rate (Hz) 50 60 Register Byte# (DEC) and Bit [7:0] HEX, Setting Byte Byte Byte Byte Byte Byte Byte 48 49 50 51 68 69 114 03 83 3E 04 00 4A C7 03 83 3E 26 82 44 C7 Video Clock (MHz) 72.000 Byte 17 07 Byte 18 80 Byte 19 AB Byte 22 C6 154.000 193.160 06 05 00 80 6B AB C6 DE 32 F8 C2 C7 193.250 05 00 AB C6 C1 4D 82 C7 85 245.250 281.250 06 06 80 80 6B 6B C6 C6 1B 1F 41 43 82 00 C7 C7 1792x 1344 60 75 204.750 261.000 31 07 00 00 AB AB C6 C6 16 07 C1 40 82 C0 1856x1392 60 75 218.250 288.000 31 07 00 00 AB AB C6 C6 18 08 41 00 82 C0 1920x1080i 1920x1200 60 60 75 5 60 75 1920x 1440 5 03 03 03 83 83 83 3E 0F C3 C7 C7 03 0F 83 C3 BE 3E C7 C7 03 0F 83 C3 3E BE 83 C3 3E BE 234.000 31 80 AB C6 0D 00 C2 C7 297.000 07 00 AB C6 05 80 80 C7 03 0F 15ppm synthesis error Rev AB January 16, 2011 Document Number: SP-AP-0198 Page 11 of 16 3E 3E BE Byte 128 34 34 36 34 34 34 34 34 34 34 34 34 SL38160-17AH SL38160-23AH Table 4. Output Control Output Byte to change Enable REF-1 64d 04h 6 08h VCLK 117d 00h 6 04h ACLK 86d 04h 6 08h REF-2 96d 04h 6 08h Disable Table 5. Power Down Control Byte to change Active Mode 29d 16h 6 Powerdown Mode 36h Table 6. Additional Bytes to Program Byte to change 126d Value 130d 53h 26h Note: these bytes should be programmed once after device power up. 6 Default condition Rev AB January 16, 2011 Document Number: SP-AP-0198 Page 12 of 16 SL38160-17AH SL38160-23AH Rev AB January 16, 2011 Document Number: SP-AP-0198 Page 13 of 16 SL38160-17AH SL38160-23AH Typical Application Circuit KDS1C727000CC1K 3.3V 1 XIN 2 27M_REF1 3 VIN 4 XOUT GND 16 0.01uF 22 Ohm VDD 15 27M_REF2 14 VDD VDD 13 5 VDD VSS 12 6 VSS ACLK 11 7 SDATA VSS 10 8 SCLK VCLK 9 22 Ohm 3.3V 3.3V 0.01uF GND 0.01uF 0.01uF 3.3V GND 22 Ohm GND 22 Ohm Legend Pad Via 3.3V 10uF GND General Guidelines: 1. Place crystal on same side of the board. 2. Place 0.01µF capacitors as close as possible to the power pin. 3. Install one bulk capacitor (10µF). Note that this filtered power should connect to the 0.01µF capacitor pads first. This is known as pin-cap-via. 4. The 22 Ohm series resistors placed on clock outputs are board dependent. This is a nominal value for 50 Ohm impedance boards. Never share ground vias. 5. It is preferable to have a ground flood directly underneath the part. 6. If PCB process takes advantage of via-in-pad technology, then it is recommended that the ground side of all bypass capacitors have the GND via placed inside the pad to lower inductance to ground. Rev AB January 16, 2011 Document Number: SP-AP-0198 Page 14 of 16 SL38160-17AH SL38160-23AH Package Outline and Package Dimensions 16-Pin TSSOP Package (4.4mm) Rev AB January 16, 2011 Document Number: SP-AP-0198 Page 15 of 16 SL38160-17AH SL38160-23AH Thermal Characteristics Parameter Symbol Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Condition Min Typ Max Unit θ JA Still air - 80 - °C/W θ JA 1m/s air flow - 70 - °C/W θ JA 3m/s air flow - 68 - °C/W θ JC Independent of air flow - 36 - °C/W Ordering Information Ordering Number Marking Shipping Package Package Temperature SL38160AZC-17AH SL38160AZC-17AH Tube 16-pin TSSOP 0 to 70°C SL38160AZC-17AHT SL38160AZC-17AH Tape and Reel 16-pin TSSOP 0 to 70°C SL38160AZC-23AH SL38160AZC-23AH Tube 16-pin TSSOP 0 to 70°C SL38160AZC-23AHT SL38160AZC-23AH Tape and Reel 16-pin TSSOP 0 to 70°C SL38160AZI-17AH SL38160AZI-17AH Tube 16-pin TSSOP -40 to 85°C SL38160AZI-17AHT SL38160AZI-17AH Tape and Reel 16-pin TSSOP -40 to 85°C SL38160AZI-23AH SL38160AZI-23AH Tube 16-pin TSSOP -40 to 85°C SL38160AZI-23AHT SL38160AZI-23AH Tape and Reel 16-pin TSSOP -40 to 85°C Notes: 1. All SLI products are RoHS compliant. Document History Page REV. Issue Date Originator Description of change A.1.0 7/8/10 D. Christenberry Create initial datasheet as advance information. B.1.0 9/2/10 D. Christenberry Final datasheet B. 1.1 10/5/10 D. Christenberry New frequency support added per customer, also updated package drawing B.1.2 10/14/10 D. Christenberry Updated cy-cy jitter specifications AA 10/28/10 D. Christenberry Release version. Added additional bytes, 5pF load condition for f>200Mz AB 1/16/11 D. Christenberry Added Industrial temperature operation The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages Rev AB January 16, 2011 Document Number: SP-AP-0198 Page 16 of 16