SMARTPSE24-KIT

Si3482 Smart PSE-24 UG Si3482 S M A R T P S E - 2 4 K IT U SER ’ S G UIDE 1. Introduction The Si3482 power management controller works with Si3452 PSE controllers and enables the use of a smaller, lower-cost, and more efficiently-utilized power supplies in managed or unmanaged Power over Ethernet (PoE) Power Sourcing Equipment (PSE) with up to 48 ports and up to three parallel power supplies. The Smart PSE-24 kit demonstrates the use of the Si3482 in a 24-port system. Figure 1 shows the assembled kit.   Figure 1. Smart PSE-24 Kit Rev. 0.2 10/10 Copyright © 2010 by Silicon Laboratories Si3482 Smart PSE-24 UG Si3 482 S mart P S E - 24 U G 2. Smart PSE-24 Kit Contents Table 1 lists the contents of the PSE-24 kit. Table 1. PSE-24 Kit Contents 1 The SmartPSE24-RD, which includes the Si3482, six Si3452 PoE controllers, a –50 V to +3.3 V dc-to-dc converter based on a Si3500, isolation for UART communications, and an alternative SPI interface (the SPI interface is not isolated). 2 Two Si3402ISO-EVB powered device evaluation boards. The boards are configured to provide a Class 3 signature. 3 One Si3402ISO-C4- EVB. This board is configured to supply a Class 4 signature. The Class 4 boards are marked Class 4 and can also be identified by the diodes on the back of the board. 4 Three switchable loads. The switchable loads draw approximately 6.5, 13, or 19.5 W from the PSE. 5 One 24-port connector board to bring the Si3452 power to Ethernet jacks. The connector board does not have Ethernet data functionality. 6 PoE USB adapter. This adapter supports USB to UART, SPI or I2C. It is generally used for UART with the Smart PSE 24 Kit. 7 Three Ethernet cables, one USB cable, and two 24-wire ribbon cables. 3. Using the Smart PSE-24 Kit 3.1. Hardware Configuration The boards are connected as shown in Figure 1. A nominal 50 V power supply is connected to J815 (note the polarity). For high-power support according to the IEEE standard, the supply voltage should be between 51 and 57 V. For normal power levels, the power supply can be 45 to 57 V. The total power supply wattage can be as high as 720 W for full power on all ports. Effective evaluation can be done with a power supply of 40 W or more. Once configured, the Si3482 manages the available power. The large diode, D801, will be forward-biased in case of incorrect input polarity. Note: It is recommended that the power supply be connected to the board and then turned on so as to reduce large inrush current charging the (3) 33 µF filter capacitors on the board. Table 2 lists the jumper settings. Table 2. Jumper Settings Jumper Logic Level JP7 1 Si3482 is not reset when the PoE USB adapter is removed. JP8 1 JP8 selects UART or SPI interface. The PoE USB adapter board is generally set for UART. JP4, JP5, JP6 1,1,1 JP4, JP5, and JP6 set the UART baud rate. The PoE USB adapter is configured for 115.2 kHz 0 JP 9 is for testing the power supply removal function for the third power supply. As will be discussed later, the power manager GUI can control the first and second power supply lines. The status of the third power supply line is reported but cannot be controlled. Generally, JP9 is set to 0 (power supply 3 not inserted). JP9 2 Reason Rev. 0.2 Si3482 Smart PSE-24 UG 3.2. Installing the PoE USB Adapter Note: Before the PoE USB adapter is plugged in, the device driver should be installed. To install the PoE USB adapter drivers, run PoEUSBSetup.exe from the supplied disk, and follow the instructions including accepting the end user license agreement. The PoE USB adapter supplied with the Smart PSE-24 Kit has been tested to be compatible with Windows XP®, Windows Vista®, and Windows 7® operating systems. After successful installation, plug in the USB cable; the PoE USB device should be recognized. For Windows XP, select “No not at this time” when Windows prompts to search for software, and select “Install the software automatically” on the next screen. After successful installation, a PC reboot may be required. 4. Demonstration Use of the Power Manager GUI The Silicon Labs power manager GUI is used to configure and observe the Smart PSE 24 via the supplied PoE USB adapter. See the Si3452 Power Management GUI user’s guide for detailed installation instructions. Note that once the Si3482 has been configured, it can run in hardware only mode without the GUI or PoE USB-to-UART adapter. The demonstration assumes the Power Manager GUI has been used to configure the Si3482 as follows:      40 W of power available on Power Supply 2. Set Power Supply 1 to zero for demonstration in the standalone mode. This is because, in the standalone mode, the control line for Power Supply 1 status is low (disabled) when the USB cable is unplugged. Port 1 High Power (PoE+, 30 W) all other ports standard PoE (15.4 W) Port 1 critical priority; all other ports low priority Consumption-based power management Retry after reconnect for overloads   Figure 2. Configuration Screen  Power Supply 2 inserted. Power Supply 1 can be inserted or not as its power capacity is set to zero. Power Supply 3 should also display as not inserted if JP 9 is set low. Power Supply 3 cannot be controlled by the GUI when using the Smart PSE 24 Kit because jumper JP9 sets the status. Rev. 0.2 3 Si3 482 S mart P S E - 24 U G   Figure 3. Initial Status Screen The Si3482 Smart Power 24 kit ships with three powered devices based on the Si3402 with loads for up to approximately 19.5 W of input power. The loads are arranged as one to three 5  resistors, which draw 5 W each at the PD output voltage of 5 V. Due to the PD input diode bridge and the dc-to-dc conversion efficiency, each resistor causes approximately 6.5 W of power to be drawn from the PSE. This means that the PD will draw approximately 6.5, 13, or 19.5 W from the PSE, depending on the number of load resistors connected. Step 1: Connect a Class 3 PD with a 6.5 W load (switches off) into Port 1 and a Class 4 PD with a 6.5 W load into Port 2. The status window is shown in Figure 4.   Figure 4. Status Screen with Class 3 PD on Port 1 and Class 4 PD on Port 2 4 Rev. 0.2 Si3482 Smart PSE-24 UG Since sufficient power is available, both ports are granted power. Because Port 2 was not enabled as PoE+, the Class 4 PD is only granted 15.4 W. Step 2: Disconnect the PDs from Step 1, and connect the Class 4 PD to Port 1 and Class 3 PDs to each of Ports 2 and 3. Initially, use a 6.5 W load on each PD. All three ports are granted power. Port 1 is now granted 30 W since Port 1 is enabled for high power (PoE+). Since only one resistor is connected, approximately 6.5 W is drawn on each port.   Figure 5. Status Screen with Class 4 PD on Port 1 and Class 3 PDs on Ports 2 and 3 Step 3: Increase the Load on the ports to create a port overload by switching in more load resistors. For Port 2 or Port 3 (with Class 3 PDs), the port overload condition occurs with the three resistors, which corresponds to about 19.5 W of input power. The following screen shot shows the result of an overload (indicated by the status “blocked”) on Port 3. Rev. 0.2 5 Si3 482 S mart P S E - 24 U G   Figure 6. Status Screen after an Overload on Port 3 To reset the port, decrease the load back to one resistor; unplug the PD, and plug it back in. This demonstrates “retry after reconnect”. For Port 1 (PoE+ port with Class 4 PD), the overload does not happen even with 19.5 W being drawn by the PD. Note: Use caution because, in this case, the load resistors and PD will get hot.   Figure 7. Status Screen Showing Class 4 PD on Port 1 Drawing 19 W Step 4: Demonstrate the port priority and system overload protection features. Disconnect all PDs, and then connect the Class 3 PDs to Ports 2 and 3 with two load resistors so that they draw 13 W each (26 W total power). 6 Rev. 0.2 Si3482 Smart PSE-24 UG Connect the Class 4 PD with three resistors (19.5 W) to Port 1. Port 1 is granted power, and a system-level overload is created with approximately 45.5 W. Either Port 3 or Ports 2 and 3 will be turned off depending on whether the Si3480 reported a severe overload (>44 W). Because the PDs have a soft start circuit, it is possible that only Port 3 is turned off when the power exceeds 40 W. The ports that are turned off will not turn back on until the load on Port 1 is reduced. This is because there is not enough power available to grant 15.4 W from the Class 3 PD.   Figure 8. Status Screen Showing Port 3 Denied Power Due to Insufficient Power Available The Si3482 will manage power on all Si3452 devices to which it is connected. The number of Si3452 devices connected is discovered upon power up. This means that the Si3482 can manage power on up to 48 ports. Once configured, the Si3482 will continue to manage the power even when the host is disconnected. To demonstrate this, exit the GUI, disconnect the PoE USB adapter, and repeat the above tests. While there is no visual display, the behavior is the same. The PD status can be seen by looking at the LEDs on the Si3402 evaluation boards located on the RJ-45 connector. These LEDs glow steadily if power is supplied. Note that, in the schematics shown in Figure 6, the Reset and Pgood2 signals are routed through an Si8423 isolator. The Si8423 default state is high so that, when the USB connector is removed, the Si3482 is not held in reset, and Power Supply 2 is still configured as inserted. This is why Power Supply 2 was chosen to be inserted in the above examples. 4.1. Easing Software Development with the Serial Packet Protocol SDK A host MCU uses the Serial Packet Protocol (SPP) to communicate with an Si3482 Power Management Controller. A Serial Packet Client in the host MCU implements the client side of the Serial Packet Protocol. The SPP Software Development Kit (SDK) provides the source code for the Serial Packet Client, greatly reducing the software development effort needed to use an Si3482. The software included with this SMARTPSE24-KIT includes the SPP SDK and related documentation. Please refer to that software as well as the Si3482 data sheet for further details on taking the next step in development with the Si3482 power management controller. Rev. 0.2 7 Rev. 0.2 +3V3LV 16 GND 15 SW_POWER_GOOD2 1 2 3 4 5 6 7 8 14 GND 13 SW_POWER_GOOD1 1 3 5 7 9 11 13 15 HEADER 8x2 2 4 6 8 10 12 14 16 INPUT POWER C816 0.1uF CONTROL HEADER UNISOLATED 26-60-5080 J815 12 GND 11 POE_RESETn JP7 TPV TPV803 HEADER 1x3 680pF Isolation PGOOD1_OUT PGOOD2_OUT PGOOD2_IN PGOOD1_IN RESETn_HOST RESETn RX TX D801 MBRS3100T3 SW PUSHBUTTON SW1 C819 0.1uF RESETn 1 3 5 7 9 2 4 6 8 10 2 4 6 8 10 R830 2 4 6 8 10 2 4 6 8 10 HEADER 5x2 1 3 5 7 9 J817 R838 10K R832 10K R840 10K 6 5 2 1 24 23 22 21 NI PS1 PS2 PS3 RSVD RSVD RSVD SDA SCL BAUD0 BAUD1 BAUD2 PSLCT RSVD INT 20 19 12 11 10 9 8 7 18 17 16 15 14 13 -48V -48V_RTN VIO C802 0.1uF +3V3_RTN +3V3 -52V->+3.3V Converter VREG RSVD RST SCK MISO MOSI NSS TX RX U802 Si3482 RESETn +3V3 JP8 HEADER 1x3 +3V3 PWR Status LED NI JP9 HEADER 1x3 C810 0.1uF +1V1REG 267 R833 +3V3 D803 GREEN 3.3V PWR R841 332 +3V3 RESETn SDA1 SCL1 INT1 Baud select +3V3 R805 1K SPI/UART SELECT PS3 JP4 HEADER 1x3 HEADER 1x3 JP5 HEADER 1x3 JP6 TPV TPV806 R804 TPV 1K TPV807 TPV TPV808 C803 4.7uF +3V3 -52V C815 10uF R802 10K +3V3 U801 TLV431 +1.24REG VREF_IN LineFeeds RESET_L SDA SCL INT Figure 9. Si3482 power manager and top level board schematic R839 10K SPI Non Iso 1 3 5 7 9 SILABS DEBUG HEADER 5X2 Shrouded Header PSU Debug 1 3 5 7 9 J809 1K R14 1K RX TX TPV804 TPV TPV802 TPV +3V3 Connect to EGND at Mount Holes C817 680pF R15 10K TPV TX_HOST RX_HOST +3V3LV C818 1 RX_HOST 3 TX_HOST 5 7 9 11 RESETn_HOST 13 PGOOD1 15 PGOOD2 10 GND 9 I2C_SDA 2 4 6 8 10 12 14 16 8 +3V3 7 I2C_SCL +3V3LV TPV805 -52V J816 6 +3V3 -52V +3V3LV EGND 4 BRD_TYPE -52V 4 VDD GND 3 +3V3 GND +3V3 GND EPAD 2 POE_INTn +3V3 +3V3 +3V3 5 POE_DISABLE_PORTSn R834 2.1K R835 0 +3V3_RTN CONNECTOR PIN DEFINITION VOUT12 VOUT13 VOUT14 VOUT15 VOUT16 VOUT17 VOIT18 VOUT19 VOUT20 VOUT21 VOUT22 VOUT23 VOUT0 VOUT1 VOUT2 VOUT3 VOUT4 VOUT5 VOUT6 VOUT7 VOUT8 VOUT9 VOUT10 VOUT11 TP804 GND R837 2.1K +1V1REG R836 267 -52V -52V 3 UART_TX 2 1 4 J5 3 6 5 8 7 10 9 12 11 14 13 16 15 18 17 20 19 22 21 24 23 2 1 4 3 6 J4 5 8 7 10 9 12 11 14 13 16 15 18 17 20 19 22 21 24 23 HEADER 12x2 33uF C812 + 33uF C813 + 33uF C814 + BULK DECOUPLING HEADER 12x2 VOUT12 VOUT13 VOUT14 VOUT15 VOUT16 VOUT17 VOUT18 VOUT19 VOUT20 VOUT21 VOUT22 VOUT23 VOUT0 VOUT1 VOUT2 VOUT3 VOUT4 VOUT5 VOUT6 VOUT7 VOUT8 VOUT9 VOUT10 VOUT11 TP803 GND -52V 8 1 UART_RX Si3 482 S mart P S E - 24 U G 4.2. Schematics The following figures show the detailed schematics, BOM, and layout for the Si3482evaluation board. -52V_RTN +3V3 +3V3 VOUT1 VOUT2 VOUT3 VOUT4 AD0 AD1 AD2 AD3 VOUT14 VOUT15 +3V3 VOUT13 -52V VOUT12 R1 0 VOUT19 Address 1110 or 1111 VOUT23 VOUT22 VOUT21 VOUT20 VOUT4 AD0 AD1 AD2 AD3 VOUT3 VOUT2 VOUT17 VOIT18 VOUT1 VOUT16 VREF_IN Analog Signals Address 1010 or 1011 -52V Address 1100 or 1101 VREF_IN -52V -52V_RTN +3V3_RTN R2 10K -52V -52V -52V VOUT4 AD0 AD1 AD2 AD3 VOUT3 VOUT2 VOUT1 -52V +3V3 Si3452 Si3452 Si3452 VREF_IN RESET_L SDA SCL INT H5 VREF_IN RESET_L SDA SCL INT H4 VREF_IN RESET_L SDA SCL INT H3 VREF_IN VREF_IN VREF_IN VREF_IN VREF_IN VREF_IN H2 H1 H0 VREF_IN RESET_L SDA SCL INT VREF_IN RESET_L SDA SCL INT VREF_IN RESET_L SDA SCL INT +3V3 SCL INT RESET_L SDA Si3452 Si3452 Si3452 Figure 10. Si3452 PSE controller bank schematic -52V -52V_RTN -52V_RTN -52V_RTN VOUT1 VOUT2 VOUT3 VOUT3 VOUT4 AD0 AD1 AD2 AD3 VOUT4 AD0 AD1 AD2 AD3 VOUT3 VOUT2 VOUT1 VOUT4 AD0 AD1 AD2 AD3 VOUT3 VOUT2 VOUT1 VOUT11 VOUT10 VOUT9 VOUT8 Address 1000 or 1001 Address 0100 or 0101 VOUT7 VOUT6 VOUT5 VOUT4 Address 0000 or 0001 VOUT0 -52V VOUT2 +3V3 VOUT1 -52V_RTN +3V3 +3V3_RTN +3V3 +3V3 +3V3_RTN +3V3 +3V3 +3V3_RTN +3V3 +3V3 +3V3_RTN -52V -52V -52V -52V +3V3 +3V3_RTN +3V3 +3V3 +3V3_RTN -52V_RTN -52V_RTN Rev. 0.2 -52V Board address Si3482 Smart PSE-24 UG 9 RESET_L -52V -52V_RTN +3V3_RTN SDA SCL INT AD_0 AD_0 AD_1 AD_2 AD_3 VREF_IN AD0 Address selection VREF_IN INT R108 10K -52V 44.2K R126 AD_1 7 3 9 4 5 6 38 14 16 26 21 23 28 27 25 24 40 34 36 1 31 22 10 Si3452 RBIAS VREF_IN OSC AIN AOUT AGND RST AD0/SDA AD1/SCL AD2 AD3 RST AD0 AD1 AD2 AD3 INT TX/AD0 RX/AD1 VEE1 VEE2 VEE3 VEE4 U100 C104 0.1uF R109 10K AD2 AD_2 SI3452 IC NC VOUT4 DET4 VOUT3 DET3 VOUT2 DET2 VOUT1 DET1 DETP3 VOUTP3 DETP4 VOUTP4 18 20 13 12 11 17 VOUTP2 DETP2 33 32 VOUTP1 DETP1 C100 0.1uF 39 37 C105 0.1uF R110 10K AD3 AD_3 Figure 11. Si3452 PSE Schematic Detail C116 0.1uF RESET AD1 DGND AGND 29 8 +3V3 19 30 VDD VDD VEE VEE EPAD 2 -52V GND34 GND12 Rev. 0.2 15 35 +3V3 -52V 10 C101 0.1uF -52V +3V3 C102 0.1uF R111 10K C103 0.1uF C114 0.1uF C111 0.1uF C109 0.1uF C107 0.1uF VOUT4 VOUT3 VOUT2 VOUT1 Si3 482 S mart P S E - 24 U G EGND PGOOD2_IN RESETn_HOST RX_HOST TX_HOST PGOOD1_IN C5 1uF +3V3LV C8 1uF Si8423 A2 A1 U3 Si8431 EN1 NC A3 A2 A1 B2 B1 EN2 NC B3 B2 B1 6 7 10 11 12 13 14 C7 1uF C6 1uF +3V3 1 VDD1 Figure 12. UART Isolator Circuitry 3 2 7 6 5 4 3 U2 1 VDD1 GND1 GND1 8 2 GND1 4 ISOLATION ISOLATION 16 VDD2 GND2 GND2 GND2 9 15 8 VDD2 Rev. 0.2 5 +3V3LV +3V3 PGOOD2_OUT RESETn TX RX PGOOD1_OUT Isolated Circuits +3V3 +3V3LV NonIsolated Circuits GND +3V3 Si3482 Smart PSE-24 UG 11 +3V3LV -48V R150 5.6 C150 0.1uF R157 10K Rev. 0.2 NC +3V3 ISOSSFT Vdd SSFT EROUT 25.5K R151 4 3 2 1 MBRS1100 D301 Vneg Figure 13. DC to DC converter 30 Ohm FB151 C155 470uF Optional short circuit protection. Si3500 Vposf NC NC U152 Q1 MMBT3904 11 12 13 14 Vssa C153 1uF 10 C152 1uF 15 Vssa NC 16 Vposs 17 8 Vneg 9 VSS1 NC 18 SWO HSO 7 19 VSS2 20 5 RDET 6 FB 21 EPAD 12 NC L151 33uH + -48V_RTN C158 0.1uF C161 0.33uF Vssa C156 22uF C159 4.7nF +3V3 C162 150pF R156 4.87K R155 2.87K C160 4.7nF +3V3 +3V3_RTN Si3 482 S mart P S E - 24 U G +3V3 R153 30.1K -52V Rev. 0.2 13 RTN12 RTN13 RTN14 RTN15 RTN16 RTN17 RTN18 RTN19 RTN20 RTN21 RTN22 RTN23 RTN0 RTN1 RTN2 RTN3 RTN4 RTN5 RTN6 RTN7 RTN8 RTN9 RTN10 RTN11 2 4 6 8 10 12 14 16 18 20 22 24 HEADER 12x2 1 3 5 7 9 11 13 15 17 19 21 23 J8 2 4 6 8 10 12 14 16 18 20 22 24 HEADER 12x2 1 3 5 7 9 11 13 15 17 19 21 23 J4 VOUT12 VOUT13 VOUT14 VOUT15 VOUT16 VOUT17 VOUT18 VOUT19 VOUT20 VOUT21 VOUT22 VOUT23 VOUT0 VOUT1 VOUT2 VOUT3 VOUT4 VOUT5 VOUT6 VOUT7 VOUT8 VOUT9 VOUT10 VOUT11 J7A RJ-45 A1 A2 MX0+ MX0- A1 A2 B3 B6 B7 B8 J7C RJ-45 J6C RJ-45 C1 C2 VOUT18 RTN18 VOUT10 RTN10 VOUT2 RTN2 C3 C6 C4 C5 MX0+ MX0MX1+ MX1MX2+ MX2MX3+ MX3MX0+ MX0MX1+ MX1MX2+ MX2MX3+ MX3MX0+ MX0MX1+ MX1MX2+ MX2MX3+ MX3- J7D RJ-45 J6D RJ-45 MX0+ MX0- J5D RJ-45 D1 D2 VOUT19 RTN19 VOUT11 RTN11 VOUT3 RTN3 D3 D6 MX1+ MX1MX2+ MX2MX3+ MX3- J7E RJ-45 J6E RJ-45 MX0+ MX0- J5E RJ-45 E1 E2 VOUT20 RTN20 VOUT12 RTN12 VOUT4 RTN4 E3 E6 E7 E8 MX1+ MX1MX2+ MX2MX3+ MX3- J7F RJ-45 J6F RJ-45 MX0+ MX0- J5F RJ-45 F1 F2 VOUT21 RTN21 VOUT13 RTN13 VOUT5 RTN5 F3 F6 F4 F5 MX1+ MX1MX2+ MX2MX3+ MX3- J7G RJ-45 J6G RJ-45 MX0+ MX0- J5G RJ-45 G1 G2 VOUT22 RTN22 VOUT14 RTN14 VOUT6 RTN6 G3 G6 MX1+ MX1MX2+ MX2MX3+ MX3- J7H RJ-45 J6H RJ-45 MX0+ MX0- J5H RJ-45 H1 H2 VOUT23 RTN23 VOUT15 RTN15 VOUT7 RTN7 H3 H6 H7 H8 J5C RJ-45 Figure 14. RJ-45 Ethernet Cable Connector Board VOUT17 VOUT9 RTN9 VOUT1 RTN17 J7B RJ-45 J6B RJ-45 B1 B2 RTN1 VOUT16 A3 A6 A4 A5 MX2+ MX2- A7 A8 MX3+ MX3MX0+ MX0MX1+ MX1- B4 B5 MX2+ MX2MX3+ MX3MX0+ MX0MX1+ MX1MX2+ MX2- C7 C8 MX3+ MX3MX0+ MX0MX1+ MX1- D4 D5 MX2+ MX2- D7 D8 MX3+ MX3MX0+ MX0MX1+ MX1- E4 E5 MX2+ MX2MX3+ MX3MX0+ MX0MX1+ MX1MX2+ MX2- F7 F8 MX3+ MX3MX0+ MX0MX1+ MX1- G4 G5 MX2+ MX2- G7 G8 MX3+ MX3MX0+ MX0MX1+ MX1- H4 H5 MX2+ MX2MX3+ MX3- J5B RJ-45 RTN16 VOUT8 RTN8 VOUT0 MX1+ MX1- RTN0 A3 A6 B1 B2 B3 B6 B7 B8 C1 C2 C3 C6 C4 C5 D1 D2 D3 D6 D4 D5 E1 E2 E3 E6 E4 E5 E7 E8 F1 F2 F3 F6 F4 F5 G1 G2 G3 G6 G4 G5 H1 H2 H3 H6 H4 H5 H7 H8 J6A RJ-45 MX0+ MX0MX1+ MX1- A4 A5 MX2+ MX2- A7 A8 MX3+ MX3MX0+ MX0MX1+ MX1- B4 B5 MX2+ MX2MX3+ MX3MX0+ MX0MX1+ MX1MX2+ MX2- C7 C8 MX3+ MX3MX0+ MX0MX1+ MX1MX2+ MX2- D7 D8 MX3+ MX3MX0+ MX0MX1+ MX1MX2+ MX2MX3+ MX3MX0+ MX0MX1+ MX1MX2+ MX2- F7 F8 MX3+ MX3MX0+ MX0MX1+ MX1MX2+ MX2- G7 G8 MX3+ MX3MX0+ MX0MX1+ MX1MX2+ MX2MX3+ MX3- J5A RJ-45 A1 A2 A3 A6 A4 A5 A7 A8 B1 B2 B3 B6 B4 B5 B7 B8 C1 C2 C3 C6 C4 C5 C7 C8 D1 D2 D3 D6 D4 D5 D7 D8 E1 E2 E3 E6 E4 E5 E7 E8 F1 F2 F3 F6 F4 F5 F7 F8 G1 G2 G3 G6 G4 G5 G7 G8 H1 H2 H3 H6 H4 H5 H7 H8 MX1+ MX1MX2+ MX2MX3+ MX3- Si3482 Smart PSE-24 UG Si3 482 S mart P S E - 24 U G 4.3. Bill of Materials Table 3. Si3482 Smart PSE-24 Bill of Materials Item Qty Ref Value 1 4 C5,C6,C7,C8 Tol PCB Footprint Mfr Part # Mfr 1 µF ±20% C0805 C0805X7R160-105M Venkel 50 C100,C101,C102, C103,C107,C109, C111,C114,C150, C200,C201,C202, C203,C207,C209, C211,C214,C300, C301,C302,C303, C307,C309,C311, C314,C400,C401, C402,C403,C407, C409,C411,C414, C500,C501,C502, C503,C507,C509, C511,C514,C600, C601,C602,C603, C607,C609,C611, C614,C816 0.1 µF ±20% C0603 C0603X7R101-104M Venkel 3 20 C104,C105,C116, C204,C205,C216, C304,C305,C316, C404,C405,C416, C504,C505,C516, C604,C605,C616, C802,C810 0.1 µF ±20% C0603 C0603X7R160-104M Venkel 4 2 C152,C153 1 µF ±10% C1210 C1210X7R101-105K Venkel 5 1 C155 470 µF ±20% C7343D T495D477M006ATE0457280 Kemet 6 1 C156 22v ±20% C0805 C0805X5R6R3-226M Venkel 7 1 C158 0.1 µF ±10% C0603 C0603X7R250-104K Venkel 8 2 C159,C160 4.7 nF ±10% C0603 C0603X7R160-472K Venkel 2 Rating 45 m ESR 9 1 C161 0.33 µF ±10% C0603 C0603X7R100-334K Venkel 10 1 C162 150 pF ±10% C0603 C0603X7R160-151K Venkel 11 1 C803 4.7 µF ±20% C1206 C1206X7R100-475M Venkel 12 3 C812,C813,C814 33 µF ±20% C3.5X8MM-RAD ECA2AM330 Panasonic ±20% C0603 C0603X5R6R3-106M Venkel ±15% C1808 GA342QR7GD681KW01L MuRata ±20% C0805 C0805X7R160-104M Venkel DO-214AA MBRS1100T3 On Semi 13 1 C815 10 µF 14 2 C817,C818 680 pF 15 1 C819 0.1 µF 16 1 D301 MBRS1100 17 1 D801 MBRS3100T3 3A DO-214AB MBRS3100T3 On Semi 18 1 D803 GREEN 30 mA LED-0805-K LTST-C170GKT Lite_In Inc 19 1 FB151 30  1000 mA L0603 BLM18PG300SN1 MuRata 20 6 JP4,JP5,JP6, JP7,JP8,JP9 HEADER 1x3 CONN-1X3 TSW-103-07-T-S Samtec 21 2 J4,J5 HEADER 12x2 CONN2X12-2MM TMM-112-01-T-D Samtec 22 1 J809 5X2 Shrouded Header CONN2X5-4W 2510-6002UB 3M 23 1 J815 26-60-5080 CONN8NP0.156RA 26-60-5080 MOLEX 14 Y3 1A Rev. 0.2 Si3482 Smart PSE-24 UG Table 3. Si3482 Smart PSE-24 Bill of Materials (Continued) Item Qty Ref Value Rating Tol PCB Footprint Mfr Part # 24 1 J816 25 1 J817 HEADER 8x2 CONN2X8 TSW-108-07-S-D Samtec HEADER 5x2 CONN2X5 TSW-105-07-T-D Samtec 26 1 L151 33 µH 0.4 A IND-LPS4018 LPS4018-333ML Coilcraft 27 1 Q1 MMBT3904 200 mA SOT23-BEC MMBT3904 Fairchild 28 2 R1,R835 0 1A R0603 CR0603-10W-000 Venkel 29 2 R2,R157 10 k 1/10 W ±5% R0603 CR0603-10W-103J Venkel 30 4 R14,R804, R805,R830 1 k 1/10 W ±1% R0603 CR0603-10W-1001F Venkel 31 30 R15,R108,R109, R110,R111,R208, R209,R210,R211, R308,R309,R310, R311,R408,R409, R410,R411,R508, R509,R510,R511, R608,R609,R610, R611,R802,R832, R838,R839,R840 10 k 1/10 W ±1% R0603 CR0603-10W-1002F Venkel 32 6 R126,R226,R326, R426,R526,R626 44.2 k 1/10 W ±1% R0603 CR0603-10W-4422F Venkel 33 1 R150 5.6  1/4 W ±5% R1210 CR1210-4W-5R6J Venkel 34 1 R151 25.5 k 1/16 W ±1% R0603 CR0603-16W-2552F Venkel 35 1 R153 30.1 k 1/16 W ±1% R0603 CR0603-16W-3012F Venkel 36 1 R155 2.87 k 1/16 W ±1% R0603 CR0603-16W-2871F Venkel 37 1 R156 4.87 k 1/16 W ±1% R0603 CR0603-16W-4871F Venkel ±20% Mfr 38 2 R833,R836 267  1/10 W ±1% R0603 CR0603-10W-2670F Venkel 39 2 R834,R837 2.1  1/16 W ±1% R0603 CR0603-16W-2101F Venkel 40 1 R841 332  1/10 W ±1% R0603 CR0603-10W-3320F Venkel 41 1 SW1 SW Pushbutton 50 mA SW4N6.5X4.5-PB 101-0161-EV Mountain Switch 42 13 TPV100,TPV200, TPV300,TPV400, TPV500,TPV600, TPV802,TPV803, TPV804,TPV805, TPV806,TPV807, TPV808 TPV VIA-TP N/A N/A 43 1 TPV50x1 EPAD VIA-EPAD N/A N/A 44 1 TP17 RED Testpoint 151-207-RC Kobiconn 45 1 TP18 WHITE Testpoint 151-201-RC Kobiconn 46 2 TP803,TP804 BLACK Testpoint 151-203-RC Kobiconn 47 1 U1 Si8423 2500 VRMS SO8N6.0P1.27 Si8423AD-B-IS-1 SiLabs 48 1 U2 Si8431 2500 VRMS SO16N10.3P1.27 Si8431BB-C-IS SiLabs 6 U100,U200,U300, U400,U500,U600 Si3452 QFN40N6X6P0.5 Si3452-A00-GM SiLabs 49 50 1 U152 Si3500 QFN20N5X5P0.8 Si3500-A-GM SiLabs 51 1 U801 TLV431 TLV431-DBZ TLV431BCDBZR TI 52 1 U802 Si3482 QFN20N4X4P0.5 Si3482 SiLabs Rev. 0.2 15 Si3 482 S mart P S E - 24 U G Figure 15. Smart PSE 24Silk Screen 4.4. Silkscreens 16 Rev. 0.2 Figure 16. Smart PSE 24 Top Layer Si3482 Smart PSE-24 UG Rev. 0.2 17 Figure 17. Smart PSE 24 Ground Layer Si3 482 S mart P S E - 24 U G 18 Rev. 0.2 Figure 18. Smart PSE 24 Power Plane Si3482 Smart PSE-24 UG Rev. 0.2 19 Figure 19. Smart PSE 24 Secondary Side Si3 482 S mart P S E - 24 U G 20 Rev. 0.2 Si3482 Smart PSE-24 UG DOCUMENT CHANGE LIST Revision 0.1 to Revision 0.2  Added "Easing Software Development with the Serial Packet Protocol SDK‚" on page 7 to describe availability of the Serial Packet Protocol SDK. Rev. 0.2 21 Si3 482 S mart P S E - 24 U G CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. 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