Si5324

Si5317 P R E L I M I N A R Y D A TA S H E E T P I N - C ONTR OLLED 1 –710 MH Z J I T T E R C LEAN ING C LOCK Features       Provides jitter attenuation on any frequency One clock input / two clock outputs Input/output frequency range: 1–710 MHz Ultra low jitter: 300 fs (12 kHz–20 MHz) typical Simple pin control interface Selectable loop bandwidth for jitter attenuation: 60 Hz–8.4 kHz        Selectable output clock signal format: LVPECL, LVDS, CML or CMOS Single supply: 1.8, 2.5, or 3.3 V VCO freeze during LOS/LOL Loss of lock and loss of signal alarms On-chip voltage regulator with high PSRR Small size: 6 x 6 mm, 36-QFN Wide temperature range: –40 to +85 ºC Applications   Ordering Information:   Data converter clocking Wireless infrastructure  Networking, SONET/SDH Switches and routers Medical instrumentation  Test and measurement See page 43. Description The Si5317 is a flexible 1:1 jitter cleaning clock for high-performance applications that require jitter attenuation without clock multiplication. The Si5317 accepts a single clock input ranging from 1 to 710 MHz and generates two low jitter clock outputs at the same frequency. The clock frequency range and loop bandwidth are selectable from a simple look-up table. The Si5317 is based on Silicon Laboratories' 3rd-generation DSPLL® technology, which provides jitter attenuation on any frequency in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is user selectable, providing jitter performance optimization at the application level. Pin Assignments CKOUT1– CKOUT2+ CKOUT2SFOUT0 CKOUT1+ 27 FRQSEL3 26 FRQSEL2 25 FRQSEL1 24 FRQSEL0 23 BWSEL1 22 BWSEL0 21 NC 20 DEC 19 INC 10 11 12 13 14 15 16 17 18 CKIN+ VDD NC NC CKIN– RATE0 DBL2_BY RATE1 LOL SFOUT1 VDD 36 35 34 33 32 31 30 29 28 RST 1 FRQTBL 2 LOS 3 NC 4 VDD 5 XA 6 XB 7 NC GND Pad Functional Block Diagram XTAL/Clock GND 8 NC 9 Clock Out1 Clock In DSPLL ® Signal Format [1:0] Clock Out2 Status/Control High PSRR Regulator VDD (1.8, 2.5, 3.3 V) GND Frequency Table Frequency Select [3:0] Bandwidth Select [1:0] Phase Skew INC/DEC Loss of Lock Loss of Signal XTAL/Clock Rate [1:0] Preliminary Rev. 0.15 4/10 Copyright © 2010 by Silicon Laboratories GND Si5317 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. S i5317 2 Preliminary Rev. 0.15 S i5317 TABLE O F C ONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.1. Three-Level (3L) Input Pins (No External Resistors) . . . . . . . . . . . . . . . . . . . . . . . . .9 1.2. Three-Level Input Pins (with External Resistors) . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3. Frequency Plan Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 3.1. Frequency Range Plan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2. Output Skew Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3. PLL Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.4. Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.5. VCO Freeze . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.6. PLL Bypass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4. High-Speed I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1. Input Clock Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.2. Output Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5. Crystal/Reference Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 5.1. Crystal/Reference Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 6. Power Supply Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7. Typical Phase Noise Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 7.1. Example: SONET OC-192 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8. Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 9. Pin Descriptions: Si5317 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 10. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 11. Package Outline: 36-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 12. Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 13. Si5317 Device Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Preliminary Rev. 0.15 3 S i5317 1. Electrical Specifications Table 1. Recommended Operating Conditions (VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC) Parameter Temperature Range Supply Voltage Symbol TA VDD Test Condition 3.3 V nominal 2.5 V nominal 1.8 V nominal Min –40 2.97 2.25 1.71 Typ 25 3.3 2.5 1.8 Max 85 3.63 2.75 1.89 Unit ºC V V V Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted. Table 2. DC Characteristics (VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC) Parameter Supply Current (Supply current is independent of VDD) Symbol IDD Test Condition LVPECL Format 622.08 MHz Out All CKOUTs Enabled1 LVPECL Format 622.08 MHz Out Only 1 CKOUT Enabled1 CMOS Format 19.44 MHz Out All CKOUTs Enabled2 CMOS Format 19.44 MHz Out Only CKOUT1 Enabled2 1.8 V ± 5% 2.5 V ± 10% 3.3 V ± 10% Min — Typ 251 Max 279 Units mA — 217 243 mA — 204 234 mA — 194 220 mA CKIN Input Pin Input Common Mode Voltage (Input Threshold Voltage) Input Resistance Input Voltage Level Limits Single-ended Input Voltage Swing VICM 0.9 1.0 1.1 20 0 0.2 0.25 — — — 40 — — — 1.4 1.7 1.95 60 VDD — — V V V k V VPP VPP CKNRIN CKNVIN VISE Single-ended See note 3 fCKIN < 212.5 MHz See Figure 2. fCKIN > 212.5 MHz See Figure 2. Notes: 1. LVPECL outputs require VDD > 2.25 V. 2. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 9. In most designs, an external resistor voltage divider is recommended. 3. No overshoot or undershoot. 4 Preliminary Rev. 0.15 S i5317 Table 2. DC Characteristics (Continued) (VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC) Parameter Differential Input Voltage Swing Symbol VID Test Condition fCKIN < 212.5 MHz See Figure 2. fCKIN > 212.5 MHz See Figure 2. Min 0.2 0.25 Typ — — Max — — Units VPP VPP CKOUT Output Clock1 Common Mode Differential Output Swing Single-ended Output Swing Differential Output Voltage Common Mode Output Voltage Differential Output Voltage VOCM VOD VSE CKOVD CKOVCM CKOVD LVPECL 100  load line-to-line LVPECL 100  load line-to-line LVPECL 100  load line-to-line CML 100  load line-to-line CML 100  load line-to-line LVDS 100  load line-to-line Low swing LVDS 100  load line-to-line Common Mode Output Voltage Output Short to GND CKOVCM CKOISC LVDS 100  load line-to-line VDD = 3.63 V CML, LVDS, LVPECL VDD = 1.89 V CML, LVDS VDD = 3.63 V CMOS VDD = 1.89 V CMOS Disable VDD – 1.42 1.1 0.5 350 — 500 350 1.125 — — — — — — — — 425 VDD – 0.36 700 425 1.2 80 45 165 65 0.1 VDD – 1.25 1.9 0.93 500 — 900 500 1.275 90 50 175 70 0.2 V VPP VPP mVPP V mVPP mVPP V mA mA mA mA µA Notes: 1. LVPECL outputs require VDD > 2.25 V. 2. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 9. In most designs, an external resistor voltage divider is recommended. 3. No overshoot or undershoot. Preliminary Rev. 0.15 5 S i5317 Table 2. DC Characteristics (Continued) (VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC) Parameter Output Short to VDD Symbol CKOISC+ Test Condition VDD = 3.63 V CML, LVDS, LVPECL VDD = 1.89 V CML, LVDS VDD = 3.63 V CMOS VDD = 1.89 V CMOS Disable Min — — — — — 170 85 1 — 0.8 x VDD Typ 25 25 190 70 1.5 200 100 — — — Max 30 30 200 80 2 230 115 — 0.4 — Units mA mA mA mA µA   M V V Differential Output Resistance Common Mode Output Resistance (to VDD) Output Voltage Low Output Voltage High Output Drive Current CKORD CKORCM CKOVOLLH CKOVOHLH CKOIO CML, LVPECL, LVDS, Disable CML, LVPECL, LVDS Disable CMOS VDD = 1.71 V CMOS CMOS Driving into CKOVOL for output low or CKOVOH for output high. CKOUT+ and CKOUT– shorted externally. VDD = 1.71 V VDD = 2.97 V 7.5 32 — — — — mA mA 2-Level LVCMOS Input Pins Input Voltage Low VIL VDD = 1.71 V VDD = 2.25 V VDD = 2.97 V Input Voltage High VIH VDD = 1.89 V VDD = 2.25 V VDD = 3.63 V Input Low Current Input High Current Weak Internal Input Pull-up Resistor IIL IIH RPUP — — — 1.4 1.8 2.5 — — — — — — — — — — — 75 0.5 0.7 0.8 — — — 50 50 — V V V V V V µA µA k Notes: 1. LVPECL outputs require VDD > 2.25 V. 2. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 9. In most designs, an external resistor voltage divider is recommended. 3. No overshoot or undershoot. 6 Preliminary Rev. 0.15 S i5317 Table 2. DC Characteristics (Continued) (VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC) Parameter Weak Internal Input Pull-down Resistor 3-Level Input Pins Input Voltage Low Input Voltage Mid Input Voltage High Input Low Current Input Mid Current Input High Current LVCMOS Output Pins Output Voltage Low Symbol RPDN Test Condition Min — Typ 75 Max — Units k VILL VIMM VIHH IILL 2 — 0.45 x VDD 0.85 x VDD — — — — — — 0.15 x VDD 0.55 x VDD V V V µA µA µA — — 2 20 –20 –2 — IIMM2 IIHH 2 VOL IO = 2 mA VDD = 1.62 V IO = 2 mA VDD = 2.97 V — — VDD – 0.4 VDD – 0.4 — — — — 0.4 0.4 — — V V V V Output Voltage High VOH IO = –2 mA VDD = 1.62 V IO = –2 mA VDD = 2.97 V Single-Ended Reference Clock Input Pin XA (XB with cap to gnd) Input Resistance Input Voltage Level Limits Input Voltage Swing XARIN XAVIN XAVPP XA/XBRIN XA/XBVIN XAVPP/XBVPP XTAL/RefCLK RATE[1:0] = LM, ML, MH, or HM XTAL/RefCLK RATE[1:0] = LM, ML, MH, or HM 8.5 0 0.5 10 — — 11.5 1.2 1.2 k V VPP k V VPP, each Differential Reference Clock Input Pins (XA/XB) Input Resistance Differential Input Voltage Level Limits Input Voltage Swing 8.5 0 0.5 10 — — 11.5 1.2 1.2 Notes: 1. LVPECL outputs require VDD > 2.25 V. 2. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 9. In most designs, an external resistor voltage divider is recommended. 3. No overshoot or undershoot. Preliminary Rev. 0.15 7 S i5317 V SIGNAL + Differential I/Os V , VOCM ICM SIGNAL – VISE , VOSE Single-Ended Peak-to-Peak Voltage (SIGNAL +) – (SIGNAL –) VID,VOD VICM, VOCM t Differential Peak-to-Peak Voltage SIGNAL + VID = (SIGNAL+) – (SIGNAL–) SIGNAL – Figure 1. Voltage Characteristics 80% DOUT, CLOUT 20% tF tR Figure 2. Rise/Fall Time Characteristics 8 Preliminary Rev. 0.15 S i5317 1.1. Three-Level (3L) Input Pins (No External Resistors) Si5317 Iimm VDD 75 k  External Driver 75 k  Figure 3. Three Level Input Pins 1.2. Three-Level Input Pins (with External Resistors) V DD Iimm 18 k  V DD Si5317 75 k  External Driver 18 k  75 k  One of eight resistors from a Panasonic EXB-D10C183J (or similar) resistor pack Figure 4. Three-Level Input Pins Table 3. Three-Level Input Pins1,2,3,4 Parameter Input Low Current Input Mid Current Input High Current Symbol Iill Iimm Iihh Min –30 µA –11 µA — Max — –11 µA –30 µA Notes: 1. The current parameters are the amount of leakage that the 3L inputs can tolerate from an external driver. In most designs, an external resistor voltage divider is recommended. 2. Resistor packs are only needed if the leakage current of the external driver exceeds the listed currents. Any resistor pack may be used (e.g. Panasonic EXB-D10C183J). PCB layout is not critical. 3. If a pin is tied to ground or VDD, no resistors are needed. 4. If a pin is left open (no connect), no resistors are needed. Preliminary Rev. 0.15 9 S i5317 Table 4. AC Characteristics (VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC) Parameter Input Frequency CKIN Input Pins Input Duty Cycle (Minimum Pulse Width) Input Capacitance Input Rise/Fall Time CKOUT Output Pins Output Frequency (Output not configured for CMOS or disable) Maximum Output Frequency in CMOS Format Single-ended Output Rise/Fall (20–80%) Symbol CKNF Test Condition Min 1 Typ — — — — — Max 710 60 — 3 11 Units MHz % ns pF ns CKNDC CKNCIN CKNTRF Whichever is smaller 40 2 — 20–80% See Figure 2 — CKOF CKOFMC CMOS Output VDD = 1.62 Cload = 5 pF CMOS Output VDD = 2.97 Cload = 5 pF 1 1 — — — — 710 212.5 8 MHz MHz ns CKOTRF — — 2 ns Differential Output Rise/Fall Time Output Duty Cycle Differential Uncertainty CKOTRF CKODC 20 to 80 %, fOUT = 622.08 100  Load Line to Line Measured at 50% Point (not for CMOS) — — 230 — 350 ±40 ps ps LVCMOS Pins Input Capacitance CIN — — 3 pF 10 Preliminary Rev. 0.15 S i5317 Table 4. AC Characteristics (Continued) (VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC) Parameter LVCMOS Output Pins Rise/Fall Times LOSn Trigger Window Time to Clear LOS Alarm Symbol tRF Test Condition CLOAD = 20 pf See Figure 2 Min — Typ 25 — Max — 750 220 Units ns µs ms LOSTRIG From LVST CKIN to LOS Measured from appearance tLOSCLR of valid CKIN to of LOS alarm fin unchanged and XA/XB stable. LOS to  LOL 90 — Time to Clear LOL after LOS Cleared tCLRLOL — 10 — ms PLL Performance Lock Time Closed Loop Jitter Peaking Jitter Tolerance Minimum Reset Pulse Width Lock Time Spurious Noise tLOCKHW RST with valid CKIN to  LOL; BW = 100 Hz JPK JTOL tRSTMIN tLOCKMP SPSPUR Reset b  to  of LOL Max spur @ n x f3 (n > 1, n x f3 < 100 MHz) BW determined by BWSEL[1:0] — — 5000/ BW 1 — — 0.05 — — 35 — 1.2 0.1 — — 1000 –75 sec dB ns pkpk µs ms dBc Preliminary Rev. 0.15 11 S i5317 Table 5. Performance Specifications1, 2, 3, 4, 5 (VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC) Parameter Jitter Generation fIN = fOUT = 622.08 MHz, LVPECL output format BW = 120 Hz Phase Noise fIN = fOUT = 622.08 MHz LVPECL output format Symbol JGEN Test Condition 50 kHz–80 MHz 12 kHz–20 MHz 800 Hz–80 MHz Min — — — — — — — — Typ 0.32 0.31 0.4 –65 –95 –110 –117 –130 Max 0.42 0.41 0.45 — — — — — Unit ps rms ps rms ps rms dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz CKOPN 100 Hz offset 1 kHz offset 10 kHz offset 100 kHz offset 1 MHz offset Notes: 1. BWSEL [1:0] loop bandwidth settings provided in Table 9 on page 22. 2. 114.285 MHz 3rd OT crystal used as XA/XB input. 3. VDD = 2.5 V 4. TA = 85 °C 5. Test condition: fIN = 622.08 MHz, fOUT = 622.08 MHz, LVPECL clock input: 1.19 Vppd with 0.5 ns rise/fall time (20-80%), LVPECL clock output. 12 Preliminary Rev. 0.15 S i5317 Table 6. Thermal Characteristics (VDD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 ºC) Parameter Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Symbol JA JC Test Condition Still Air Min — — Typ 32 14 Max — — Unit ºC/W ºC/W Table 7. Absolute Maximum Ratings Parameter DC Supply Voltage LVCMOS Input Voltage Operating Junction Temperature Storage Temperature Range ESD HBM Tolerance (100 pF, 1.5 kΩ); All pins except CKIN+/CKIN– ESD MM Tolerance; All pins except CKIN+/CKIN– ESD HBM Tolerance (100 pF, 1.5 kΩ); CKIN+/CKIN– ESD MM Tolerance; CKIN+/CKIN– Latch-Up Tolerance Symbol VDD VDIG TJCT TSTG Value –0.5 to 3.63 –0.3 to (VDD + 0.3) –55 to 150 –55 to 150 2 200 700 150 JESD78 Compliant Unit V V C C kV V V V Note: Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operation sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. Preliminary Rev. 0.15 13 S i5317 2. Functional Description External Crystal or Reference Clock RATE[1:0] XB XA 2 CKOUT+ CKOUT– SFOUT[1:0] CKIN+ CKIN– 2 f3 DSPLL® fOSC 2 CKOUT+ CKOUT– DBL2_BY LOS LOL RST BWSEL[1:0] FRQSEL[3:0] FRQTBL INC DEC Alarms Control Bandwidth Control Frequency Control Skew Control Voltage Regulator with High PSRR VDD (1.8, 2.5, or 3.3 V) GND Figure 5. Detailed Block Diagram 2.1. Overview The Si5317 is a 1:1 jitter-attenuating precision clock for applications requiring sub 1 ps jitter performance. The Si5317 accepts one clock input ranging from 1 to 710 MHz and generates two clock outputs at the same frequency ranging from 1 to 710 MHz. The Si5317 is based on Silicon Laboratories' 3rd-generation DSPLL® technology, which provides jitter attenuation on any frequency in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The nominal operating frequency is selectable from a look-up table. The Si5317 PLL loop bandwidth (BW) is selectable via the BWSEL[1:0] pins and supports a range from 60 Hz to 8.4 kHz. The Si5317 monitors the input clock for loss-of-signal (LOS) and provides a LOS alarm when it detects missing pulses on the input clock. The device monitors the lock status of the DSPLL. The lock detect algorithm works by continuously monitoring the phase of the input clock in relation to the phase of the feedback clock. The Si5317 provides a VCO freeze capability that allows the device to continue generation of a stable output clock when the selected input clock is lost. During VCO freeze, the DSPLL latches its VCO settings and uses its XA/XB clock as its frequency reference. The Si5317 has two output clock drivers and can be configured as four single-ended or two differential outputs. The signal format of the clock output is selectable to support LVPECL, LVDS, CML, or CMOS loads. The device operates from a single 1.8, 2.5, or 3.3 V supply. The use of LVPECL requires a VDD > 2.25 V. 14 Preliminary Rev. 0.15 S i5317 3. Frequency Plan Tables For ease of use, the Si5317 is pin-controlled to enable simple device configuration of the frequency range plan and PLL loop bandwidth via a predefined look-up table. The DSPLL has been optimized for jitter performance and tunability for each frequency range and PLL loop bandwidth provided in Table 9 on page 22. Many of the control inputs are three levels: High, Low, and Medium. High and Low are standard voltage levels determined by the supply pins: VDD and Ground. If the input pin is left floating, it is driven to nominally half of VDD. Effectively, this creates three logic levels for these controls. See section 6. "Power Supply Filtering" on page 35 and section 1.2. "Three-Level Input Pins (with External Resistors)" on page 9 for additional information. 3.1. Frequency Range Plan The input to output clock frequency range is set by the 3-level FRQSEL[3:0] and FRQTBL pins. The CKIN and CKOUT is the same frequency range as specified in Table 8. Due to the wide tunability of the Si5317, each frequency plan provides overlap between adjacent settings. To select a frequency plan, the desired frequency should be selected as close to the defined center frequency. In certain cases where the desired frequency is exactly between two overlapping plans, either FRQTBL and FRQSEL can be used. 3.1.1. PLL Loop Bandwidth Plan The Si5317's loop bandwidth ranges from 60 Hz to 8.4 kHz. For each frequency range, the corresponding loop bandwidth is provided in a simple look-up table (see Table 9 on page 22). The loop bandwidth is digitally programmable using the three-level BWSEL [1:0] input pins. 3.2. Output Skew Adjustment The overall device skew (CKIN to CKOUTn phase delay) is adjustable via the INC and DEC input pins. A positive edge triggered pulse applied to the INC pin increases the device skew defined by Table 8, INC/DEC step size, for each given frequency plan. The identical operation on the DEC pin decreases the skew by the same amount. Using the INC and DEC pins, there is no limit to the range of skew adjustment that can be made. Following a powerup or reset, the overall device skew will revert to the reset value, although the input-to-output skew is effectively random. The rate of change for each INC/DEC operation is defined by the selected loop bandwidth, BWSEL[1:0]. Preliminary Rev. 0.15 15 S i5317 Table 8. Look-up Tables for Fin = Fout Frequency Range and Loop Bandwidth Settings Frequency Range (MHz) Plan FRQTBL FRQSEL No [3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L LLLL LLLM LLLH LLML LLMM LLMH LLHL LLHM LLHH LMLL LMLM LMLH LMML LMMM LMMH LMHL LMHM LMHH LHLL LHLM LHLH LHML LHMM LHMH LHHL LHHM LHHH MLLL MLLM MLLH MLML MLMM MLMH MLHL Min 1.00 1.00 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.10 2.20 2.30 2.40 2.50 2.60 2.70 2.80 2.90 3.00 3.10 3.20 Center 1.00 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.10 2.20 2.30 2.40 2.50 2.60 2.70 2.80 2.90 3.00 3.10 3.20 3.30 Max 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.10 2.20 2.30 2.40 2.50 2.60 2.70 2.80 2.90 3.00 3.10 3.20 3.30 3.40 LH — — — — — — — — — — — — — — — — — — — BWSEL [1:0] (BW in Hz) ML 3814 3814 3834 4052 4251 4451 4652 4852 5054 5256 5256 5459 5866 5866 6071 6276 6483 6688 6895 MM 927 927 931 983 1030 1078 1125 1172 1219 1267 1267 1314 1409 1409 1457 1504 1552 1599 1647 560 575 591 622 983 1030 1078 1125 1172 1219 1267 1314 1409 1409 1457 MH 230 230 231 244 255 267 279 290 302 314 314 325 349 349 360 372 384 395 407 139 143 147 154 244 255 267 279 290 302 314 325 349 349 360 HL 114 114 115 121 127 133 139 145 150 156 156 162 174 174 180 185 191 197 69 71 73 77 121 127 133 139 145 150 156 162 174 174 180 INC/DEC Phase Change HM (ns) 57 57 57 60 63 66 69 72 75 78 78 81 87 87 89 92 95 98 — — — — 60 63 66 69 72 75 78 81 87 87 89 0.21 0.21 0.21 0.21 0.21 0.21 0.21 0.21 0.21 0.21 0.21 0.21 0.21 0.21 0.21 0.21 0.21 0.21 0.21 0.21 0.21 0.21 0.21 0.21 0.21 0.21 0.21 0.20 0.21 0.20 0.20 0.20 0.20 0.21 203 101 4696 2285 4832 2350 4967 2415 5239 2544 — — — — — — — — — — — 4052 4251 4451 4651 4852 5054 5255 5458 5859 5859 6071 Note: For BWSEL[1:0] settings LL, LM, HH are reserved. 16 Preliminary Rev. 0.15 S i5317 Table 8. Look-up Tables for Fin = Fout Frequency Range and Loop Bandwidth Settings Frequency Range (MHz) Plan FRQTBL FRQSEL No [3:0] 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L MLHM MLHH MMLL MMLM MMLH MMML MMMM MMMH MMHL MMHM MMHH MHLL MHLM MHLH MHML MHMM MHMH MHHL MHHM MHHH HLLL HLLM HLLH HLML HLMM HLMH HLHL HLHM HLHH HMLL HMLM HMLH HMML HMMM Min 3.30 3.40 3.50 3.60 3.70 3.80 3.90 4.00 4.20 4.40 4.60 4.80 5.00 5.20 5.40 5.60 5.80 6.00 6.20 6.40 6.60 6.80 7.00 7.20 7.40 7.60 7.80 8.00 8.40 8.80 9.00 9.20 9.60 10.00 Center 3.40 3.50 3.60 3.70 3.80 3.90 4.00 4.20 4.40 4.60 4.80 5.00 5.20 5.40 5.60 5.80 6.00 6.20 6.40 6.60 6.80 7.00 7.20 7.40 7.60 7.80 8.00 8.40 8.80 9.00 9.20 9.60 10.00 10.50 Max 3.50 3.60 3.70 3.80 3.90 4.00 4.20 4.40 4.60 4.80 5.00 5.20 5.40 5.60 5.80 6.00 6.20 6.40 6.60 6.80 7.00 7.20 7.40 7.60 7.80 8.00 8.40 8.80 9.00 9.20 9.60 10.00 10.50 11.00 LH — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — BWSEL [1:0] (BW in Hz) ML 6071 6276 6483 6895 6895 4650 4786 4919 5457 5457 5730 6268 6273 6550 6823 6823 6333 6571 6811 6071 6534 6534 6483 6686 6891 4648 4786 4919 6599 7080 7080 5727 6003 6273 MM 1457 1504 1552 1647 1647 1125 1156 1188 1314 1314 1378 1504 1504 1568 1631 1631 3064 3176 3289 1457 1567 1567 1552 1599 1647 1125 1156 1188 1580 1693 1693 1377 1441 1504 MH 360 372 384 407 407 279 286 294 325 325 341 372 372 387 403 403 748 774 801 360 387 387 384 395 407 279 286 294 391 418 418 341 356 372 HL 180 185 191 INC/DEC Phase Change HM (ns) 89 92 95 0.21 0.21 0.21 0.21 0.21 0.20 0.21 0.21 0.20 0.20 0.21 0.20 0.20 0.20 0.20 0.20 0.20 0.20 0.20 0.21 0.20 0.20 0.21 0.20 0.20 0.20 0.21 0.21 0.20 0.19 0.19 0.20 0.21 0.20 203 101 203 101 139 143 147 162 162 170 185 185 193 69 71 73 81 81 85 92 92 96 201 100 201 100 185 192 199 180 193 193 191 197 139 143 147 195 92 96 99 89 96 96 95 98 69 71 73 97 203 101 209 104 209 104 170 178 185 85 88 92 Note: For BWSEL[1:0] settings LL, LM, HH are reserved. Preliminary Rev. 0.15 17 S i5317 Table 8. Look-up Tables for Fin = Fout Frequency Range and Loop Bandwidth Settings Frequency Range (MHz) Plan FRQTBL FRQSEL No [3:0] 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 L L L L L L L L L L L L L M M M M M M M M M M M M M M M M M M M M M HMMH HMHL HMHM HMHH HHLL HHLM HHLH HHML HHMM HHMH HHHL HHHM HHHH LLLL LLLM LLLH LLML LLMM LLMH LLHL LLHM LLHH LMLL LMLM LMLH LMML LMMM LMMH LMHL LMHM LMHH LHLL LHLM LHLH Min 10.50 11.00 11.50 12.00 12.50 13.00 13.50 14.00 14.50 15.00 15.50 16.00 16.50 17.00 17.50 18.00 18.50 19.00 19.50 20.00 21.00 22.00 23.00 24.00 25.26 26.00 27.00 28.00 29.00 30.31 31.00 32.00 33.00 34.00 Center 11.00 11.50 12.00 12.50 13.00 13.50 14.00 14.50 15.00 15.50 16.00 16.50 17.00 17.50 18.00 18.50 19.00 19.50 20.00 21.00 22.00 23.00 24.00 25.00 26.00 27.00 28.00 29.00 30.00 31.00 32.00 33.00 34.00 35.00 Max 11.50 12.00 12.50 13.00 13.50 14.00 14.50 15.00 15.50 16.00 16.50 17.00 17.50 18.00 18.50 19.00 19.50 20.00 21.00 22.00 23.00 24.00 25.00 26.00 27.00 28.00 29.00 30.00 31.00 32.00 33.00 34.00 35.00 36.00 LH — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — BWSEL [1:0] (BW in Hz) ML 6992 5866 6155 6446 7034 5408 5633 5861 7383 6321 6321 6774 7230 4422 7342 7342 7298 4995 7518 6208 7429 6155 6155 6739 7613 6817 6817 7640 4941 7658 7658 6774 6774 7692 MM 1672 1409 1477 1545 1680 1303 1356 1409 1764 1515 1515 1620 1726 1071 1756 1756 1742 1206 1796 1488 1777 1477 1477 1612 1816 1631 1631 1821 1194 1827 1827 1620 1620 1832 MH 413 349 365 382 415 323 336 349 436 374 374 400 426 265 434 434 430 299 444 368 439 365 365 399 449 403 403 450 296 451 451 400 400 452 HL INC/DEC Phase Change HM (ns) 0.20 0.21 0.20 0.20 0.20 0.20 0.20 0.20 0.19 0.21 0.21 0.20 0.20 0.21 0.19 0.19 0.20 0.20 0.19 0.21 0.18 0.20 0.20 0.20 0.19 0.20 0.20 0.20 0.20 0.19 0.19 0.20 0.20 0.20 206 103 174 182 190 161 167 174 187 187 200 132 87 91 95 80 83 87 93 93 99 66 207 103 217 108 213 106 216 108 216 108 214 107 149 221 183 182 182 199 224 74 110 91 91 91 99 111 219 109 201 100 201 100 224 147 225 225 200 200 225 112 73 112 112 99 99 112 Note: For BWSEL[1:0] settings LL, LM, HH are reserved. 18 Preliminary Rev. 0.15 S i5317 Table 8. Look-up Tables for Fin = Fout Frequency Range and Loop Bandwidth Settings Frequency Range (MHz) Plan FRQTBL FRQSEL No [3:0] 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M LHML LHMM LHMH LHHL LHHM LHHH MLLL MLLM MLLH MLML MLMM MLMH MLHL MLHM MLHH MMLL MMLM MMLH MMML MMMM MMMH MMHL MMHM MMHH MHLL MHLM MHLH MHML MHMM MHMH MHHL MHHH HLLL HLLM Min 35.00 36.00 37.00 38.00 39.00 40.00 43.30 44.00 46.00 48.00 50.52 52.00 54.00 56.00 58.00 60.00 62.00 64.00 66.00 68.00 70.00 72.00 75.78 76.00 78.00 80.00 84.00 88.00 90.00 92.00 Center 36.00 37.00 38.00 39.00 40.00 42.00 44.00 46.00 48.00 50.00 52.00 54.00 56.00 58.00 60.00 62.00 64.00 66.00 68.00 70.00 72.00 74.00 76.00 78.00 80.00 84.00 88.00 90.00 92.00 Max 37.00 38.00 39.00 40.00 42.00 44.00 46.00 48.00 50.00 52.00 54.00 56.00 58.00 60.00 60.00 64.00 66.00 68.00 70.00 70.88 74.00 76.00 78.00 80.00 84.00 88.00 88.59 92.00 96.00 LH — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — BWSEL [1:0] (BW in Hz) ML 7680 7539 7658 7607 7607 5709 7653 7653 6155 7630 7692 7880 6169 7664 7664 7882 7890 7878 7878 6228 7888 7889 7917 7895 7895 6010 6010 6329 7878 7795 7795 7903 7812 6329 7820 MM 1833 1803 1827 1818 1818 1373 1828 1828 1477 1823 1832 1882 1481 1826 1826 1882 1883 1882 1882 1494 1883 1883 1884 1883 1883 1445 1445 1518 1882 1864 1864 1884 1866 1518 1867 MH 453 446 451 449 449 340 452 452 365 450 452 465 366 451 451 465 465 465 465 369 465 465 465 465 465 357 357 375 465 461 461 465 461 375 461 HL 226 222 225 224 224 169 225 225 182 225 225 232 183 225 225 232 232 232 232 184 232 232 232 232 232 178 178 187 232 230 230 232 230 187 230 INC/DEC Phase Change HM (ns) 113 111 112 112 112 84 112 112 91 112 112 116 91 112 112 116 116 116 116 92 116 116 116 116 116 89 89 93 116 114 114 116 115 93 115 0.19 0.18 0.19 0.18 0.18 0.21 0.18 0.18 0.20 0.18 0.20 0.18 0.20 0.20 0.20 0.18 0.18 0.18 0.18 0.20 0.18 0.18 0.20 0.19 0.19 0.20 0.20 0.20 0.18 0.18 0.18 0.19 0.18 0.20 0.18 96.00 100.00 96.00 100.00 105.00 105.00 110.00 115.00 110.00 115.00 118.13 115.00 120.00 125.00 MHHM 101.04 105.00 110.00 Note: For BWSEL[1:0] settings LL, LM, HH are reserved. Preliminary Rev. 0.15 19 S i5317 Table 8. Look-up Tables for Fin = Fout Frequency Range and Loop Bandwidth Settings Frequency Range (MHz) Plan FRQTBL FRQSEL No [3:0] 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 M M M M M M M M M M M M M M M M M M M M M M M M M H H H H H H H H H HLLH HLML HLMM HLMH HLHL HLHM HLHH HMLL HMLM HMLH HMML Min Center Max LH — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — BWSEL [1:0] (BW in Hz) ML 7812 7878 6873 7851 7826 7240 7853 7890 7831 7831 6912 7140 7846 7878 7878 6993 7903 7069 7903 7507 7910 7878 7429 7908 7879 7571 7903 7890 7878 7878 7344 7900 7889 7878 MM 1868 1882 1648 1871 1870 1735 1872 1883 1871 1871 1654 1710 1873 1882 1882 1673 1884 1689 1884 1793 1884 1882 1776 1884 1882 1811 1884 1883 1882 1882 1757 1883 1883 1882 MH 462 465 408 462 462 429 462 465 462 462 409 423 463 465 465 414 465 417 465 443 465 465 439 465 465 448 465 465 465 465 434 465 465 465 HL 230 232 230 230 230 232 231 231 211 231 232 232 232 232 221 232 232 232 232 223 232 232 232 232 232 232 232 INC/DEC Phase Change HM (ns) 115 116 115 115 115 116 115 115 105 115 116 116 116 116 110 116 116 116 116 111 116 116 116 116 116 116 116 0.18 0.18 0.19 0.19 0.18 0.18 0.19 0.18 0.18 0.18 0.20 0.19 0.18 0.18 0.18 0.19 0.19 0.20 0.19 0.19 0.19 0.18 0.19 0.19 0.18 0.18 0.19 0.18 0.18 0.18 0.18 0.19 0.18 0.18 120.00 125.00 130.00 125.00 130.00 135.00 130.00 135.00 140.00 135.00 140.00 145.00 140.00 145.00 150.00 145.00 150.00 155.00 151.56 155.00 160.00 155.00 160.00 165.00 160.00 165.00 170.00 165.00 170.00 175.00 170.00 175.00 177.19 203 101 214 107 204 102 HMMM 175.00 180.00 185.00 HMMH 180.00 185.00 190.00 HMHL HMHH HHLL HHLM HHLH HHML HHMH HHHL HHHM HHHH LLLL LLLM LLLH LLML LLMM LLMH LLHL LLHM LLHH 185.00 190.00 195.00 195.00 200.00 202.50 202.08 210.00 220.00 210.00 220.00 230.00 220.45 230.00 240.00 230.00 240.00 250.00 250.00 260.00 270.00 260.00 270.00 280.00 270.00 280.00 290.00 280.00 290.00 300.00 290.00 300.00 310.00 303.13 310.00 320.00 310.00 320.00 330.00 320.00 330.00 340.00 330.00 340.00 350.00 340.00 350.00 354.38 350.00 360.00 370.00 360.00 370.00 380.00 370.00 380.00 390.00 HMHM 190.00 195.00 200.00 206 103 208 104 HHMM 242.50 250.00 260.00 219 109 217 108 Note: For BWSEL[1:0] settings LL, LM, HH are reserved. 20 Preliminary Rev. 0.15 S i5317 Table 8. Look-up Tables for Fin = Fout Frequency Range and Loop Bandwidth Settings Frequency Range (MHz) Plan FRQTBL FRQSEL No [3:0] 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 H H H H H H H H H H H H H H H H H H LMLL LMLM LMLH LMML LMMM LMMH LMHL LMHM LMHH LHLL LHLM LHLH LHML LHMM LHMH LHHL LHHM LHHH Min Center Max LH — — — — — — — — — — — — — — — — — — BWSEL [1:0] (BW in Hz) ML 7878 7755 7903 7848 7903 7507 7910 7878 7704 7908 7879 7571 7903 7890 7878 7878 7831 7908 MM 1882 1854 1884 1874 1884 1793 1884 1882 1842 1884 1882 1811 1884 1883 1882 1882 1871 1880 MH 465 458 465 463 465 443 465 465 455 465 465 448 465 465 465 465 462 464 HL 232 228 232 231 232 221 232 232 227 232 232 223 232 232 232 232 231 231 INC/DEC Phase Change HM (ns) 116 114 116 115 116 110 116 116 113 116 116 111 116 116 116 116 115 115 0.18 0.18 0.19 0.18 0.19 0.19 0.19 0.18 0.18 0.19 0.18 0.18 0.19 0.18 0.18 0.18 0.18 0.20 380.00 390.00 400.00 390.00 400.00 405.00 404.17 420.00 440.00 420.00 440.00 460.00 440.91 460.00 480.00 460.00 480.00 500.00 485.00 500.00 520.00 500.00 520.00 540.00 520.00 540.00 560.00 540.00 560.00 580.00 560.00 580.00 600.00 580.00 600.00 620.00 606.25 620.00 640.00 620.00 640.00 660.00 640.00 660.00 680.00 660.00 680.00 700.00 680.00 700.00 704.00 700.00 710.00 710.00 Note: For BWSEL[1:0] settings LL, LM, HH are reserved. Preliminary Rev. 0.15 21 S i5317 3.3. PLL Self-Calibration An internal self-calibration (ICAL) is performed before operation to optimize loop parameters and jitter performance. While the self-calibration is being performed, the DSPLL is being internally controlled by the selfcalibration state machine. The LOL alarm will be active during ICAL. The self-calibration time tLOCKHW is given in Table 4, “AC Characteristics”. Any of the following events will trigger a self-calibration: Power-on-reset (POR)  Release of the external reset pin RST (transition of RST from 0 to 1)  Change in FRQSEL, FRQTBL, BWSEL, or RATE[1:0] pins  Internal DSPLL registers out-of-range, indicating the need to relock the DSPLL In any of the above cases, an ICAL will be initiated if a valid input clock exists with no input alarm. The external crystal or reference clock must also be present for the self-calibration to begin. If no valid input clock is present, the self-calibration state machine will wait until it appears, at which time the calibration will start. After a successful ICAL has been performed with a valid input clock, no subsequent self-calibrations are performed unless one of the above conditions are met. If the input clock is lost following self-calibration, the device enters VCO freeze mode. When the input clock returns, the device relocks to the input clock without performing a selfcalibration. 3.3.1. Input Clock Stability during Internal Self-Calibration An exit from reset must occur when the selected CKIN clock is stable in frequency with a frequency value that is within the device operating range. 3.3.2. Self-Calibration caused by Changes in Input Frequency If the selected CKIN frequency varies by 500 ppm or more within the frequency range defined by FRQSEL and FRQTBL since the last calibration, the device may initiate a self-calibration. 3.3.3. Device Reset Upon powerup, the device internally executes a power-on-reset (POR) which resets the internal device logic. The pin RST can also be used to initiate a reset. The device stays in this state until a valid CKINn is present, when it then performs a PLL self-calibration (refer to section 3.3. "PLL Self-Calibration”). 3.3.4. Recommended Reset Guidelines Follow the recommended RESET guidelines in Table 9 that describe when reset should be applied to a device.  Table 9. Si5317 Pins and Reset Pin # 2 11 15 22 23 24 25 26 27 Si5317 Pin Name FRQTBL RATE0 RATE1 BWSEL0 BWSEL1 FRQSEL0 FRQSEL1 FRQSEL2 FRQSEL3 Must Reset after Changing Yes Yes Yes Yes Yes Yes Yes Yes Yes 22 Preliminary Rev. 0.15 S i5317 3.4. Alarms Summary alarms are available to indicate the overall status of the input signals. Alarm outputs stay high until all the alarm conditions for that alarm output are cleared. 3.4.1. Loss-of-Signal The device has loss-of-signal circuitry that continuously monitors CKIN for missing pulses. An LOS condition on CKIN causes the LOS alarm to become active. Once a LOS alarm is asserted, it remains asserted until the input clock is validated over a designated time period. The time to clear LOS after a valid input clock appears is listed in Table 4, “AC Characteristics”. If another error condition on the same input clock is detected during the validation time, then the alarm remains asserted and the validation time starts over. 3.4.1.1. LOS Algorithm The LOS circuitry divides down each input clock to produce an 8 kHz to 2 MHz signal. The LOS circuitry oversamples this divided down input clock using a 40 MHz clock to search for extended periods of time without input clock transitions. If the LOS monitor detects twice the normal number of samples without a clock edge, a LOS alarm is declared. Table 4, “AC Characteristics” gives the minimum and maximum amount of time for the LOS monitor to trigger. 3.4.1.2. Lock Detect The PLL lock detection algorithm indicates the lock status on the LOL output pin. The algorithm works by continuously monitoring the phase of the input clock in relation to the phase of the feedback clock. If the time between two consecutive phase cycle slips is greater than the retrigger time, the PLL is in lock. The LOL output has a guaranteed minimum pulse width as shown in Table 4, “AC Characteristics”. The LOL pin is also held in the active state during an internal PLL calibration. The retrigger time is automatically set based on the PLL closed loop bandwidth (see Table 10). Table 10. Lock Detect Retrigger Time PLL Bandwidth Setting (BW) 60–120 Hz 120–240 Hz 240–480 Hz 480–960 Hz 960–1920 Hz 1920–3840 Hz 3840–7680 Hz Retrigger Time (ms) 53 26.5 13.3 6.6 3.3 1.66 0.833 3.5. VCO Freeze The Si5317 device features a VCO freeze mode whereby the DSPLL is locked to a frequency value. If an LOS condition exists on the selected input clock, the device freezes the VCO. In this mode, the device provides a stable output frequency until the input clock returns and is validated. When the device enters VCO freeze, the internal oscillator is initially held to its last frequency value. 3.5.1. Recovery from VCO Freeze When the input clock signal returns, the device transitions from VCO freeze to the selected input clock. Preliminary Rev. 0.15 23 S i5317 3.6. PLL Bypass Mode The Si5317 supports a PLL bypass mode in which the selected input clock is fed directly to both enabled output buffers, bypassing the DSPLL. Internally, the bypass path is implemented with high-speed differential signaling; however, this path is not a low jitter path and will see significantly higher jitter on CKOUT. In PLL bypass mode, the input and output clocks will be at the same frequency. PLL bypass mode is useful in a laboratory environment to measure system performance with and without the jitter attenuation provided by the DSPLL. The DSBL2_BY pin is used to select the PLL Bypass Mode according to Table 11. Table 11. DSBL2/BYPASS Pin Settings DSBL2/BYPASS L M H Function CKOUT2 Enabled CKOUT2 Disabled PLL Bypass Mode w/ CKOUT2 Enabled External Crystal or Reference Clock RATE[1:0] XB XA PLL Bypass 0 2 CKOUT+ CKOUT– SFOUT[1:0] CKIN+ CKIN– 2 f3 DSPLL® fOSC 1 0 2 LOS LOL RST BWSEL[1:0] FRQSEL[3:0] FRQTBL INC DEC Alarms 1 CKOUT+ CKOUT– Control Bandwidth Control Frequency Control Skew Control Voltage Regulator with High PSRR DBL2_BY VDD (1.8, 2.5, or 3.3 V) GND Figure 6. Bypass Signal 24 Preliminary Rev. 0.15 S i5317 4. High-Speed I/O 4.1. Input Clock Buffer The Si5317 provides differential inputs for the CKIN clock input. This input is internally biased to a common mode voltage (see Table 2, “DC Characteristics”) and can be driven by either a single-ended or differential source. No additional external bias is required. Figure 7 through Figure 10 shows typical interface circuits for LVPECL, CML, LVDS, or CMOS input clocks. Note that the jitter generation improves for higher levels on CKINn within the limits in Table 4, “AC Characteristics”. AC coupling the input clocks is recommended because it removes any issue with common mode input voltages. However, either ac or dc coupling is acceptable. Figure 7 and Figure 8 shows various examples of different input termination arrangements. Unused inputs can be left unconnected. 3.3 V Si5317 130  130  C CKIN + 40 k  LVPECL Driver 40 k  CKIN 82  82  C _ 300  ± VICM Figure 7. Differential LVPECL Termination 3.3 V Si5317 130  Driver 40 k  C CKIN + 300  40 k  CKIN _ 82  C ± VICM Figure 8. Single-ended LVPECL Termination Preliminary Rev. 0.15 25 S i5317 Si5317 C CKIN + CML/ LVDS Driver 40 k 100  40 k CKIN _ C 300  ± VICM Figure 9. CML/LVDS Termination (1.8, 2.5, 3.3 V) V DD V DD 39  CMOS Driver 40 k  Si5317 CKIN + 300  40 k  CKIN 0.1 uF _ ± V ICM Figure 10. CMOS Termination (1.8, 2.5, 3.3 V) 26 Preliminary Rev. 0.15 S i5317 50 1. Attenuation circuit limits overshoot and undershoot. 2. Not to be used with non-square wave input clocks. Figure 11. CMOS Termination with Attenuation and AC-coupling (1.8, 2.5, 3.3 V) Preliminary Rev. 0.15 27 S i5317 4.2. Output Clock Driver The Si5317 has a flexible output driver structure that can drive a variety of loads, including LVPECL, LVDS, CML, and CMOS formats. The signal format is selected for CKOUT output using the SFOUT [1:0] pins. This modifies the output common mode and differential signal swing. See Table 2, “DC Characteristics” for output driver specifications. The SFOUT [1:0] pins are three-level input pins with the states designated as L (ground), M (VDD/2), and H (VDD). Table 12 shows the signal formats based on the supply voltage and the type of load being driven. Table 12. Output Signal Format Selection (SFOUT) SFOUT[1:0] HL HM LH LM MH ML All Others Signal Format CML LVDS CMOS Disabled LVPECL Low-swing LVDS Reserved Si5317 Z0 = 50  100  Z0 = 50  Rcvr CKOUTn Figure 12. Typical Differential Output Circuit Si5317 CMOS Logic CKOUTn Optionally Tie CKOUTn Outputs Together for Greater Strength Figure 13. Typical CMOS Output Circuit (Tie CKOUTn+ and CKOUTn– Together) For the CMOS setting (SFOUT = LH), both output pins drive single-ended in-phase signals and should be externally shorted together to obtain the drive strength specified in Table 2, “DC Characteristics”. 28 Preliminary Rev. 0.15 S i5317 + SFOUT[1:0] = ML (Output disable) 100  100  CKOUT Output from DSPLL Figure 14. Disable CKOUT Structure The SFOUT [1:0] pins can also be used to disable both outputs. Disabling the output puts the CKOUT+ and CKOUT– pins in a high-impedance state relative to VDD (common mode tri-state) while the two outputs remain connected to each other through a 200  on-chip resistance (differential impedance of 200 ). The maximum amount of internal circuitry is powered down, minimizing power consumption and noise generation (see Figure 14). Recovery from the disable mode requires additional time as specified in Table 4, “AC Characteristics”. Preliminary Rev. 0.15 29 S i5317 5. Crystal/Reference Clock Input The device can use an external crystal or external clock as a reference. If an external clock is used, it must be ac coupled. With appropriate buffers, the same external reference clock can be applied to CKIN. Although the reference clock input can be driven single ended (See Figure 15), the best performance is with a crystal or differential clock source. 3.3 V 3.3 V 130  150  0.1 F XA 150  0.1 F XB Si5317 10 k 0.6 V CMOS buffer, 8 mA output current For 2.5 V operation, change 130  to 82 . Figure 15. CMOS External Reference Circuit 0 dBm into 50  0.01  F 0.01 F E xternal Clock Source 50  Si5317 XA 10 pF XB 0.1 µF 10 k 0.6 V 1.2 V Figure 16. Sinewave External Reference Clock Input Example 0.01 F 100  LVPECL, CML, etc. 0.01 F Si5317 XA 1.2 V XB 10 k 10 k 0.6 V Figure 17. Differential External Reference Clock Input Example 30 Preliminary Rev. 0.15 S i5317 5.1. Crystal/Reference Clock Selection An external low-jitter clock or a low-cost crystal is used as part of a fixed-frequency oscillator within the DSPLL. This external clock is required for the device to perform jitter attenuation. Silicon Laboratories recommends using a high-quality crystal. In VCO freeze, the DSPLL remains locked to this external clock. Any changes in the frequency of this clock when the DSPLL is in VCO freeze will be tracked by the output of the device. Note that crystals can have temperature sensitivities. Table 13 shows the recommended crystals. Table 13. Approved Crystals Manufacturer TXC Connor Winfield Connor Winfield NDK NDK Siward Saronix/eCera Mtron Part Number 7MA1400014 CS-018-114.285M CS-023-114.285M NX3225SA EXS00A-CS00871 NX3225SA EXS00A-CS00997 XTL573200NLG114.285 MHz-OR FLB420001 M1253S071 Web Address http://www.txc.com.tw http://www.conwin.com http://www.conwin.com http://www.ndk.com/en/ http://www.ndk.com/en/ http://www.siward.com http://www.pericom.com/saronix http://www.mtronpti.com Stability 100 ppm 100 ppm 20 ppm 100 ppm 20 ppm 20 ppm 100 ppm 100 ppm Initial Accuracy 100 ppm 100 ppm 20 ppm 100 ppm 20 ppm 20 ppm 100 ppm 100 ppm Note: While these crystals meet the preceding criteria according to their data sheets, Silicon Laboratories, Inc. does not guarantee operation with the Si5317, nor does Silicon Laboratories endorse one supplier of crystals over another. Contact Silicon Labs for details and a current list of crystal vendors and recommended part numbers. Preliminary Rev. 0.15 31 S i5317 Table 14. XA/XB Reference Sources and Frequencies RATE[1:0] HH HM HL MH MM ML LH LM LL Type Reserved External clock Reserved External clock 3rd overtone crystal External clock Reserved External clock Reserved Recommended — 171.4275 MHz — 114.285 MHz 114.285 MHz 57.1425 MHz — 38.88 MHz — Lower limit — 163 MHz — 109 MHz — 55 MHz — 37 MHz — Upper limit — 180 MHz — 125.5 MHz — 61 MHz — 41 MHz — Because the crystal is used as a jitter reference, rapid changes of the crystal temperature can temporarily disturb the output phase and frequency. For example, it is recommended that the crystal not be placed close to a fan that is being turned off and on. If a situation such as this is unavoidable, the crystal should be thermally isolated with an insulating cover. 5.1.1. XA/XB Clock Drift During VCO freeze, long-term and temperature-related drift of the XA/XB clock input results in a one-to-one drift of the output frequency. The stability of the any frequency output is identical to the drift of the XA/XB frequency. This means that for the most demanding applications where the drift of a crystal is not acceptable, an external temperature-compensated or ovenized oscillator will be required. Drift is not an issue unless the part is in VCO freeze. Also, the initial accuracy of the XA/XB oscillator (or crystal) is not relevant. 5.1.2. XA/XB Jitter Jitter on the XA/XB input has a roughly one-to-one transfer function to the output jitter over the bandwidth ranging from 100 Hz up to 30 kHz. If a crystal is used on the XA/XB pins, this will have low jitter if a suitable crystal is in use. If the XA/XB pins are connected to an external oscillator, the jitter of the external oscillator may contribute significantly to the output jitter. 32 Preliminary Rev. 0.15 S i5317 5.1.3. Jitter Attenuation Performance The internal VCO uses the XA/XB clock on the XA/XB pins as its reference for jitter attenuation. The XA/XB pins support either a crystal input or an input buffer single-ended or differential clock input, such that an external oscillator can become the reference source. In either case, the device accepts a wide margin in absolute frequency of the XA/XB input (refer to section 3.5.1. "Recovery from VCO Freeze" on page 23). In VCO freeze, the Si5317's output clock stability matches the clock supplied on the XA/XB pins. The external crystal or clock must be selected based on the stability requirements of the application if VCO freeze is a key requirement. However, care must be exercised in certain areas for optimum performance. For examples of connections to the XA/XB pins, refer to section 5. Figure 23, “Si5317 Typical Application Circuit,” on page 37. Jitter Transfer XA/XB Reference to CKOUT 38.88 MHz Clock on XA/XB, RATE[1:0]=LM 5 0 -5 Jitter Transfer (dB) -10 -15 -20 -25 -30 1 10 100 1000 10000 100000 1000000 Jitter Frequency (Hz) Figure 18. Typical XA-XB Jitter Transfer Function Preliminary Rev. 0.15 33 S i5317 5.1.4. Reference Clock Frequency Based on the application and desired output frequency, care should be exercised in selecting the frequency on the reference used for XA/XB. When the CKOUT operating frequency is close to having a simple integer relationship, significant spurs can occur. For example, compare the spurs when the CKOUT operating frequency is 622.08 MHz with a reference of 114.285 MHz (see Figure 22) versus a reference frequency of 38.88 MHz, which is 16 times the XA/XB reference (see Figure 19). Figure 19. Effect of Reference Frequency on Spurs 34 Preliminary Rev. 0.15 S i5317 6. Power Supply Filtering This device incorporates an on-chip voltage regulator to power the device from supply voltages of 1.8, 2.5, or 3.3 V. Internal core circuitry is driven from the output of this regulator while I/O circuitry uses the external supply voltage directly. Table 4, “AC Characteristics” gives the sensitivity of the on-chip oscillator to changes in the supply voltage. The center ground pad under the device must be electrically and thermally connected to the ground plane. See Figure 26, “Ground Pad Recommended Layout,” on page 45. 0.1 uF System Power Supply (1.8, 2.5, or 3.3 V) C1 – C3 Ferrite Bead 1.0 uF C4 VDD GND & GND Pad Si5317 Figure 20. Typical Power Supply Bypass Network Power Supply Noise to Output Transfer Function -60 Power Supply Noise Rejection Ratio (dB) -65 -70 -75 -80 -85 -90 -95 -100 -105 1 10 100 1000 Frequency of Power Supply Noise (kHz) Figure 21. Fin = Fout = 155 MHz with 120 Hz Loop Bandwidth, 100 mV, pk-pk Supply Noise Preliminary Rev. 0.15 35 S i5317 7. Typical Phase Noise Plots The following is a typical phase noise plot. The clock input source was a Rohde and Schwarz model SML03 RF Generator. The phase noise analyzer was an Agilent model E5052B. The Si5317 operates at 3.3 V with an ac coupled differential PECL output and an ac coupled differential sine wave input from the RF generator at 0 dBm. Note that, as with any PLL, the output jitter that is below the loop BW is caused by the jitter at the input clock. The loop BW was 120 Hz. 7.1. Example: SONET OC-192 Figure 22. Typical Phase Noise Plot Jitter Band SONET_OC48, 12 kHz to 20 MHz SONET_OC192_A, 20 kHz to 80 MHz SONET_OC192_B, 4 to 80 MHz SONET_OC192_C, 50 kHz to 80 MHz Brick Wall, 800 Hz to 80 MHz Jitter, RMS 250 fs 274 fs 166 fs 267 fs 274 fs 36 Preliminary Rev. 0.15 S i5317 8. Typical Application Circuit C4 1 µF System Power Supply C3 0.1 µF Ferrite Bead C2 0.1 µF C1 0.1 µF GND Pad GND VDD 0.1 µF CKOUT1+ 100  CKOUT1– 0.1 µF – + Clock Outputs VDD = 3.3 V 130  130  VDD CKIN+ Input Clock1 CKIN– 82  82  CKOUT2+ SFOUT[1:0]2 15 k Signal Format Select 15 k 0.1 µF 100  CKOUT2– LOS LOL CKIN Loss of Signal Indicator PLL Loss of Lock Indicator Option 1: Crystal XA XB Option 2: Ext. Refclk+ Ext. Refclk– 0.1 µF XA 0.1 µF XB VDD 15 k Si5317 Crystal/Ref Clk 15 k RATE[1:0]2 VDD Frequency Table FRQTBL3 VDD 15 k Frequency Select VDD 15 k 15 k FRQSEL[3:0]2 BWSEL[1:0]2 INC DEC DBL2_BY2 RST Bandwidth Select 15 k Skew Increment Skew Decrement Clock Output 2 Disable/ Bypass Mode Control Reset Notes: 1. Assumes differential LVPECL termination (3.3 V) on clock inputs. 2. Denotes tri-level input pins with states designated as L (ground), M (VDD/2), and H (VDD). 3. For schematic and layout examples, refer to Si5317-EVB User Manual. Figure 23. Si5317 Typical Application Circuit Preliminary Rev. 0.15 37 S i5317 9. Pin Descriptions: Si5317 CKOUT1– CKOUT2+ CKOUT2SFOUT0 GND CKOUT1+ 27 FRQSEL3 26 FRQSEL2 25 FRQSEL1 24 FRQSEL0 23 BWSEL1 22 BWSEL0 21 NC 20 DEC 19 INC 10 11 12 13 14 15 16 17 18 RATE0 DBL2_BY RATE1 CKIN+ CKIN– VDD LOL NC NC SFOUT1 VDD 36 35 34 33 32 31 30 29 28 RST FRQTBL LOS NC VDD XA XB GND NC 1 2 3 4 5 6 7 8 9 NC GND Pad Note: Pin assignments are preliminary and subject to change. Table 15. Si5317 Pin Descriptions Pin # 1 Pin Name RST I/O I Signal Level Description LVCMOS External Reset. Active low input that performs external hardware reset of device. Resets all internal logic to a known state. Clock outputs are tristated during reset. After rising edge of RST signal, the Si5317 will perform an internal self-calibration when a valid input signal is present. This pin has a weak pull-up. 3-level Frequency Table. Selects frequency table. This pin has a weak pull-up and weak pull-down and defaults to M. Some designs may require an external resistor voltage divider when driven by an active device that will tri-state. LVCMOS CKIN Loss of Signal. Active high loss-of-signal indicator for CKIN. Once triggered, the alarm will remain active until CKIN is validated. 0 = CKIN present 1 = LOS on CKIN Supply Supply. The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass capacitors should be associated with the following VDD pins: 5 0.1 µF 10 0.1 µF 32 0.1 µF A 1.0 µF should also be placed as close to device as is practical. 2 FRQTBL I 3 LOS O 5, 10, 32 VDD VDD 38 Preliminary Rev. 0.15 S i5317 Table 15. Si5317 Pin Descriptions (Continued) Pin # 7 6 Pin Name XB XA Signal Level Description Analog External Crystal or Reference Clock. External crystal should be connected to these pins to use internal oscillator-based reference. Crystal or reference clock selection is set by the XTAL/CLOCK pin. GND Supply Ground. Must be connected to system ground. Minimize the ground path impedance for optimal performance of this device. I 3-Level External Crystal or Reference Clock Rate. Note: L setting corresponds to ground. M setting corresponds to VDD/2. H setting corresponds to VDD. Some designs may require an external resistor voltage divider when driven by an active device that will tri-state. See Table 14 for settings. I/O I 8,31 GND 11 15 RATE0 RATE1 14 DBL2_BY I 3-Level 16 17 CKIN+ CKIN– I Multi 18 LOL O LVCMOS 19 DEC I LVCMOS 20 INC I LVCMOS Output 2 Disable/Bypass Mode Control. Controls enable of CKOUT2 divider/output buffer path and PLL bypass mode. L = CKOUT2 enabled M = CKOUT2 disabled H = Bypass mode with CKOUT2 enabled This pin has a weak pull-up and weak pull-down and defaults to M. Some designs may require an external resistor voltage divider when driven by an active device that will tri-state. Clock Input. Differential input clock. This input can also be driven with a single-ended signal. Input frequency selected from Table 9 on page 22. PLL Loss of Lock Indicator. This pin functions as the active high PLL loss of lock indicator. 0 = PLL locked 1 = PLL unlocked Skew Decrement. This edge-triggered pin decreases the input to output device skew. There is no limit on the range of skew adjustment by this method. Detailed operations and timing characteristics for this pin are found in Section 3.2, Table 8. This pin has a weak pull-down. Skew Increment. This edge-triggered pin increases the input to output device skew. There is no limit on the range of skew adjustment by this method. Detailed operations and timing characteristics for this pin are found in Section 3.2, Table 8. This pin has a weak pull-down. Preliminary Rev. 0.15 39 S i5317 Table 15. Si5317 Pin Descriptions (Continued) Pin # 23 22 Pin Name BWSEL1 BWSEL0 I/O I Signal Level Description 3-Level Loop Bandwidth Select. Three level inputs that select the DSPLL closed loop bandwidth. See Table 9 on page 22 for available settings. These pins have both weak pull-ups and weak pull-downs and default to M. Some designs may require an external resistor voltage divider when driven by an active device that will tri-state. Frequency Select. Three level inputs that select the input clock and clock range. See Table 9 on page 22. These pins have both weak pull-ups and weak pull-downs and default to M. Some designs may require an external resistor voltage divider when driven by an active device that will tri-state. Multi Clock Output 1. Output signal format is selected by SFOUT pins. Differential formats supported for LVPECL, LVDS, and CML compatible modes. For single-ended CMOS format, both output pins drive identical, in-phase clock outputs. 3-Level Signal Format Select. Three-level inputs that select the output signal format (common mode voltage and differential swing) for both CKOUT1 and CKOUT2. SFOUT[1:0] HH HM HL MH MM ML LH LM LL Signal Format Reserved LVDS CML LVPECL Reserved LVDS—Low Swing CMOS Disable Reserved 27 26 25 24 FRQSEL3 FRQSEL2 FRQSEL1 FRQSEL0 29 28 CKOUT1– CKOUT1+ O 33 30 SFOUT0 SFOUT1 I 34 35 CKOUT2– CKOUT2+ O Multi These pins have both weak pull-ups and weak pull-downs and default to M. Some designs may require an external resistor voltage divider when driven by an active device that will tri-state.* Clock Output 2. Output signal format is selected by SFOUT pins. Differential formats supported for LVPECL, LVDS, and CML compatible modes. For single-ended CMOS format, both output pins drive identical, in-phase clock outputs. 40 Preliminary Rev. 0.15 S i5317 Table 15. Si5317 Pin Descriptions (Continued) Pin # 4,9,12,13, 21,36 GND PAD Pin Name NC Signal Level Description — No Connect. Leave floating. Make no external connections to this pin for normal operation. GND Supply Ground Pad. The ground pad must provide a low thermal and electrical impedance to a ground plane. I/O — GND *Note: LVPECL requires VDD > 2.25 V Preliminary Rev. 0.15 41 S i5317 Table 16. Si5317 Pull-Up/-Down Pin # 1 2 11 15 22 23 24 25 26 27 30 33 Si5317 RST FRQTBL RATE0 RATE1 BWSEL0 BWSEL1 FRQSEL0 FRQSEL1 FRQSEL2 FRQSEL3 SFOUT1 SFOUT0 Pull? U U, D U, D U, D U, D U, D U, D U, D U, D U, D U, D U, D 42 Preliminary Rev. 0.15 S i5317 10. Ordering Guide Ordering Part Number Output Clock Freq Range Si5317A-C-GM Si5317B-C-GM Si5317C-C-GM Si5317D-C-GM Si5317-EVB 1–710 MHz 1–350 MHz 1–200 MHz 1–100 MHz 1–710 MHz Device Pkg 36-Lead 6 x 6 mm QFN 36-Lead 6 x 6 mm QFN 36-Lead 6 x 6 mm QFN 36-Lead 6 x 6 mm QFN Evaluation Board ROHS6, Pb-Free Yes Yes Yes Yes — Temp Range –40 to 85 °C –40 to 85 °C –40 to 85 °C –40 to 85 °C — Note: Add an “R” at the end of the device to denote tape and reel options (i.e., Si5317A-C-GMR). Table 17. DSPLL Precision Clock Product Selection Guide Part Number Control Clock Inputs/ Outputs 2/2 Input Frequency (MHz) 0.008 to 644 Output Frequency (MHz) 0.008 to 644 Jitter (12 kHz to 20 MHz) PLL Bandwidth Hitless Switching Digital Hold Freerun VCO Freeze Signal Format Package Si5315 Pin 450 fs ms typ 60 Hz to 8.4 kHz 60 Hz to 8.4 kHz 60 Hz to 8.4 kHz 60 Hz to 8.4 kHz 30 kHz to 1.3 MHz 60 Hz to 8.4 kHz 4 to 525 Hz 30 kHz to 1.3 MHz 60 Hz to 8.4 kHz 30 kHz to 1.3 MHz 60 Hz to 8.4 kHz 30 kHz to 1.3 MHz 60 Hz to 8.4 kHz        36-QFN Si5316 Pin 2/1 19 to 710 19 to 710 300 fs ms typ 36-QFN Si5317 Pin I2C / SPI 1/2 1 to 710 1 to 710 300 fs ms typ 36-QFN Si5319 1/1 0.002 to 710 0.002 to 1417 300 fs ms typ 36-QFN Si5322 Pin 2/2 19 to 707 19 to 1050 600 fs ms typ 36-QFN Si5323 Pin I2C / SPI I2C/ SPI I2C / SPI 2/2 0.008 to 707 0.008 to 1050 300 fs ms typ       CMOS, LVDS, LVPECL, CML 36-QFN Si5324 Si5325 2/2 2/2 0.002 to 710 10 to 710 0.002 to 1417 10 to 1417 290 fs ms typ 600 fs ms typ 36-QFN 36-QFN Si5326 2/2 0.002 to 710 0.002 to 1417 300 fs ms typ     36-QFN Si5365 Pin 4/5 19 to 710 19 to 1050 600 fs ms typ 100-TQFP Si5366 Pin I2C / SPI I2C / SPI 4/5 0.008 to 707 0.008 to1050 300 fs ms typ    100-TQFP Si5367 4/5 10 to 710 10 to 1417 600 fs ms typ 100-TQFP Si5368 4/5 0.002 to 710 0.002 to 1417 300 fs ms typ    100-TQFP Preliminary Rev. 0.15 43 S i5317 11. Package Outline: 36-Pin QFN Figure 24 illustrates the package details for the Si5317. Table 18 lists the values for the dimensions shown in the illustration. Figure 24. 36-Pin Quad Flat No-Lead (QFN) Table 18. Package Dimensions Symbol Min A A1 b D D2 e E E2 3.95 3.95 0.80 0.00 0.18 Millimeters Nom 0.85 0.02 0.25 6.00 BSC 4.10 0.50 BSC 6.00 BSC 4.10 4.25 4.25 Max 0.90 0.05 0.30 L  aaa bbb ccc ddd eee Symbol Min 0.50 — — — — — — Millimeters Nom 0.60 — — — — — — Max 0.70 12º 0.10 0.10 0.08 0.10 0.05 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC outline MO-220, variation VJJD. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. 44 Preliminary Rev. 0.15 S i5317 12. Recommended PCB Layout Figure 25. PCB Land Pattern Diagram Figure 26. Ground Pad Recommended Layout Preliminary Rev. 0.15 45 S i5317 Table 19. PCB Land Pattern Dimensions Dimension e E D E2 D2 GE GD X Y ZE ZD — — 4.00 4.00 4.53 4.53 — 0.89 REF. 6.31 6.31 MIN 0.50 BSC. 5.42 REF. 5.42 REF. 4.20 4.20 — — 0.28 MAX Notes (General): 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on IPC-SM-782 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. Notes (Solder Mask Design): 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Notes (Stencil Design): 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 4. A 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the center ground pad. Notes (Card Assembly): 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 46 Preliminary Rev. 0.15 S i5317 13. Si5317 Device Top Mark Si 5317q C - GM Y Y WW R F XXXX q: Speed Code: A, B, C, D C: Product Revision G: Temperature Range –40 to 85 °C M: Package: QFN YY: Year WW: Week R: Die Rev F: Internal SiLabs Code X: Lot Code Preliminary Rev. 0.15 47 S i5317 NOTES: 48 Preliminary Rev. 0.15 S i5317 DOCUMENT CHANGE LIST Revision 0.1 to Revision 0.15           Updated corresponding sections and pinouts to add CKOUT2, INC/DEC, and DBL2_BY functionality. Updated functional block diagram on page 1. Updated Table 2 IDD (DD is subscript). Added Differential Rise/Fall Time spec to Table 2. Updated pin assignment symbol and pin description on page 1 and in section 9 to add CKOUT2, INC/DEC, and DBL2_BY. Added section 3.6. "PLL Bypass Mode”. Updated section 8 diagram to add CKOUT2 and DBL2_BY. Added additional CMOS Termination with attenuation figure. Corrected pin name assignment (pin28) diagram on page 1 and section 9, page 35 to match pin description name. Updated all the frequency plans in Table 8 to provide coverage over the entire frequency range. Material Material Preliminary Rev. 0.15 49 S i5317 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 50 Preliminary Rev. 0.15