TS1103-200EG6

TS1103 A 1µA, 200µVOS Bidirectional Precision Current-Sense Amplifier FEATURES DESCRIPTION ♦ Ultra-Low Supply Current: 1μA ♦ Wide Input Common Mode Range: +2V to +27V ♦ Low Input Offset Voltage: 200μV (max) ♦ Low Gain Error: 0.6% (max) ♦ Voltage Output ♦ Four Gain Options Available: TS1103-25: Gain = 25V/V TS1103-50: Gain = 50V/V TS1103-100: Gain = 100V/V TS1103-200: Gain = 200V/V ♦ 6-Lead SOT23 Packaging The TS1103 is the latest addition to the TS1101 family of bidirectional current-sense amplifiers. Consuming a very low 1μA supply current, the TS1103 high-side current-sense amplifiers combine a 200-µV (max) VOS and a 0.6% (max) gain error for cost-sensitive applications. For all high-side bidirectional current-sensing applications, the TS1103s are self-powered and feature a wide input common-mode voltage range from 2V to 27V. A SIGN comparator digital output is also provided that indicates the direction of current flow depending on the external connections to the TS1103’s RS+ and RS- input terminals. APPLICATIONS Notebook Computers Power Management Systems Portable/Battery-Powered Systems Smart Chargers Smart Phones The SOT23 package makes the TS1103 an ideal choice for pcb-area-critical, supply-current-conscious, high-accuracy current-sense applications in all battery-powered and portable instruments. All TS1103s are specified for operation over the -40°C to +105°C extended temperature range. TYPICAL APPLICATION CIRCUIT SIGN Comparator’s Symmetric ILOAD Crossover PART TS1103-25 TS1103-50 TS1103-100 TS1103-200 GAIN OPTION 25 V/V 50 V/V 100 V/V 200 V/V Page 1 © 2014 Silicon Laboratories, Inc. All rights reserved. TS1103 ABSOLUTE MAXIMUM RATINGS RS+, RS- to GND ..............................................-0.3V to +27V VDD, OUT, SIGN to GND ....................................... -0.3V to +6 RS+ to RS- ..................................................................... ±28V Short-Circuit Duration: OUT to GND .................... Continuous Continuous Input Current (Any Pin) ............................ ±20mA Continuous Power Dissipation (TA = +70°C) 6-Lead SOT23 (Derate at 4.5mW/°C above +70°C) ............................................................................... 360mW Operating Temperature Range .................... -40°C to +105°C Junction Temperature ................................................ +150°C Storage Temperature Range ....................... -65°C to +150°C Lead Temperature (Soldering, 10s) ........................... +300°C Soldering Temperature (Reflow) ............................ +260°C Electrical and thermal stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the specifications is not implied. Exposure to any absolute maximum rating conditions for extended periods may affect device reliability and lifetime. PACKAGE/ORDERING INFORMATION ORDER NUMBER PART MARKING TS1103-25EG6 CARRIER QUANTITY Tape & Reel ----- Tape & Reel 3000 Tape & Reel ----- Tape & Reel 3000 Tape & Reel ----- Tape & Reel 3000 Tape & Reel ----- Tape & Reel 3000 TADW TS1103-25EG6T TS1103-50EG6 TADX TS1103-50EG6T TS1103-100EG6 TADY TS1103-100EG6T TS1103-200EG6 TADZ TS1103-200EG6T Lead-free Program: Silicon Labs supplies only lead-free packaging. Consult Silicon Labs for products specified with wider operating temperature ranges. Page 2 TS1103 Rev. 1.1 TS1103 ELECTRICAL CHARACTERISTICS VRS+ = 3.6V; VSENSE = (VRS+ - VRS-) = 0V; COUT = 47nF; VDD = 1.8V; TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C. See Note 1. PARAMETER Supply Current (Note 2) SYMBOL CONDITIONS TA = +25°C ICC VRS+ = 25V MIN TA = +25°C Common-Mode Input Range VCM Guaranteed by CMRR CURRENT SENSE AMPLIFIER PARAMETERS Common-Mode Rejection Ratio CMRR 2V < VRS+ < 27V TA = +25°C Input Offset Voltage (Note 3) VOS VOS Hysteresis (Note 4) Gain VHYS G Gain Error (Note 5) GE Gain Match (Note 5) GM Output Resistance (Note 6) ROUT OUT Low Voltage VAOL OUT High Voltage (Note 7) VAOH Output Settling Time tS 2 120 VCOL Output High Voltage VCOH Propagation Delay tPD 150 ±30 TA = +25°C TS1103-25 TS1103-50 TS1103-100 TS1103-200 TA = +25°C 10 25 50 100 200 ±0.2 TA = +25°C ±0.2 TS1103-25/50/100 TS1103-200 Gain = 25 Gain = 50 Gain = 100 Gain = 200 VOH = VRS- - VOUT TS1103-25/50/100 TS1103-200 7.0 14.0 10 20 0.05 2.2 4.3 1% final value, VOUT = 3V SIGN COMPARATOR PARAMETERS VDD Supply Voltage Range VDD VDD Supply Current IDD Output Low Voltage TYP 0.68 1.25 0.02 VDD = 1.25V, ISINK = 5µA VDD = 1.8V, ISINK = 35µA VDD = 1.25V, ISOURCE = 5µA VDD = 1.8V, ISOURCE = 35µA VSENSE = ±1mV VSENSE = ±10mV MAX 0.85 1.0 1.0 1.2 27 UNITS μA V dB ±200 ±300 μV µV V/V ±0.6 ±1.0 ±0.6 ±1 13.2 26.4 5 10 20 40 0.2 % % kΩ mV V ms 5.5 0.2 V µA 0.2 V VDD – 0.2 V 3 0.4 ms Note 1: All devices are 100% production tested at TA = +25°C. All temperature limits are guaranteed by product characterization. Note 2: Extrapolated to VOUT = 0. ICC is the total current into the RS+ and the RS- pins. Note 3: Input offset voltage VOS is extrapolated from a VOUT+ measurement with VSENSE set to +1mV and a VOUT- measurement with VSENSE set to -1mV; vis-a-viz, Average VOS = VOUT- - VOUT+ 2 x GAIN Note 4: Amplitude of VSENSE lower or higher than VOS required to cause the comparator to switch output states. Note 5: Gain error applies to current flow in either direction and is calculated by applying two values for VSENSE and then calculating the error of the actual slope vs. the ideal transfer characteristic: For GAIN = 25, the applied VSENSE is 20mV and 120mV. For GAIN = 50, the applied VSENSE is 10mV and 60mV. For GAIN = 100, the applied VSENSE is 5mV and 30mV. For GAIN = 200, the applied VSENSE is 2.5mV and 15mV. Note 6: The device is stable for any capacitive load at VOUT. Note 7: VOH is the voltage from VRS- to VOUT with VSENSE = 3.6V/GAIN. TS1103 Rev. 1.1 Page 3 TS1103 TYPICAL PERFORMANCE CHARACTERISTICS VRS+ = VRS- = 3.6V; TA = +25°C, unless otherwise noted. Gain Error Histogram 35 35 30 30 PERCENT OF UNITS - % PERCENT OF UNITS - % Input Offset Voltage Histogram 25 20 15 10 5 10 20 30 40 50 10 60 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 INPUT OFFSET VOLTAGE - µV GAIN ERROR - % Supply Current vs Temperature Input Offset Voltage vs Common-Mode Voltage 40 INPUT OFFSET VOLTAGE - µV 1 SUPPLY CURENT - µA 15 0 -10 0.8 25V 2V 0.6 3.6V 0.4 0.2 0 35 30 25 20 -40 -15 10 35 60 85 110 0 5 10 15 20 25 30 TEMPERATURE - °C SUPPLY VOLTAGE - Volt Input Offset Voltage vs Temperature Supply Current vs Common-Mode Voltage 80 1 60 SUPPLY CURRENT - µA INPUT OFFSET VOLTAGE - µV 20 5 0 40 20 0 -20 -40 0.8 0.6 0.4 0.2 0 -40 -15 10 35 60 TEMPERATURE - °C Page 4 25 85 110 0 5 10 15 20 25 30 SUPPLY VOLTAGE - Volt TS1103 Rev. 1.1 TS1103 TYPICAL PERFORMANCE CHARACTERISTICS VRS+ = VRS- = 3.6V; TA = +25°C, unless otherwise noted. Gain Error vs. Temperature Gain Error vs Common-Mode Voltage 0.4 0.3 GAIN ERROR - % GAIN ERROR - % 0.3 0.2 0.1 0.2 0.1 0 -0.1 -0.2 -0.3 -40 0 0 5 15 10 20 25 30 10 -15 60 35 SUPPLY VOLTAGE - Volt TEMPERATURE - °C VOUT vs VSENSE @ Supply = 3.6V VOUT vs VSENSE @ Supply = 2V 4 110 2 G = 100 1.8 3.5 1.6 3 G = 100 1.4 G = 50 2.5 VOUT - V VOUT - V 85 2 G = 25 1.5 1.2 1.0 G = 50 0.8 0.6 1 G = 25 0.4 0.5 0.2 0 0 50 0 100 0 150 80 60 100 VSENSE- mV VSENSE- mV Small-Signal Gain vs Frequency Common-Mode Rejection vs Frequency 5 COMMON-MODE REJECTION - dB 0 0 SMALL-SIGNAL GAIN -dB 40 20 G = 50 -5 -10 G = 100 G = 25 -15 -20 -25 -30 -35 0.001 0.01 0.1 1 10 FREQUENCY - kHz TS1103 Rev. 1.1 100 1000 -20 G = 50, 100 -40 -60 G =25 -80 -100 -120 -140 0.001 0.01 0.1 1 10 100 1000 FREQUENCY - kHz Page 5 TS1103 TYPICAL PERFORMANCE CHARACTERISTICS VRS+ = VRS- = 3.6V; COUT = 0pF; TA = +25°C, unless otherwise noted. Large-Signal Pulse Response, Gain = 50 VOUT VOUT VSENSE VSENSE Small-Signal Pulse Response, Gain = 50 200µs/DIV Small-Signal Pulse Response, Gain = 25 Large-Signal Pulse Response, Gain = 25 VOUT VOUT VSENSE VSENSE 200µs/DIV Small-Signal Pulse Response, Gain = 100 Large-Signal Pulse Response, Gain = 100 VOUT VOUT VSENSE 200µs/DIV VSENSE 200µs/DIV 200µs/DIV Page 6 200µs/DIV TS1103 Rev. 1.1 TS1103 PIN FUNCTIONS PIN 1 2 3 4 5 6 LABEL GND SIGN OUT RSVDD RS+ FUNCTION Ground. Connect this pin to analog ground. Comparator Output, push-pull; SIGN is HIGH for (VRS+ > VRS-) and LOW for (VRS- > VRS+). Output Voltage. VOUT is proportional to VSENSE = (VRS+ - VRS-) or (VRS- - VRS+). External Sense Resistor Load-Side Connection SIGN Comparator External Power Supply Pin; Connect this pin to system’s logic VDD supply. External Sense Resistor Power-Side Connection BLOCK DIAGRAM DESCRIPTION OF OPERATION The internal configuration of the TS1103 – a bidirectional high-side, current-sense amplifier – is a variation of the TS1100 uni-directional current-sense amplifier. In the design of the TS1103, the input amplifier was reconfigured for fully differential input/output operation and a second low-threshold pchannel FET (M2) was added where the drain terminal of M2 is also connected to ROUT. Therefore, the behavior of the TS1103 for when VRS- > VRS+ is identical for when VRS+ > VRS-. inverting input of the TS1103 (the RS- terminal), the applied voltage is ILOAD x RSENSE. Since the RSterminal is the non-inverting input of the internal op amp, op amp feedback action forces the inverting input of the internal op amp to the same potential (ILOAD x RSENSE). Therefore, the voltage drop across RSENSE (VSENSE = VRS+ - VRS-) and the voltage drop across RGAINA (at the RS+ terminal) are equal. Necessary for gain ratio match, both RGAINA and RGAINB are the same value. Referring to the typical application circuit on Page 1, the inputs of the TS1103’s differential input/output amplifier are connected across an external RSENSE resistor that is used to measure current. At the non- Since p-channel M1’s source is connected to the inverting input of the internal op amp and since the voltage drop across RGAINA is the same as the TS1103 Rev. 1.1 Page 7 TS1103 external VSENSE, op amp feedback action drives the gate of M1 such that M1’s drain-source current is equal to: IDS(M1) = VSENSE RGAINA or ILOAD x RSENSE RGAINA Since M1’s drain terminal is connected to ROUT, the output voltage of the TS1103 at the OUT terminal is, therefore; IDS(M1) = VOUT = ILOAD x RSENSE x indicates the magnitude of the load current, the TS1103’s SIGN output indicates the load current’s direction. The SIGN output is a logic high when M1 is conducting current (VRS+ > VRS-). Alternatively, the SIGN output is a logic low when M2 is conducting current (VRS+ < VRS-). The SIGN comparator’s transfer characteristic is illustrated in Figure 1. Unlike other current-sense amplifiers that implement a OUT/SIGN arrangement, the TS1103 exhibits no “dead zone” at ILOAD switchover. ROUT RGAINA When the voltage at the RS- terminal is greater than the voltage at the RS+ terminal, the external VSENSE voltage drop is impressed upon RGAINB. The voltage drop across RGAINB is then converted into a current by M2 that then produces an output voltage across ROUT. In this design, when M1 is conducting current (VRS+ > VRS-), the TS1103’s internal amplifier holds M2 OFF. When M2 is conducting current (VRS- > VRS+), the internal amplifier holds M1 OFF. In either case, the disabled FET does not contribute to the resultant output voltage. Table 1: Internal Gain Setting Resistors (Typical Values) GAIN (V/V) 25 50 100 200 RGAIN[A/B] (Ω) 400 200 100 100 ROUT (Ω) 10k 10k 10k 20k Part Number TS1103-25 TS1103-50 TS1103-100 TS1103-200 Figure 1: TS1103's SIGN Comparator Transfer Characteristic. 100 SIGN Propagation Delay - ms The current-sense amplifier’s gain accuracy is therefore the ratio match of ROUT to RGAIN[A/B]. For each of the four gain options available, Table 1 lists the values for ROUT and RGAIN[A/B]. The TS1103’s output stage is protected against input overdrive by use of an output current-limiting circuit of 3mA (typical) and a 7V internal clamp protection circuit. 10 1 The SIGN Comparator Output 0.1 As shown in the TS1103’s block diagram, the design of the TS1103 incorporated one additional feature – an analog comparator the inputs of which monitor the internal amplifier’s differential output voltage. While the voltage at the TS1103’s OUT terminal Page 8 0.1 1 10 100 VSENSE (│VRS+ - VRS-│) - mV Figure 2: SIGN Comparator Propagation Delay vs VSENSE. TS1103 Rev. 1.1 TS1103 The other attribute of the SIGN comparator’s behavior is its propagation delay as a function of applied VSENSE [(VRS+ - VRS-) or (VRS- - VRS+)]. As shown in Figure 2, the SIGN comparator’s propagation delay behavior is symmetric regardless of current-flow direction and is inversely proportional to VSENSE. APPLICATIONS INFORMATION Choosing the Sense Resistor Selecting the optimal value for the external RSENSE is based on the following criteria and for each commentary follows: 1) RSENSE Voltage Loss 2) VOUT Swing vs. Applied Input Voltage at VRS+ and Desired VSENSE 3) Total ILOAD Accuracy 4) Circuit Efficiency and Power Dissipation 5) RSENSE Kelvin Connections 1) RSENSE Voltage Loss For lowest IR power dissipation in RSENSE, the smallest usable resistor value for RSENSE should be selected. 2) VOUT Swing vs. Applied Input Voltage at VRS+ and Desired VSENSE As there is no separate power supply pin for the TS1103, the circuit draws its power from the voltage at its RS+ and RS- terminals. Therefore, the signal voltage at the OUT terminal is bounded by the minimum voltage applied at the RS+ terminal. Therefore, VOUT(max) = VRS+(min) - VSENSE(max) – VOH(max) and RSENSE VOUT max GAIN × ILOAD max where the full-scale VSENSE should be less than VOUT(MAX)/GAIN at the application’s minimum RS+ terminal voltage. For best performance with a 3.6V power supply, RSENSE should be chosen to generate a VSENSE of: a) 120mV (for the 25V/V GAIN option), b) 60mV (for the 50V/V GAIN option), c) 30mV (for the 100V/V GAIN option), or d) 15mV (for the 200V/V GAIN option) at the full-scale ILOAD current in each application. For the case where the TS1103 Rev. 1.1 minimum power supply voltage is higher than 3.6V, each of the four full-scale VSENSEs above can be increased. 3) Total Load Current Accuracy In the TS1103’s linear region where VOUT < VOUT(max), there are two specifications related to the circuit’s accuracy: a) the TS1103’s input offset voltage (VOS(max) = 200μV) and b) its gain error (GE(max) = 0.6%). An expression for the TS1103’s total error is given by: VOUT = [GAIN x (1 ± GE) x VSENSE] ± (GAIN x VOS) A large value for RSENSE permits the use of smaller load currents to be measured more accurately because the effects of offset voltages are less significant when compared to larger VSENSE voltages. Due care though should be exercised as previously mentioned with large values of RSENSE. 4) Circuit Efficiency and Power Dissipation IR losses in RSENSE can be large especially at high load currents. It is important to select the smallest, usable RSENSE value to minimize power dissipation and to keep the physical size of RSENSE small. If the external RSENSE is allowed to dissipate significant power, then its inherent temperature coefficient may alter its design center value, thereby reducing load current measurement accuracy. Precisely because the TS1103’s input stage was designed to exhibit a very low input offset voltage, small RSENSE values can be used to reduce power dissipation and minimize local hot spots on the pcb. 5) RSENSE Kelvin Connections For optimal VSENSE accuracy in the presence of large load currents, parasitic pcb track resistance should be minimized. Kelvin-sense pcb connections between RSENSE and the TS1103’s RS+ and RSterminals are strongly recommended. The drawing in Figure 3 illustrates the connections between the Page 9 TS1103 current-sense amplifier and the current-sense resistor. The pcb layout should be balanced and symmetrical to minimize wiring-induced errors. In addition, the pcb layout for RSENSE should include good thermal management techniques for optimal RSENSE power dissipation. rectification of noise signals occurs because all amplifier input stages are constructed with transistors that can behave as high-frequency signal detectors in the same way pn-junction diodes were used as RF envelope detectors in early radio designs. Against common-mode injected noise, the amplifier’s internal common-mode rejection is usually sufficient. To counter the effects of externally-injected noise, it has always been good engineering practice to add external low-pass filters in series with the inputs of a current-sense amplifier. In the design of discrete current-sense amplifiers, resistors used in the external low-pass filters were incorporated into the circuit’s overall design so errors because of any input-bias current-generated offset voltage errors and gain errors were compensated. Figure 3: Making PCB Connections to RSENSE. 6) RSENSE Composition Current-shunt resistors are available in metal film, metal strip, and wire-wound constructions. Wirewound current-shunt resistors are constructed with wire spirally wound onto a core. As a result, these types of current shunt resistors exhibit the largest self inductance. In applications where the load current contains high-frequency transients, metal film or metal strip current sense resistors are recommended. Internal Noise Filter In power management and motor control applications, current-sense amplifiers are required to measure load currents accurately in the presence of both externally-generated differential and commonmode noise. An example of differential-mode noise that can appear at the inputs of a current-sense amplifier is high-frequency ripple. High-frequency ripple – whether injected into the circuit inductively or capacitively - can produce a differential-mode voltage drop across the external current-shunt resistor (RSENSE). An example of externallygenerated, common-mode noise is the highfrequency output ripple of a switching regulator that can result in common-mode noise injection into both inputs of a current-sense amplifier. Even though the load current signal bandwidth is DC, the input stage of any current-sense amplifier can rectify unwanted, out-of-band noise that can result in an apparent error voltage at its output. This Page 10 With the advent of monolithic current-sense amplifiers, like the TS1103, the addition of external low-pass filters in series with the current-sense amplifier’s inputs only introduces additional offset voltage and gain errors. To minimize or eliminate altogether the need for external low-pass filters and to maintain low input offset voltage and gain errors, the TS1103 incorporates a 50-kHz (typ), 2nd-order differential low-pass filter as shown in the TS1103’s Block Diagram. Output Filter Capacitor If the TS1103 is part of a signal acquisition system where its OUT terminal is connected to the input of an ADC with an internal, switched-capacitor trackand-hold circuit, the internal track-and-hold’s sampling capacitor can cause voltage droop at VOUT. A 22nF to 100nF good-quality ceramic capacitor from the OUT terminal to GND forms a low-pass filter with the TS1103’s ROUT and should be used to minimize voltage droop (holding VOUT constant during the sample interval. Using a capacitor on the OUT terminal will also reduce the TS1103’s smallsignal bandwidth as well as band-limiting amplifier noise. PC Board Layout and Power-Supply Bypassing For optimal circuit performance, the TS1103 should be in very close proximity to the external currentsense resistor and the pcb tracks from RSENSE to the RS+ and the RS- input terminals of the TS1103 should be short and symmetric. Also recommended are a ground plane and surface mount resistors and capacitors. TS1103 Rev. 1.1 TS1103 PACKAGE OUTLINE DRAWING 6-Pin SOT23 Package Outline Drawing (N.B., Drawings are not to scale) Note: Dimension are exclusive of mold flash and gate burr. 2. Dimension are exclusive of solder plating. 3. The foot length measuring is based on the gauge plane method. 4. Package is surface to be matte finish VDI 11~13. 5. Dimensions and tolerances are as per ANSI Y14.5M, 1982. 6. This part is compliant with EIAJ specification SC74A and JEDEC MO-178 AB spec. 7. Die is facing up for mold, Die is facing down for trim/form, ie. reverse trim/form. 8. All dimensions are in mm. 2.80 - 3.00 0.300(MIN) 0.500(MAX) 2.60 - 3.00 0.950 TYP. 1.50 - 1.75 0.950 TYP. 10° TYP. (2 Plcs) 10° TYP. (2 Plcs) 1.50 – 1.75 0.50 -0.70 0.90 - 1.45 0.60 - 0.80 0.09 – 0.127 0.050(MIN) 0.15(MAX) 10° TYP. (2 Plcs) 10° TYP. (2 Plcs) 0.25 Guage 0.30 - 0.55 Plane 0° ~ 8 Patent Notice Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analog-intensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. 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