W320-04H

W320-04 200 MHz Spread Spectrum Clock Synthesizer/Driver with Differential CPU Outputs Features Benefits • Compliant with Intel® CK-Titan clock synthesizer/driver specifications • Supports next-generation Pentium® processors using differential clock drivers • Multiple output clocks at different frequencies • Motherboard clock generator — Three pairs of differential CPU outputs, up to 200 MHz — Supports multiple CPUs and a chipset — Ten synchronous PCI clocks, three free-running — Supports AGP, DRCG reference, and Hub Link — Six 3V66 clocks — Supports USB host controller and graphic controller — Two 48 MHz clocks — Support for PCI slots and chipset — Supports ISA slots and I/O chip — One reference clock at 14.318 MHz • Enables reduction of electromagnetic interference (EMI) and overall system cost — One VCH clock • Spread Spectrum clocking (down spread) • Enables ACPI-compliant designs • Power-down features (PCI_STOP#, CPU_STOP# PWR_DWN#) • Supports up to four CPU clock frequencies • Three Select inputs (Mode select and IC Frequency Select) • Widely available standard package enables lower cost • Enables ATE and “bed of nails” testing • OE and Test Mode support • 56-pin SSOP package and 56-pin TSSOP package Logic Block Diagram Pin Configurations SSOP and TSSOP Top View XTAL OSC VDD_REF PWR VDD_REF 1 56 REF XTAL_IN 2 55 S1 XTAL_OUT 3 54 S0 GND_REF 4 53 CPU_STOP# PCI_F0 5 52 CPU0 PCI_F1 6 51 CPU#0 PCI_F2 7 50 VDD_CPU VDD_PCI 8 49 CPU1 GND_PCI 9 48 CPU#1 PCI0 10 47 GND_CPU VDD_PCI PCI_F0:2 PCI1 11 46 VDD_CPU PCI2 45 CPU2 PCI0:6 PCI3 12 13 44 CPU#2 VDD_PCI 14 43 MULT0# GND_PCI PCI4 15 42 IREF 41 PCI5 PCI6 VDD_3V66 17 GND_IREF S2 19 38 REF PLL Ref Freq PLL 1 Divider Network PWR S0:2 Gate Stop Clock Control PWR_GD# CPU_STOP# VDD_CPU CPU0:2 CPU#0:2 PWR Stop Clock Control PCI_STOP# /2 PWR_DWN# VDD_3V66 PWR 3V66_0 PWR 3V66_2:4/ 66BUFF0:2 3V66_5/ 66IN PLL 2 VDD_48MHz PWR USB (48MHz) DOT (48MHz) VCH_CLK/ 3V66_1 18 40 39 USB GND_3V66 20 37 DOT VDD_ 48 MHz 66BUFF0/3V66_2 21 36 GND_ 48 MHz 66BUFF1/3V66_3 22 35 66BUFF2/3V66_4 66IN/3V66_5 23 34 3V66_1/VCH PCI_STOP# 24 25 33 3V66_0 32 VDD_3V66 26 31 GND_3V66 27 30 28 29 SCLK SDATA PWR_DWN# VDD_CORE GND_CORE PWR_GD# SDATA SCLK 16 W320-04 X1 X2 SMBus Logic ....................... Document #: 38-07010 Rev. *C Page 1 of 16 400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1+(512) 416-9669 www.silabs.com W320-04 Pin Summary Name Pins Description REF 56 3.3V 14.318-MHz clock output. XTAL_IN 2 14.318-MHz crystal input. XTAL_OUT 3 14.318-MHz crystal input. CPU, CPU# [0:2] 44, 45, 48, 49, 51, 52 Differential CPU clock outputs. 3V66_0 33 3.3V 66-MHz clock output. 3V66_1/VCH 35 3.3V selectable through SMBus to be 66 MHz or 48 MHz. 66IN/3V66_5 24 66-MHz input to buffered 66BUFF and PCI or 66-MHz clock from internal VCO. 66BUFF [2:0] /3V66 [4:2] 21, 22, 23 66-MHz buffered outputs from 66Input or 66-MHz clocks from internal VCO. PCI_F [0:2] 5, 6, 7, 33-MHz clocks divided down from 66Input or divided down from 3V66. PCI [0:6] 10, 11, 12, 13, 16, 17, 18 PCI clock outputs divided down from 66Input or divided down from 3V66. USB 39 Fixed 48-MHz clock output. DOT 38 Fixed 48-MHz clock output. S2 40 Special 3.3V 3-level input for Mode selection. S1, S0 54, 55 3.3V LVTTL inputs for CPU frequency selection. IREF 42 A precision resistor is attached to this pin, which is connected to the internal current reference. MULT0 43 3.3V LVTTL input for selecting the current multiplier for the CPU outputs. PWR_DWN# 25 3.3V LVTTL input for Power_Down# (active LOW). PCI_STOP# 34 3.3V LVTTL input for PCI_STOP# (active LOW). CPU_STOP# 53 3.3V LVTTL input for CPU_STOP# (active LOW). PWRGD# 28 3.3V LVTTL input is a level sensitive strobe used to determine when S[2:0] and MULTI0 inputs are valid and OK to be sampled (Active LOW). Once PWRGD# is sampled LOW, the status of this output will be ignored. SDATA 29 SMBus compatible SDATA. SCLK 30 SMBus compatible SCLK. VDD_REF, VDD_PCI, VDD_3V66, VDD_CPU 1, 8, 14, 19, 32, 46, 50 3.3V power supply for outputs. VDD_48 MHz 37 3.3V power supply for 48 MHz. VDD_CORE 26 3.3V power supply for PLL. GND_REF, GND_PCI, GND_3V66, GND_IREF, VDD_CPU 4, 9, 15, 20, 31, 36, 41, 47 Ground for outputs. GND_CORE 27 Ground for PLL. .......................Document #: 38-07010 Rev. *C Page 2 of 16 W320-04 Function Table[1] CPU (MHz) 3V66[0:1] (MHz) 66BUFF[0:2]/ 3V66[2:4] (MHz) 66IN/3V66_5 (MHz) PCI_F/PCI (MHz) USB/DOT (MHz) Notes 14.318 MHz 48 MHz 2, 3, 4 66IN/2 14.318 MHz 48 MHz 2, 3, 4 66 MHz Input 66IN/2 14.318 MHz 48 MHz 2, 3, 4 66 MHz Input 66IN/2 14.318 MHz 48 MHz 2, 3, 4 66 MHz 66 MHz 33 MHz 14.318 MHz 48 MHz 2, 3, 4 66 MHz 66 MHz 33 MHz 14.318 MHz 48 MHz 2, 3, 4 66 MHz 66 MHz 66 MHz 33 MHz 14.318 MHz 48 MHz 2, 3, 4 133 MHz 66 MHz 66 MHz 66 MHz 33 MHz 14.318 MHz 48 MHz 2, 3, 4 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 1, 5 1 TCLK/2 TCLK/4 TCLK/4 TCLK/4 TCLK/8 TCLK TCLK/2 5, 6, 7 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved – 1 1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved – S2 S1 S0 1 0 0 66 MHz 66 MHz 66IN 66 MHz Input 66IN/2 1 0 1 100 MHz 66 MHz 66IN 66 MHz Input 1 1 0 200 MHz 66 MHz 66IN 1 1 1 133 MHz 66 MHz 66IN 0 0 0 66 MHz 66 MHz 0 0 1 100 MHz 66 MHz 0 1 0 200 MHz 0 1 1 Mid 0 0 Mid 0 Mid Mid REF0(MHz) Swing Select Functions Mult0 Board Target Trace/Term Z Reference R, IREF = VDD/(3*Rr) Output Current VOH @ Z 0 50 Rr = 221 1%, IREF = 5.00 mA IOH = 4*IREF 1.0V @ 50 1 50 Rr = 475 1%, IREF = 2.32 mA IOH = 6*IREF 0.7V @ 50 Clock Driver Impedances Impedance Buffer Name VDD Range CPU, CPU# Buffer Type Min.  Typ.  12 30 Type X1 Max.  50 REF 3.135–3.465 Type 5 55 PCI, 3V66, 66BUFF 3.135–3.465 Type 5 12 30 55 USB 3.135–3.465 Type 3A 12 30 60 DOT 3.135–3.465 Type 3B 12 30 60 Clock Enable Configuration PWR_DWN# CPU_STOP# PCI_STOP# CPU CPU# 3V66 66BUFF PCI_F PCI 0 X X IREF*2 FLOAT LOW LOW LOW LOW USB/DOT VCOS/ OSC 1 0 0 ON FLOAT ON ON ON OFF ON ON 1 0 1 ON LOW ON ON ON ON ON ON 1 1 0 ON ON ON ON ON OFF ON ON 1 1 1 ON ON ON ON ON ON ON ON LOW OFF Note: 1. TCLK is a test clock driven in on the XTALIN input in test mode. 2. “Normal” mode of operation 3. Range of reference frequency allowed is min. = 14.316, nom. = 14.31818 MHz, max. = 14.32 MHz. 4. Frequency accuracy of 48 MHz must be +167PPM to match USB default. 5. Mid. is defined a Voltage level between 1.0V and 1.8V for three-level input functionality. Low is below 0.8V. High is above 2.0V. 6. Required for DC output impedance verification. 7. These modes are to use the SAME internal dividers as the CPU = 200 MHz mode. The only change is to slow down the internal VCO to allow under clock margining. .......................Document #: 38-07010 Rev. *C Page 3 of 16 W320-04 Serial Data Interface (SMBus) ability to stop after any complete byte has been transferred. Indexed bytes are not allowed. To enhance the flexibility and function of the clock synthesizer, a two-signal SMBus interface is provided according to SMBus specification. Through the Serial Data Interface, various device functions such as individual clock output buffers, can be individually enabled or disabled. W320-04 supports both block read and block write operations. A block write begins with a slave address and a WRITE condition. The R/W bit is used by the SMBus controller as a data direction bit. A zero indicates a WRITE condition to the clock device. The slave receiver address is 11010010 (D2h). The registers associated with the Serial Data Interface initialize to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions. Data Protocol The clock driver serial protocol accepts only block writes from the controller. The bytes must be accessed in sequential order from lowest to highest byte, (most significant bit first) with the A command code of 0000 0000 (00h) and the byte count bytes are required for any transfer. After the command code, the core logic issues a byte count which describes number of additional bytes required for the transfer, not including the command code and byte count bytes. For example, if the host has 20 data bytes to send, the first byte would be the number 20 (14h), followed by the 20 bytes of data. The byte count byte is required to be a minimum of 1 byte and a maximum of 32 bytes It may not be 0. Figure 1 shows an example of a block write. A transfer is considered valid after the acknowledge bit corresponding to the byte count is read by the controller. Figure 1. Start Slave Address R/W 0/1 A bit 1 1 0 1 0 0 1 0 From Master to Slave 1 bit 7 From bits Slave to1Master1 Command Code 00000000 A Byte Count = N A Data Byte 0 A 8 bits 1 8 bits 1 8 bits Figure 1. An Example of a Block Write . . . Data Byte N-1 A Stop bit 1 8 bits 1 1 bit Data Byte Configuration Map Data Byte 0: Control Register (0 = Enable, 1 = Disable) Affected Pin# Bit Name Description Type Power On Default Bit 7 5, 6, 7, 10, 11, 12, 13, 16, 17, 18, 33, 35 PCI [0:6] CPU[2:0] 3V66[1:0] Spread Spectrum Enable 0 = Spread Off, 1 = Spread On R/W 0 Bit 6 – TBD TBD R 0 Bit 5 35 3V66_1/VCH VCH Select 66 MHz/48 MHz 0 = 66 MHz, 1 = 48 MHz R/W 0 Bit 4 44, 45, 48, 49, 51, 52 CPU [2:0] CPU# [2:0] CPU_STOP# Reflects the current value of the external CPU_STOP# pin R N/A Bit 3 10, 11, 12, 13, 16, 17, 18 PCI [6:0] PCI_STOP# (Does not affect PCI_F [2:0] pins) R/W N/A Bit 2 – – S2 Reflects the value of the S2 pin sampled on power-up R N/A Bit 1 – – S1 Reflects the value of the S1 pin sampled on power-up R N/A Bit 0 – – S0 Reflects the value of the S1 pin sampled on power-up R N/A .......................Document #: 38-07010 Rev. *C Page 4 of 16 W320-04 Data Byte 1 Bit Pin# Bit 7 Bit 6 – Name N/A 52, 49, 45 CPU0:2 Description Type Power On Default CPU Mult0 Value R N/A Three-State CPU0:2 during power down 0 = Normal; 1 = Three-stated R/W 0 Bit 5 44, 45 CPU2 CPU2# Allow Control of CPU2 with assertion of CPU_STOP# 0 = Not free running; 1 = Free running R/W 0 Bit 4 48, 49 CPU1 CPU1# Allow Control of CPU1 with assertion of CPU_STOP# 0 = Not free running;1 = Free running R/W 0 Bit 3 51, 52 CPU0 CPU0# Allow Control of CPU0 with assertion of CPU_STOP# 0= Not free running; 1 = Free running R/W 0 Bit 2 44, 45 CPU2 CPU2# CPU2 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Bit 1 48, 49 CPU1 CPU1# CPU1Output Enable 1 = Enabled; 0= Disabled R/W 1 Bit 0 51, 52 CPU0 CPU0# CPU0 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Data Byte 2 Bit Pin# Name Pin Description Type Power On Default Bit 7 – N/A N/A R 0 Bit 6 18 PCI6 PCI6 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Bit 5 17 PCI5 PCI5 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Bit 4 16 PCI4 PCI4 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Bit 3 13 PCI3 PCI3 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Bit 2 12 PCI2 PCI2 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Bit 1 11 PCI1 PCI1 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Bit 0 10 PCI0 PCI0 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Data Byte 3 Bit Pin# Bit 7 38 Bit 6 Bit 5 Name Pin Description Type DOT DOT 48-MHz Output Enable 39 USB USB 48-MHz Output Enable R/W 1 7 PCI_F2 Allow control of PCI_F2 with assertion of PCI_STOP# 0 = Free running; 1 = Stopped with PCI_STOP# R/W 0 Bit 4 6 PCI_F1 Allow control of PCI_F1 with assertion of PCI_STOP# 0 = Free running; 1 = Stopped with PCI_STOP# R/W 0 Bit 3 5 PCI_F0 Allow control of PCI_F0 with assertion of PCI_STOP# 0 = Free running; 1 = Stopped with PCI_STOP# R/W 0 Bit 2 7 PCI_F2 PCI_F2 Output Enable R/W 1 Bit 1 6 PCI_F1 PCI_F1Output Enable R/W 1 Bit 0 5 PCI_F0 PCI_F0 Output Enable R/W 1 .......................Document #: 38-07010 Rev. *C Page 5 of 16 R/W Power On Default 1 W320-04 Data Byte 4 Bit Pin# Bit 7 Name Pin Description – TBD Bit 6 – TBD Bit 5 33 3V66_0 Bit 4 35 3V66_1/VCH 3V66_1/VCH Output Enable 1 = Enabled; 0 = Disabled Bit 3 24 Bit 2 Type N/A Power On Default R 0 N/A R 0 3V66_0 Output Enable 1 = Enabled; 0 = Disabled R/W 1 R/W 1 66IN/3V66_5 R/W 3V66_5 Output Enable 1 = Enable; 0 = Disable NOTE: This bit should be used when pin 24 is configured as 3v66_5 output. Do not clear this bit when pin 24 is configured as 66in input. 1 23 66BUFF2 66-MHz Buffered 2 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Bit 1 22 66BUFF1 66-MHz Buffered 1 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Bit 0 21 66BUFF0 66-MHz Buffered 0 Output Enable 1 = Enabled; 0 = Disabled R/W 1 Data Byte 5 Bit Pin# Name Pin Description Type Power On Default Bit 7 N/A N/A R 0 Bit 6 N/A N/A R 0 Bit 5 66BUFF [2:0] Tpd 66IN to 66BUFF propagation delay control R/W 0 Bit 4 66BUFF [2:0] R/W 0 Bit 3 DOT R/W 0 Bit 2 DOT R/W 0 Bit 1 USB R/W 0 Bit 0 USB R/W 0 DOT edge rate control USB edge rate control Byte 6: Vendor ID Bit Description Type Power On Default Bit 7 Revision Code Bit 3 R 0 Bit 6 Revision Code Bit 2 R 0 Bit 5 Revision Code Bit 1 R 0 Bit 4 Revision Code Bit 0 R 0 Bit 3 Vendor ID Bit 3 R 1 Bit 2 Vendor ID Bit 2 R 0 Bit 1 Vendor ID Bit 1 R 0 Bit 0 Vendor ID Bit 0 R 0 .......................Document #: 38-07010 Rev. *C Page 6 of 16 W320-04 Maximum Ratings Storage Temperature (Non-Condensing) ....–65C to +150C (Above which the useful life may be impaired. For user guidelines, not tested.) Max. Soldering Temperature (10 sec) ....................... +260C Junction Temperature................................................ +150C Supply Voltage..................................................–0.5 to +7.0V Package Power Dissipation............................................... 1 Input Voltage.............................................. –0.5V to VDD+0.5 Static Discharge Voltage (per MIL-STD-883, Method 3015) ............................ > 2000V Operating Conditions[8] Over which Electrical Parameters are Guaranteed Min. Max. Unit VDD_REF, VDD_PCI,VDD_CORE, VDD_3V66, VDD_CPU, Parameter 3.3V Supply Voltages Description 3.135 3.465 V VDD_48 MHz 48-MHz Supply Voltage 2.85 3.465 V TA Operating Temperature, Ambient 0 70 C Cin Input Pin Capacitance 5 pF CXTAL XTAL Pin Capacitance 22.5 pF CL Max. Capacitive Load on USBCLK, REF PCICLK, 3V66 f(REF) Reference Frequency, Oscillator Nominal Value pF 20 30 14.318 14.318 MHz Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min. Max. Unit VIH High-level Input Voltage Except Crystal Pads. Threshold Voltage for Crystal Pads = VDD/2 VIL Low-level Input Voltage Except Crystal Pads 2.0 VOH High-level Output Voltage USB, REF, 3V66 VOL Low-level Output Voltage 0.55 V IIH Input HIGH Current 0 < VIN < VDD –5 5 mA IIL Input LOW Current 0 < VIN < VDD –5 5 mA IOH High-level Output Current CPU For IOH =6*IRef Configuration Type X1, VOH = 0.65V REF, DOT, USB Type 3, VOH = 1.00V IOH = –1 mA 2.4 PCI IOH = –1 mA 2.4 USB, REF, 3V66 IOL = 1 mA PCI IOL = 1 mA Type 5, VOH = 1.00V Low-level Output Current REF, DOT, USB Type 3, VOL = 1.95V Type 5, VOL = 1.95 V Type 5, VOL = 0.4V IOZ Output Leakage Current Three-state mA –29 –23 –33 –33 29 Type 3, VOL = 0.4V 3V66, PCI, REF V 14.9 Type 5, VOH = 3.135V IOL V 12.9 Type X1, VOH = 0.74V V V 0.4 Type 3, VOH = 3.135V 3V66, DOT, PCI, REF V 0.8 mA 27 30 38 10 mA IDD3 3.3V Power Supply Current VDD_CORE/VDD3.3 = 3.465V, FCPU = 133 MHz 360 mA IDDPD3 3.3V Shut-down Current VDD_CORE/VDD3.3 = 3.465V and @ IREF = 2.32 mA 25 mA IDDPD3 3.3V Shut-down Current VDD_CORE/VDD3.3 = 3.465V and @ IREF = 5.0 mA 45 mA Note: 8. The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. .......................Document #: 38-07010 Rev. *C Page 7 of 16 W320-04 - Switching Characteristics[9] Over the Operating Range Parameter Output Description Output Duty Cycle[10] Test Conditions Min. Max. Unit Measured at 1.5V 45 55 % 2.0 ns t1 All t3 USB, REF, DOT Falling Edge Rate Between 2.4V and 0.4V 0.5 t3 PCI,3V66 Falling Edge Rate Between 2.4V and 0.4V 1.0 4.0 V/ns t5 3V66[0:1] 3V66-3V66 Skew Measured at 1.5V 500 ps t5 66BUFF[0:2] 66BUFF-66BUFF Skew Measured at 1.5V 175 ps t6 PCI PCI-PCI Skew Measured at 1.5V 500 ps t7 3V66, PCI 3V66-PCI Clock Jitter 3V66 leads. Measured at 1.5V 3.5 ns t9 3V66 Cycle-Cycle Clock Jitter Measured at 1.5V t9 = t9A – t9B 250 ps t9 USB, DOT Cycle-Cycle Clock Jitter Measured at 1.5V t9 = t9A – t9B 350 ps t9 PCI Cycle-Cycle Clock Jitter Measured at 1.5V t9 = t9A – t9B 500 ps t9 REF Cycle-Cycle Clock Jitter Measured at 1.5V t9 = t9A – t9B 1000 ps 1.5 CPU 1.0V Switching Characteristics t2 CPU Rise Time Measured differential waveform from –0.35V to +0.35V 175 467 ps t3 CPU Fall Time Measured differential waveform from –0.35V to +0.35V 175 467 ps t4 CPU CPU-CPU Skew Measured at Crossover 150 ps t8 CPU Cycle-Cycle Clock Jitter Measured at Crossover t8 = t8A – t8B 150 ps 325 mV CPU Rise/Fall Matching Measured with test loads[11] loads[11] 0.92 1.45 V Voh CPU High-level Output Voltage including overshoot Measured with test Vol CPU Low-level Output Voltage including undershoot Measured with test loads[11] –0.2 0.35 V Vcrossover CPU Crossover Voltage Measured with test loads[11] 0.51 0.76 V CPU 0.7V Switching Characteristics t2 CPU Rise Time Measured single ended waveform from 175 0.175V to 0.525V 700 ps t3 CPU Fall Time Measured single ended waveform from 175 0.175V to 0.525V 700 ps t4 CPU CPU-CPU Skew Measured at Crossover 150 ps t8 CPU Cycle-Cycle Clock Jitter Measured at Crossover t8 = t8A – t8B With all outputs running 150 ps CPU Rise/Fall Matching Measured with test loads[12, 13] 20 % 0.85 V –0.15 V 0.43 V [13] Voh CPU High-level Output Voltage Including Overshoot Measured with test loads Vol CPU Low-level Output Voltage Including Undershoot Measured with test loads[13] Vcrossover CPU Crossover Voltage Measured with test loads[13] Notes: 9. All parameters specified with loaded outputs. 10. Duty cycle is measured at 1.5V when VDD = 3.3V. When VDD = 2.5V, duty cycle is measured at 1.25V. 11. The 1.0V test load is shown on the test circuit page. 12. Determined as a fraction of 2*(Trp – Trn)/(Trp +Trn) Where Trp is a rising edge and Trp is an intersecting falling edge. 13. The 0.7V test load is Rs = 33.2 ohm, Rp = 49.9 ohm in test circuit. .......................Document #: 38-07010 Rev. *C Page 8 of 16 0.28 W320-04 Definition and Application of PWRGD# Signal Vtt VRM8.5 PWRGD# CPU BSEL0 BSEL1 3.3V 3.3V 3.3V NPN PWRGD# CLOCK S0 10K 10K 10K 10K GMCH GENERATOR S1 .......................Document #: 38-07010 Rev. *C Page 9 of 16 W320-04 Switching Waveforms Duty Cycle Timing (Single-ended Output) t1B t1A Duty Cycle Timing (CPU Differential Output) t1B t1A All Outputs Rise/Fall Time VDD OUTPUT 0V t3 t2 CPU-CPU Clock Skew Host_b Host Host_b Host t4 3V66-3V66 Clock Skew 3V66 3V66 t PCI-PCI Clock Skew PCI PCI t .....................Document #: 38-07010 Rev. *C Page 10 of 16 W320-04 Switching Waveforms (continued) 3V66-PCI Clock Skew 3V66 PCI t7 CPU Clock Cycle-Cycle Jitter t8A t8B Host_b Host Cycle-Cycle Clock Jitter t9A t9B CLK PWRDWN# Assertion 66BUFF PCI Power Down Rest of Generator PCI_F (APIC) PWR_DWN# CPU CPU# 3V66 UNDEF 66IN USB REF Note: PCI_STOP# asserted LOW ..................... Document #: 38-07010 Rev. *C Page 11 of 16 W320-04 PWRDWN# Deassertion 10-30 s min. 100-200 s max. < 3 ms 66BUFF1/GMCH 66BUFF0,2 PCI PCI_F (APIC) PWR_DWN# CPU CPU# 3V66 66IN USB REF Note: PCI_STOP# asserted LOW PWRGD# Timing Diagrams GND VRM 5/12V PWRGD# VID [3:0] BSEL [1:0] PWRGD# FROM VRM Possible glitch while Clock VCC is coming up. Will be gone in 0.2–0.3 mS delay. PWRGD# FROM NPN VCC CPU CORE PWRGD# 0.2 -- 0.3 ms Wait for delay PWRGD# VCC W320 CLOCK GEN CLOCK STATE State 1 State 0 State 2 Sample BSELS State 3 OFF ON CLOCK VCO OFF ON CLOCK OUTPUTS Figure 2. CPU Power Before Clock Power .....................Document #: 38-07010 Rev. *C Page 12 of 16 W320-04 GND VRM 5/12V PWRGD# VID [3:0] BSEL [1:0] PWRGD# FROM VRM PWRGD# FROM NPN VCC CPU CORE PWRGD# 0.2 – 0.3 ms delay VCC W320 CLOCK GEN CLOCK STATE State 0 Wait for PWRGD# State 1 Sample BSELS State 2 State 3 OFF ON CLOCK VCO OFF ON CLOCK OUTPUTS Figure 3. CPU Power After Clock Power .....................Document #: 38-07010 Rev. *C Page 13 of 16 W320-04 Layout Example +3.3V Supply FB VDDQ3 0.005F 10 F C2 G G G C1 G 1 2 3 4 5 6 7 8 9 G G G V G G G G G V G W320-04 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 G 51 V 50 G 49 48 G 47 V 46 G 45 44 43 42 G 41 40 39 38 37 G 36 35 34 G 33 V 32 G 31 30 G 29 G V G V G G V G G G VDDQ3  G C6 C5 G G FB = Dale ILB1206 - 300 or 2TDKACB2012L-120 or 2 Murata BLM21B601S. Ceramic Caps C1 = 10–22 µF C2 = 0.005 F C5 = 0.1 F C6 = 10 F G = VIA to GND plane layer. V = VIA to respective supply plane layer. Note: Each supply plane or strip should have a ferrite bead and capacitors. .....................Document #: 38-07010 Rev. *C Page 14 of 16 W320-04 Test Circuit VDD_REF, VDD_PCI, VDD_3V66, VDD_CORE VDD_48 MHz, VDD_CPU 0.7V Test Load 4, 9, 15, 20, 27, 31, 36, 41 Rp 8, 14, 19, 26, 32, 37, 46, 50 Ref,USB Outputs Test Node Rs W320-04 Test Nodes OUTPUTS 20 pF PCI,3V66 Outputs Test Node 2 pF CPU 2 pF Rs Rp 30 pF Note: Each supply pin must have an individual decoupling capacitor. Note: All capacitors must be placed as close to the pins as is physically possible. 0.7V amplitude: RS = 33 ohm, RP = 50 ohm VDD_REF, VDD_PCI, VDD_3V66, VDD_CORE VDD_48 MHz, VDD_CPU 4, 9, 15, 20, 27, 31, 36, 41 1.0V Test Load 33 8, 14, 19, 26, 32, 37, 46 ,50 2 pF Ref,USB Outputs Test Node W320-04 475 CPU 33 OUTPUTS 20 pF Test Nodes 2 pF PCI,3V66 Outputs Test Node 30 pF 63.4 63.4 1.0V Amplitude Ordering Information Ordering Code Package Type Operating Range W320-04H 56-pin SSOP Commercial 0C TO 70C W320-04HT 56-pin SSOP - Tape and Reel Commercial 0C TO 70C W320-04X 56-pin TSSOP Commercial 0C TO 70C W320-04XT 56-pin TSSOP - Tape and Reel Commercial 0C TO 70C CYW320OXC-4 56-pin SSOP Commercial 0C TO 70C CYW320OXC-4T 56-pin SSOP - Tape and Reel Commercial 0C TO 70C CYW320ZXC-4 56-pin TSSOP Commercial 0C TO 70C CYW320ZXC-4T 56-pin TSSOP - Tape and Reel Commercial 0C TO 70C Lead-Free .....................Document #: 38-07010 Rev. *C Page 15 of 16 W320-04 Package Diagrams 56-Lead Shrunk Small Outline Package O56 .020 1 28 0.395 0.420 0.292 0.299 DIMENSIONS IN INCHES MIN. MAX. 29 56 0.720 0.730 SEATING PLANE 0.088 0.092 0.095 0.110 0.005 0.010 .010 GAUGE PLANE 0.110 0.025 BSC 0.008 0.0135 0.024 0.040 0°-8° 0.008 0.016 56-Lead Thin Shrunk Small Outline Package, Type II (6 mm x 12 mm) Z56 0.249[0.009] 28 1 DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-153 7.950[0.313] 8.255[0.325] PACKAGE WEIGHT 0.42gms 5.994[0.236] 6.198[0.244] PART # Z5624 STANDARD PKG. ZZ5624 LEAD FREE PKG. 29 56 13.894[0.547] 14.097[0.555] 1.100[0.043] MAX. GAUGE PLANE 0.25[0.010] 0.20[0.008] 0.851[0.033] 0.950[0.037] 0.500[0.020] BSC 0.170[0.006] 0.279[0.011] 0.051[0.002] 0.152[0.006] 0°-8° 0.508[0.020] 0.762[0.030] 0.100[0.003] 0.200[0.008] SEATING PLANE The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. .....................Document #: 38-07010 Rev. *C Page 16 of 16