WF121 Wi-Fi MODULE
DATA SHEET
Friday, 01 November 2013
Version 1.4.9
Copyright © 2000-2013 Bluegiga Technologies
All rights reserved.
Bluegiga Technologies assumes no responsibility for any errors which may appear in this manual.
Furthermore, Bluegiga Technologies reserves the right to alter the hardware, software, and/or specifications
detailed here at any time without notice and does not make any commitment to update the information
contained here. Bluegiga’s products are not authorized for use as critical components in life support devices
or systems.
The WRAP, Bluegiga Access Server, Access Point and iWRAP are registered trademarks of Bluegiga
Technologies.
The Bluetooth trademark is owned by the Bluetooth SIG Inc., USA and is licensed to Bluegiga Technologies.
All other trademarks listed herein are owned by their respective owners.
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VERSION HISTORY
Version
Comment
1.0
First version
1.1
FCC and IC information added
1.2
WF121-N layout guide
1.3
Added power consumption measurements, regulatory info and some
corrections
1.4
Added unassociated idle consumption and a chapter about power saving
modes
1.4.1
Added CE information
1.4.2
Removed details from the regulatory info
1.4.3
Corrected typos in the pad function tables
1.4.4
Reduced the list of supported coexistence schemes
1.4.5
Added links to Microchip reference guide, some notes on the coexistence
1.4.6
Added inversion notices to RTS/CTS for unambiguity
1.4.7
Added notes on the USB data pins GPIO use being input only to pin function
table
1.4.8
Added note on the engineering sample order codes
1.4.9
Additions to power supply description, rewrote power consumption section
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TABLE OF CONTENTS
1
Ordering Information......................................................................................................................................7
2
Pin-out and Terminal Descriptions ................................................................................................................8
3
Power control.............................................................................................................................................. 10
3.1
Power supply requirements ............................................................................................................... 10
3.2
Reset.................................................................................................................................................. 10
4
Microcontroller ............................................................................................................................................ 11
5
Interfaces .................................................................................................................................................... 12
5.1
General Purpose I/O pins .................................................................................................................. 12
5.2
Serial ports ......................................................................................................................................... 12
5.3
I C/SPI ............................................................................................................................................... 13
5.4
USB On-The-Go ................................................................................................................................ 13
5.5
Ethernet ............................................................................................................................................. 14
5.6
Analog inputs ..................................................................................................................................... 15
5.7
Timers ................................................................................................................................................ 15
5.8
Parallel master port ............................................................................................................................ 15
5.9
Microcontroller programming interface .............................................................................................. 15
5.10
RF Debug Interface ........................................................................................................................... 16
5.11
Bluetooth co-existence ...................................................................................................................... 16
5.12
CPU Clock ......................................................................................................................................... 17
5.13
32.768 kHz External Reference Clock ............................................................................................... 18
2
6
Example schematic .................................................................................................................................... 19
7
802.11 Radio .............................................................................................................................................. 20
7.1
Wi-Fi Receiver ................................................................................................................................... 20
7.2
Wi-Fi Transmitter ............................................................................................................................... 20
7.3
Antenna switch for Bluetooth coexistence ......................................................................................... 16
8
Firmware ..................................................................................................................................................... 21
9
Host interfaces............................................................................................................................................ 22
9.1
UART ................................................................................................................................................. 22
9.2
USB .................................................................................................................................................... 22
9.3
SPI ..................................................................................................................................................... 22
10
Electrical characteristics ........................................................................................................................ 23
10.1
Absolute maximum ratings ................................................................................................................ 23
10.2
Recommended operating conditions ................................................................................................. 23
10.3
Input/output terminal characteristics .................................................................................................. 24
10.4
Digital ................................................................................................................................................. 24
10.5
Reset.................................................................................................................................................. 24
10.6
Power consumption (preliminary) ...................................................................................................... 25
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11
RF Characteristics ................................................................................................................................. 27
12
Physical dimensions .............................................................................................................................. 29
13
Layout guidelines ................................................................................................................................... 30
13.1
WF121-E ............................................................................................................................................ 30
13.2
WF121-N............................................................................................................................................ 30
13.3
WF121-A ............................................................................................................................................ 31
13.4
Thermal considerations ..................................................................................................................... 32
13.5
EMC considerations ........................................................................................................................... 32
14
Soldering recommendations .................................................................................................................. 34
15
Certifications .......................................................................................................................................... 35
15.1
CE ...................................................................................................................................................... 35
15.2
FCC and IC ........................................................................................................................................ 35
15.2.1
FCC et IC ................................................................................................................................... 37
16
Qualified Antenna Types for WF121-E .................................................................................................. 40
17
Contact information ................................................................................................................................ 41
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DESCRIPTION
KEY FEATURES:
WF121 is a self-contained Wi-Fi module
providing a fully integrated 2.4GHz 802.11
b/g/n radio and a 32-bit microcontroller (MCU)
platform, making it an ideal product for
embedded applications requiring simple, lowcost and low-power wireless TCP/IP
connectivity. WF121 also provides flexible
interfaces
for
connecting
to
various
peripherals.
2.4GHz band IEEE 802.11 b/g/n radio
Excellent radio performance:
WF121 allows end user applications to be
embedded onto the on-board 32-bit
microcontroller either using a simple
TM
BGScript
scripting language or for more
sophisticated applications; ANSI C-language.
This cuts out the need of an external MCU
and allows the development of smaller and
lower-cost products. However WF121 can
also be used in modem-like mode in
applications where the external MCU is
needed.
TX power:
RX sensitivity: -97 dBm
+17 dBm
Host interfaces:
20Mbps UART
USB on-the-go
Peripheral interfaces:
GPIO, AIO and timers
I2C, SPI and UART
Ethernet
Embedded TCP/IP and 802.11 MAC
stacks:
With an integrated 802.11 radio, antenna,
single power supply, and regulatory
certifications, WF121 provides a low-risk and
fast time-to-market for applications requiring
Internet connectivity. This combined with
Bluegiga’s excellent customer service will turn
your Internet-of-Things applications into
reality.
IP, TCP, UDP, DHCP and DNS
protocols
BGAPI host protocol for modem
like usage
BGScript
TM
scripting language or
native C-development for selfcontained applications
APPLICATIONS:
PoS terminals
RFID and laser scanners
Wi-Fi internet radios
streaming products
32-bit embedded microcontroller
80MHz, 128kB RAM and 512kB
Flash
and
Wireless cameras
Video streaming
Portable navigation devices
Portable handheld devices
Wi-Fi medical sensors
Wireless picture frames
audio
MIPS architecture
o
Fully CE, FCC and IC qualified
PHYSICAL OUTLOOK:
WF121-A
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o
Temperature range: -40 C to +85 C
1
Ordering Information
Product code
Description
WF121-A
WF121 module with integrated antenna
WF121-E
WF121 module with U.FL connector
WF121 module with RF pin.
WF121-N
Non-standard product, so minimum order quantity applies.
Please contact: sales@bluegiga.com
DKWF121
WF121 development kit
Note: Modules with order code ending in –v1 are sold as engineering samples, while those with code –v2 are
production units. The difference between the two is in the microcontroller version used, the –v2 version fixes a
hardware bug that in some circumstances may cause rare bit errors. The modules differ in outlook in that the
–v1 only has the Bluegiga logo and text “WF121” while –v2 versions also have FCC/IC ID codes and CE logo.
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2
Pin-out and Terminal Descriptions
Figure 1: WF121 pinout
Pad number
Function
Description
9
VDD_3.3V
Module power supply
8
VDD_PA
1, 16, 26, 45,
48, 50
GND
51
GNDPAD
Thermal ground pad, should be soldered to a directly to a solid ground plane for improved thermal
conductance
40
BT_RF
Bluetooth coexistence antenna connection, connect to ground through a 51ohm resistor if
coexistence is not used
49
ANT
25
VBUS
USB VBUS input
13
MCLR
Module reset, also used for programming using a Microchip tool. Internal pull-up, can be left
floating or connected to ground through a 100nF capacitor for delayed power-up reset (note:
Microchip ICSP programming tools will not work with a capacitor)
RF power amplifier power supply
Ground, connected together internally but should all be connected directly to a solid ground plane
Antenna connection pad in N variant of the module, in other variants not connected
Table 1: Single function pad descriptions
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PAD#
GPIO
2
RB15
CN12
I2C
SPI
UART
Ethernet
Timer
USB
EMDC
3
RE0
ERXD1
PMD0
4
RE1
ERXD0
PMD1
5
RE2
ECRSDV
PMD2
6
RE3
EREFCL
K
PMD3
OCFB
Analog
Prog.
Parallel
AN15
7
RE4
ERXERR
PMD4
10
RE5
ETXEN
PMD5
11
RE6
ETXD0
PMD6
12
RE7
ETXD1
PMD7
14
15
17
RB1
CN3
RB0
CN2
RB8
SS4
nU2CTS
U5RX
SCK4
nU2RTS
U5TX
C1OUT
Other
PMA0
PMLL
AN1
PGEC1
AN0
PGED1
PMA6
AN8
18
RF3
19
RB14
OTG_ID
20
RB13
AN13
21
RB12
22
RB11
23
RB10
24
RB5
CN 7
27
RG3 (input)
D-
28
RG2 (input)
D+
VBUSON
AN12
TCK
PMA11
AN11
TDO
PMA12
AN10
TMS
PMA13
AN5
RD3
RC12
OSC1
31
RC15
OSC2
34
35
36
37
38
RD2
RC13
CN 1
RC14
CN0
RF4
CN17
RF5
CN18
RD11
INT4
RD0
INT0
39
RD4
41
RD5
42
43
44
46
47
RD6
CN15
RD7
CN16
RD9
INT2
RD10
INT3
RD1
SDA3
SDI3
U1TX
PMA10
30
33
SDO3
TDI
29
32
SCL3
PMA1
PMALH
AN14
OC4
U1RX
OC3
SOSCI
T1CK
SOSCO
SDA5
SDI4
U2RX
PMA9
SCL5
SDO4
U2TX
PMA8
IC4
PMA14
OC1
IC5/OC5
BT_PERIODIC
WLAN_DENY
PMWR
BT_STATUS
PMRD
BT_ACTIVE
ETXERR
SDA1
SS3
nU1CTS
U4RX
SCK3
nU1RTS
U4TX
IC2
SCL1
IC3
EMDIO
PMA15
OC2
Table 2: Multifunction pad descriptions
Note: 5V tolerant pads are marked with orange. CN pins support pull-up, pull-down and GPIO notifications
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3
3.1
Power control
Power supply requirements
WF121 consists of two separate internal blocks, the microcontroller and the radio part. The blocks have
separate supply voltage inputs and the microcontroller can disable the radio part supply internally.
WF121 is designed to operate with a 3.3V nominal input voltage supplied to the two supply inputs. The
VDD_3.3V pad can be fed with a voltage between 2.3V and 3.6V and is used to power the internal
microcontroller. The VDD_PA pad can be supplied with a voltage between 2.7V and 4.8V and supplies the RF
power amplifier and the internal switch-mode converter powering the Wi-Fi digital core.
In lithium battery powered applications, VDD_PA can be connected directly to the battery, while a regulator is
needed to supply the VDD_3.3V with a lower voltage, as needed by the design.
The VDD_PA supply should be capable of providing at least 350mA, though the average consumption of the
module will be much less than that. The VDD_3.3V supply will draw a peak current of less than 100mA, not
including current drawn from the GPIO pins. The PA supply should preferably be bypassed with a 10 to 100µF
capacitor to smooth out the current spikes drawn by the Wi-Fi power amplifier. External high frequency
bypassing is not needed, the module contains the needed supply filtering capacitors.
Note that there is about 20µF worth of ceramic capacitors on the VDD_PA line inside the module. When using
low drop linear regulators to generate a regulated supply for the VDD_PA line, the stability of the regulator
with the low ESR provided by these capacitors should be checked. Many linear regulators (and some
switched mode ones) are not stable with ceramic output capacitors.
3.2
Power saving functionality
In Wi-Fi client mode, the WF121 radio core automatically powers on the RF circuitry only when needed. The
Wi-Fi core processors support automatic sleep modes when not communicating actively, allowing very low
idle consumption. When used as an access point, the radio core must receive constantly and cannot enter
sleep modes.
The WF121 main processor automatically enters an idle mode after a timeout period whenever it is not
actively executing anything, lowering its consumption to about a third of the full while allowing instant wakeup.
When the power saving functions are enabled in the hardware configuration script, the processor will after a
pre-set timeout enter a deeper sleep mode to lower the consumption to much lower levels, but will take a few
milliseconds to wake up from and needs an interrupt to wake up.
Keeping the WF121 associated with an access point with the power saving modes enabled will allow relatively
fast response times with a low power consumption, but in some applications the consumption can be reduced
further. Unassociating the Wi-Fi will allow fast re-association with lower idle consumption in applications where
the module needs to transfer data only occasionally, while for applications where the absolute minimum
consumption is desired and the communication intervals are long, the Wi-Fi section of the module can be fully
powered off by disabling the module internal switch mode converter feeding the Wi-Fi core. Powering the WiFi down fully will require a full reinitialization of the Wi-Fi core, and will take several seconds before
associating with an access point.
The power saving modes are user configurable and controllable. For more information see the firmware
documentation.
3.3
Reset
WF121 can be reset by the MCLR-pin (active low), system power up, the internal brown-out detector or the
internal watchdog timer.
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4
Microcontroller
WF121 contains a Microchip PIC32-series 32 bit microcontroller with a MIPS M4K core. At a maximum clock
frequency of 80 MHz the core can reach a performance of 125 DMIPS while keeping low power consumption.
The microcontroller used in WF121 contains 512kB of Flash memory and 128kB of SRAM.
Most peripheral features are directly provided by the microcontroller and for low level information and detailed
descriptions please refer to the material and datasheets of the PIC32MX695H.
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5
5.1
Interfaces
General Purpose I/O pins
To see which GPIOs are multiplexed with which features, please refer to Table 2.
WF121 contains a number of pads that can be configured to be used as general purpose digital IO’s, analog
inputs or for various built-in functions. Provided functions include a Full Speed USB-OTG port, three I2C-ports,
two SPI-ports, two to four UART’s, Ethernet MAC with RMII connection and various timer functions. Some of
the pads are 5V tolerant. All GPIO pads can drive currents of up to +/- 25 mA.
Four pins are available for implementing a coexistence scheme with a Bluetooth device. The exact order and
function as well as the coexistence system desired is software configurable, with the default pad bindings
shown in Table 3 for a Unity-3e+ coexistence scheme. If the pads are bound to WiFi chip pins, the CPU pins
associated with the pads must be set to inputs.
5.2
Serial ports
Pad number
UART 1
UART 2
UART 4
UART 5
17
nCTS
RX
19
nRTS
TX
29
TX (output)
32
RX (input)
35
RX
36
TX
44
nCTS (input)
RX
47
nRTS (output)
TX
Table 3: Serial port pads
Two UART’s are provided with RTS/CTS-handshaking. If handshaking is not needed, up to four UART’s can
be implemented. Speeds up to 20 Mbps are possible, but the higher bit rates might require the use of an
external crystal for sufficient clock accuracy. The serial ports can also be used as host connections when
using an external microcontroller.
For details on the hardware details of the serial port, please refer to the PIC32 Family Reference Manual on
UART.
To see what other functions are present on the same pins, please refer to Table 2.
.
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5.3
I2C/SPI
2
Pad number
IC
SPI
17
SS4 – Slave select SPI 4
19
SCK4 - Clock SPI 4
2
29
SCL3 – Clock I C 3
32
SDA3 – Data I C 3
35
SDA5 – Data I C 5
36
SCL5 – Clock I C 5
44
SDA1 – Data I C 1
46
SCL1 – Clock I C 1
SDO3 – Data out SPI 3
2
SDI3 – Data in SPI 3
2
SDI4 – Data in SPI 4
2
2
SDO4 – Data out SPI 4
SS3 – Slave select SPI 3
2
SCK3 – Clock SPI 3
47
Table 4: Pads for I2C and SPI
2
Up to three I C-ports and up to two SPI ports can be implemented, mostly multiplexed on the same pins
2
together and with the UART signals. The I C ports support 100 kHz and 400 kHz speed specifications, while
the SPI can be operated at up to 40 Mbps. The SPI ports are also available for use as a host connection for
use with an external microcontroller.
For details on the SPI/I2C hardware, please refer to Microchip documentation on SPI and I2C.
To see what other functions are present on the same pins, please refer to Table 2.
5.4
USB On-The-Go
Pad number
Function
Description
18
OTG_ID
USB-OTG mode identify line
25
VBUS
USB bus supply input
27
D-
Data -
28
D+
Data +
24
VBUSON
USB bus supply switch enable in host mode
Table 5: USB pads
The module contains a USB-OTG system with an integrated transceiver. Full Speed (12 Mbps) USB 2.0
profile is supported in device mode, while the host system can operate in Low Speed and Full Speed modes.
For host use an external switch can be implemented to provide switched power for the connected device. Pad
number 24 can be dedicated to control this switch. The USB device can be used as a host connection,
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although the embedded (simplified) USB-OTG may not be able to support every kind of USB system, like
hubs.
Using the USB connection requires an external crystal for sufficient clock accuracy.
For details on the USB hardware operation please refer to the Microchip reference guide on USB.
Other functions are present on the same pins; please refer to Table 2 for details.
5.5
Ethernet
Pad number
Function
Description
2
EMDC
Management bus clock
3
ERXD1
Receive data 1
4
ERXD0
Receive data 0
5
ECRSDV
Receive data valid
6
EREFCLK
Reference clock
7
ERXERR
Receive error
10
ETXEN
Transmit enable
11
ETXD0
Transmit data 0
12
ETXD1
Transmit data 1
42
ETXERR
Transmit error
47
EMDIO
Management bus data
Table 6: Ethernet pads
An RMII interface to an external Ethernet PHY is available. The PHY should supply EREFCLK with a 50 MHz
RMII reference clock. Other functions are present on the same pads; please refer to Table 2 for details. For
more details on the Ethernet operation, please refer to the Microchip reference guide on Ethernet MAC.
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5.6
Analog inputs
Pad number
Function
2
AN15
14
AN1
15
AN0
17
AN8
19
AN14
20
AN13
21
AN12
22
AN11
23
AN10
24
AN5
Table 7: ADC pads
The microcontroller provides a 10-bit Analog to digital converter (ADC) with sampling speeds up to 1MSps.
The measurement can be done on any of the input pins listed in the table above. For further information see
the PIC32MX695H data sheet and related documents.
For details on the ADC operation, please refer to the Microchip reference guide on ADC.
5.7
Timers
The module processor contains 5 timers with various functions including capture & compare. For more
information see the PIC32MX695H data sheet.
5.8
Parallel master port
An 8-bit master/slave port is also available for transferring parallel data at a high speed to or from the module
microcontroller. For more information, see Microchip reference guide on Parallel Master Port.
5.9
Microcontroller programming interface
Pad number
Pad function
Description
13
MCLR
Reset
14
PGEC1
Programming Clock
15
PGED1
Programming Data
20
TDI
JTAG Test Data In
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21
TCK
JTAG Test Clock
22
TDO
JTAG Test Data out
23
TMS
JTAG Test Machine State
Table 8: Programming and JTAG pads
An ICSP (In-Circuit Serial Programming) interface (PGEC1, PGED1, MCLR) is provided to allow device reflashing using a Microchip tool. A JTAG connection is also provided which can be used for system debugging
purposes or device programming. For information on JTAG operation, please refer to Microchip
documentation.
5.10
RF Debug Interface
Pad number
Pad function
Description
52
SPI_MISO
RF Debug data out
53
SPI_CLK
RF Debug clock
54
SPI_MOSI
RF Debug data in
55
SPI_CS
RF Debug chip select
Table 9: RF Debug SPI pads
Four pads are provided for the debug interface of the WiFi chipset in the module bottom. This is meant for RF
calibration and testing during module production and product certification measurements. These should in
most applications be left unconnected, but should be taken into account when doing the application board
layout. Avoid placing vias or signals without a solder mask under these pads. If separate radiated emission
compliance measurements need to made for the application, these should be connected to a header. More
information on the certification measurements can be obtained from Bluegiga support.
5.11
Bluetooth co-existence
Bluetooth coexistence systems allow co-located WiFi and Bluetooth devices to be aware of each other and to
avoid simultaneous transfers that would degrade link performance. The most common coexistence schemes
combine host driver-side prioritizing with hardware connections between the different radio devices where the
hardware interface is used to communicate the exact timings for driver pre-defined events.
WF121 has up to 4 pins available for implementing the hardware connection, but as the internal host
processor is not running the Bluetooth stack too, it is not possible to implement any priorities for the separate
radio devices. The hardware connections by themselves will still enable a crude form of coexistence, with the
Wi-Fi side controlling the communications.
Wi-Fi data will always have priority over Bluetooth data, and with high duty cycle Wi-Fi transfers (low bit rate,
high throughput) the Bluetooth might not be able to transfer any data. Mostly however the Wi-Fi duty cycle will
be less than 100% and the Bluetooth device may be able to transfer significant amounts of data.
5.12
Antenna switch for Bluetooth coexistence
WF121 supports sharing the integrated antenna or antenna connector with a Bluetooth device through the
BT_RF pad. The module contains a bypass switch to route the Bluetooth signal directly to the antenna, and
supports using the internal LNA for Bluetooth reception. The switch is controlled through the coexistence
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interface. Use of the antenna switch requires the use of Unity-3e scheme, as there are not enough pins
available to implement a separate antenna control which requires two extra signals.
While antenna sharing will ease antenna placement and general application design, it will also cause a
number of problems.
There will be additional losses on the Bluetooth path due to the switch, reducing range.
Throughput reductions due to the coexistence operation will be increased and there may occur Wi-Fi
timeouts due to Bluetooth scans reserving the full use of the antenna.
Wi-Fi power-off may also cause poor ranges for the Bluetooth device.
Sharing a single antenna will require a re-certification for at least FCC of both modules as the RF
paths will have changed significantly from the scheme specified in the original certification setups.
For use with CSR-based Bluetooth (BC4 to BC6 with firmware version 21 or later, BC7 and onwards with all
versions), Unity-3e is recommended as the coexistence scheme. Unity-3e is an enhanced version of the
traditional 3-wire Unity-3 –scheme that uses tighter timings and uses the three control lines also for antenna
switch control, removing the need for the two separate switch control signals.
The BT_PERIODIC signal is related to the Unity+ -standard, which allows more reliable audio throughputs,
but it is not currently supported for WF121.
Pad number
Function
37
BT_PERIODIC
38
WLAN_DENY
39
BT_STATUS
41
BT_ACTIVE
Table 10: Bluetooth co-existence interface
Industry standard 3-wire and 4-wire, as well as Unity-3, Unity-4, and Unity-3e coexistence schemes are
supported and the associated signals can be assigned to the GPIO pads. In default mode these pins are tied
to CPU GPIO functions. Antenna sharing is possible with the Unity-3e scheme.
For more detailed information about implementing co-existence, see WF111 datasheet.
5.13
CPU Clock
Pad number
Function
Description
30
OSC1
External crystal input
31
OSC2
External crystal output
Table 11: Clocking pads
WF121 uses an internal 26 MHz crystal as the WiFi reference clock. The internal processor uses an
integrated 8MHz RC oscillator and associated phase locked loop (PLL) to create its clock signals, but cannot
share the internal crystal-stabilized WiFi clock. The internal CPU uses a PLL to create an 80MHz core clock.
To use the USB functionality an external crystal and the associated capacitors must be implemented on the
application board to provide a sufficiently accurate clock. A crystal with its associated capacitors can be
connected to pads OSC1 and OSC2. If an external crystal is not needed, these pads are available for GPIO
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use. The USB clock synthesizer requires an internal reference frequency of 4MHz, so the crystal for USB use
must be a multiple of 4MHz.
An external oscillator can also be used to generate the CPU clock frequency. The voltage levels should be
3.3V logic level.
Note: The present WF121 default firmware only supports 8MHz crystals or oscillators.
The internal clock divider generating the reference frequency for the internal PLL’s cannot be changed by the
firmware, and to support automatic switchover between the internal RC oscillator and the external crystal, the
default firmware needs an 8MHz clock. A custom firmware can be ordered with support for desired
frequencies for easier crystal availability, for achieving desired UART baud rates and other applications.
The Ethernet connection requires the external PHY to provide the 50MHz RMII reference clock. A crystal is
not required for the module CPU for Ethernet operation.
5.14
32.768 kHz External Reference Clock
Pad number
Function
Description
33
SOSCI
External 32.768 kHz crystal input
34
SOSCO
External 32.768 kHz crystal output
Table 12: Slow clock
The module contains integrated RC oscillators for sleep timing, one in the WiFi chipset, one in the CPU. The
sleep clocks are used to periodically wake up the module while in power save modes. If more accurate timing
is required, an external 32.768 kHz crystal and the associated capacitors can be placed to pads SOSCI and
SOSCO. If an accurate sleep clock is not needed, the pads are available for GPIO use.
An external oscillator can also be used to generate the sleep clock. The voltage levels should be 3.3V logic
level.
This low frequency clock is shared for both the CPU and the WiFi chipset. The default WiFi configuration uses
only the internal oscillator, if support for a crystal stabilized WiFi sleep clock is required, please contact
Bluegiga technical support.
The Wi-Fi packet timing during active data transfer is derived from the internal 26MHz crystal and so is
unaffected by the tolerances of the sleep clock.
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6
Example schematic
Figure 2: Minimal system required for UART host connection
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7
7.1
802.11 Radio
Wi-Fi Receiver
The receiver features direct conversion architecture. Sufficient out-of-band blocking specification at the Low
Noise Amplifier (LNA) input allows the receiver to be used in close proximity to GSM and WCDMA cellular
phone transmitters without being desensitized. High-order baseband filters ensure good performance against
in-band interference.
7.2
Wi-Fi Transmitter
The transmitter features a direct IQ modulator. Digital baseband transmit circuitry provides the required
spectral shaping and on-chip trims are used to reduce IQ modulator distortion. Transmitter gain can be
controlled on a per-packet basis, allowing the optimization of the transmit power as a function of modulation
scheme.
The internal Power Amplifier (PA) has a maximum output power of +15dBm for IEEE 802.11g/n and +17dBm
for IEEE 802.11b. The module internally compensates for PA gain and reference oscillator frequency drifts
with varying temperature and supply voltage.
7.3
Regulatory domains
WF121 uses the IEEE 802.11d standard to select the available channels based on the regulatory domain
setting of the access point.
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8
Firmware
WF121 incorporates firmware which implements a full TCP/IP stack and Wi-Fi management. Exact features
will depend on the firmware version used. Please see the documentation of the firmware for exact details.
There are three main ways to use the module: Host controlled, script controlled or native application
controlled.
Host controlled means an external host is physically connected to the module and it sends simple commands
to the module and one of several different host interfaces can be used. The module provides high level APIs
for managing Wi-Fi as well as data connections. Bluegiga provides a thin API layer (BGLib) written in ANSI C
for the host which can take care of creating and parsing the messages sent over the transport. For evaluation
purposes GUI tools and a library for python are also provided.
Host
Application
BGLib
(implements BGAPI)
BGAPI
UART / USB / SPI
HTTP, FTP,
SMTP etc.
DHCP, TFTP,
DNS etc.
TCP
UDP
MLME
IP
802.2 LLC
802.11 MAC
802.11 PHY
Figure 3: WF121 software
Data can be routed either through the API or through another physical interface. For example if the first UART
is used for sending and receiving command events, a TCP/IP socket can be bound to the second UART and
data written to the UART will seamlessly be passed to the TCP/IP socket. For information about the latest
capabilities of the firmware, please refer to the WF121 API reference documentation accompanying it.
The module can also be controlled by a script running on the module. This is especially useful for simple
applications as it eliminates the need for a host controller and can drastically cut development time. In
combination with a host it can also be used automate certain features such as the serial to TCP/IP
functionality described above.
Native application development is also possible as the stack will not require all of the available flash or
memory. Please see the material accompanying the firmware release about more details of this option.
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9
9.1
Host interfaces
UART
The module can be controlled over the UART interface. In order for the communication to be reliable,
hardware flow control signals (RTS and CTS) must be present between the host and the module. When using
high UART transfer speeds (between 1 and 20Mbps) an external crystal is required for sufficient clock
accuracy.
9.2
USB
When using the USB host interface, the module will appear as a USB CDC/ACM device enumerating as
virtual COM port. The same protocol can be used as with the UART interface.
9.3
SPI
Please refer to the Bluegiga WF121 API reference documentation supplied with the firmware regarding using
SPI as the Host interface.
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10
Electrical characteristics
10.1
Absolute maximum ratings
Rating
Min
Max
Unit
Storage Temperature
-40
85
°C
VDD_PA
-0.3
6
V
VDD_3.3V
-0.3
3.6
5V tolerant GPIO Voltages
-0.3
5.5
V
VSS-0.3
VDD_3.3V+0.3
V
Maximum output current sourced or sunk by any GPIO pad
25
mA
Maximum current on all GPIO pads combined
200
mA
Other Terminal Voltages
Table 13: Absolute maximum ratings
10.2
Recommended operating conditions
Rating
Min
Max
Unit
Operating Temperature Range *
-40
85
°C
VDD_3.3V
2.3
3.6
V
VDD_PA
2.7
4.8
V
Table 14: Recommended operating conditions
*Note: The module may heat up depending on use, at high constant transmit duty cycles (high throughput,
low bitrate for more than a few seconds) the maximum operating temperature may need to be derated to keep
below the maximum ratings.
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10.3
Input/output terminal characteristics
10.4
Digital
Digital terminals
Min
Typ
Max
Unit
VIL input logic level low 1.7V ≤ VDD ≤ 3.6V
VSS-0.3V
-
0.15VDD
V
VIH input logic level high 1.7V ≤ VDD ≤ 3.6V
0.8VDD
-
VDD+0.3V
V
-
-
0.4
V
2.4
-
VDD
V
Input voltage levels
Output voltage levels
VOL output logic level low, Vdd = 3.6 V, Iol = 7 mA
VOH output logic level high Vdd = 3.6 V, Ioh = -12 mA
Table 15: Digital terminal electrical characteristics
Frequency
o
Min
Typ
max
32.748
32.768
32.788
kHz
Deviation @25 C
-20
+20
ppm
Deviation over temperature
-150
+150
ppm
Duty cycle
30
50
Rise time
70
%
50
ns
Input high level
0.625Vdd
Vdd+0.3
V
Input low level
-0.3
0.25Vdd
V
Table 16: External sleep clock specifications
10.5
Reset
Power-on Reset
Min
Typ
Max
Unit
Power on reset threshold
1.75
-
2.1
V
VDD rise rate to ensure reset
0.05
-
115
V/ms
Table 17: Power on reset characteristics
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10.6
Power consumption
Consumption
type
Current
Unit
Supply
domain
Total maximum
400
mA
both
CPU average
100
mA
VDD_3.3V
Typical average program execution consumption
CPU idle
35
mA
VDD_3.3V
Idle mode, instant wakeup
CPU sleep
60
µA
VDD_3.3V
Sleep mode, clocks off, WDT on, wakeup in milliseconds
68
mA
Wi-Fi core idle
110
µA
Wi-Fi PA
240
Wi-Fi LNA
Wi-Fi total sleep
Wi-Fi
active
core
VDD_PA
Description
Absolute peak current during packet transmission (