SC73P1601MTR

SC73P1601 4-BIT MCU FOR REMOTE CONTROLLER(OTP TYPE) DESCRIPTION SC73P1601 is one of Silan’ 4-bit CMOS single-chip micros controllers for infrared remote control transmitters (IRCTs). It can be implemented in various IRCTs circuits by OTP program. And it is compatible with SC73C1602 on software and package. SOP-20-300-1.27 SOP-20-375-1.27 FEATURES * Wide operating voltage (2.0~4.0V), and low static power consumption ( VPOC. Here, VDD: power supply voltage. VPOC: POC detection voltage. VDD 3.6V 2.0V VPOC Operating ambient temperature Tamb=-20 °C~+75°C POC detection voltage VPOC =1.4V~1.6V 0V Internal reset signal Reset Operation mode Note 1 Note 2 HANGZHOU SILAN MICROELECTRONICS CO.,LTD Http: www.silan.com.cn REV:1.4 2009.08.03 Page 9 of 22 SC73P1601 Notes. 1. After the circuit is power on, there is a short oscillation stabilization wait time before the circuit is in operation mode. The oscillation stabilization wait time is about 216/fmain. 2. The POC circuit generates an internal reset signal when the power supply voltage has fallen to a certain value in working mode. 19. Instruction Cycle Instructions and internal operations are executed in synchronization with the main clock. The minimum time of carrying out a complete instruction is called the instruction cycle. SC73P1601 has 1 and 2-cycle two kind of instructions. An instruction cycle consists of 5 states (STCLK1 to STCLK5). Each state consists of 1 main clock. Therefore, the instruction cycle time is 5/fmain [s]. HANGZHOU SILAN MICROELECTRONICS CO.,LTD Http: www.silan.com.cn REV:1.4 2009.08.03 Page 10 of 22 SC73P1601 INSTRUCTION SETS 1. Transmit instruction Instruction LD A, LL LD A, B LD A, H LD A, D LD A, @LL LD A, #k LD CL1, A LD CL0, A LD CH1, A LD CH0, A LDH A, @BD LDL A, @BD LDS A, @BD LDH @LL, @BD LDL @LL, @BD LDS @LL, @BD LD LL, A LD LL, #k LD @LL, A LD @LL, #k LD D, A LD H, A LD B, A LD PR, A LD PR2, A LD TM, A LD A, TM 1 2 3 4 5 6 7 8 9 10 LD A, LL LD A, D LD A, H LD A, B LD A, @LL LD A, #k LDL A, @BD LDH A, @BD LDS A, @BD LDL @LL, @BD A ← LL A←B A←H A←D A ← RAM(LL) A←k CL1 ← A CL0 ← A CH1 ← A CH0 ← A A ← ROM(BD)7-4 A ← ROM(BD)3-0 A ← ROM(BD)8 RAM(LL) ← ROM(BD)7-4 RAM(LL) ← ROM(BD)3-0 RAM(LL) ← ROM(BD)8 LL ← A LL ← k RAM(LL) ← A RAM(LL) ← k D←A H←A B←A PR ← A PR2 ← A TM ← A A ← TM Load values in the LL register to the accumulator. Load values in the D register to the accumulator. Load values in the H register to the accumulator. Load values in the B register to the accumulator. Load the contents of RAM pointed at by the LL ( LL & LH) register to accumulator. Load the 4 bit immediate K to accumulator. Load the lower 4 bit of ROM data pointed at by the BHD to accumulator. Load the higher 4 bit of ROM data pointed at by the BHD to accumulator. Load the highest 1 bit of ROM data pointed at by the BHD to accumulator Load the lower 4 bit of ROM data pointed at by the BHD to RAM pointed at by the LL register. Operation CF ------------------------------------------------------SF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Cycle 2 2 2 2 1 1 2 2 2 2 2 2 2 2 2 2 2 1 1 1 2 2 2 2 2 2 2 HANGZHOU SILAN MICROELECTRONICS CO.,LTD Http: www.silan.com.cn REV:1.4 2009.08.03 Page 11 of 22 SC73P1601 11 LDH @LL, @BD Load the higher 4 bit of ROM data pointed at by the BHD to RAM pointed at by the LL register. 12 LDS @LL, @BD Load the highest 1 bit of ROM data pointed at by the BHD to RAM pointed at by the LL register. 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 LD LL, A LD LH, A LD LL,#K LD @LL, A LD @LL, #k LD D, A LD H, A LD B, A LD CL1, A LD CL0, A LD CH1, A LD CH0, A LD PR, A LD PR2, A LD TM, A LD A, TM Load the contents of the accumulator to the LL register. Load the contents of the accumulator to the LH register. Load immediate K to the LL register. Load the content of the accumulator to the RAM pointed at by the LL register. Load the immediate K to RAM pointed at by the LL register. Load the content of the accumulator to the D register. Load the content of the accumulator to the H register. Load the content of the accumulator to the B register. Load the content of the accumulator to the CL1 register. Load the content of the accumulator to the CL0 register. Load the content of the accumulator to the CH1 register. Load the content of the accumulator to the CH0 register. Load the content of the accumulator to the port register(PR). Load the content of the accumulator to the port register(PR2). Load the content of the accumulator to the timer register. Load the content of the timer register to the accumulator. Execution the above transmit instructions will not affect the carry flag, and the status flag remains 1. 2. Input/output instructions Instruction LD A, %p LD @LL, %p LD %p, A LD %p, @LL Operation A ← PORT(p) RAM(LL) ← PORT(p) PORT(p) ← A PORT(p) ← RAM(LL) CF --------SF /Z /Z 1 1 Cycle 2 2 2 2 a. b. c. d. LD A, %P LD @LL, %p LD %p, A LD %p, @LL Move the value of port(P) to the accumulator Move the value of port(P) to RAM pointed at by the LL register. Move the contents of the accumulator to port (P). Load the contents of RAM pointed at by the LL register to port(P). The above four input/output instructions are used mostly for port operation, the two read instructions will affect the status flag SF. HANGZHOU SILAN MICROELECTRONICS CO.,LTD Http: www.silan.com.cn REV:1.4 2009.08.03 Page 12 of 22 SC73P1601 3. Arithmetic and logical instructions Instruction ADD A, @LL ADDC A, @LL ADD A, #k ADD LL, #k SUBRC A, @LL INC @LL DEC @LL INC LL DEC LL INC D INC H INC B DEC D DEC H DEC B AND A, @LL OR A, @LL XOR A, @LL Operation A ← A+RAM(LL) A ← A+RAM(LL)+CF A ← A+k LL ← LL+k A ← RAM(LL)-A-/CF RAM(LL) ← RAM(LL)+1 RAM(LL) ← RAM(LL)-1 LL ← LL+1 LL ← LL-1 D ← D+1 H ← H+1 B ←B+1 D ← D-1 H ← H-1 B ← B-1 A ← A&RAM(LL) A ← A | RAM(LL) A ← A^RAM(LL) CF --C ----C --------------------------SF /C /C /C /C C /C C /C C /C /C /C C C C /Z /Z /Z Cycle 1 1 1 2 1 1 1 2 2 2 2 2 2 2 2 1 1 1 1. 2. 3. 4. ADD A, @LL ADDC A, @LL ADD A,#K ADD L,#K Add the contents of RAM pointed at by the LL to accumulator, store the sum in the ACC. This operation will affect SF, SF=/CF. Add the contents of RAM pointed at by the LL register to accumulator with carry. Store the carry bit in the CF. This operation will affect SF, SF=/CF. Add immediate K to accumulator. Store the sum in the ACC. This will affect SF, SF=/CF. Add immediate K to the LL register. Store the sum in the LL. This will affect SF, SF=/CF. Subtract instruction with borrow(the complement of carry). Subtract the contents of the accumulator from the contents of RAM pointed at by the LL register, subtract the complement of the carry bit, then store the results in the accumulator, transfer the carry bit to the CF, this will affect SF and CF, SF=CF. Increment instruction. Increment the contents of RAM pointed at by the LL register by 1. This will affect SF, SF=/CF. Decrement instruction. Decrement the contents of RAM pointed at by the LL register by 1. This will affect SF, SF=CF. Increment instruction. Increment the contents of the D register by 1. This will affect SF, SF=/CF. Increment instruction. Increment the contents of the H register by 1. This will affect SF, SF=/CF. Increment instruction. Increment the contents of the B register by 1. This will affect SF, SF=/CF. 5. SUBRC A, @LL 6. 7. 8. 9. 10. INC @LL DEC @LL INC D INC H INC B HANGZHOU SILAN MICROELECTRONICS CO.,LTD Http: www.silan.com.cn REV:1.4 2009.08.03 Page 13 of 22 SC73P1601 Decrement instruction. Decrement the contents of the D register by 1. This will affect SF, SF=CF. Decrement instruction. Decrement the contents of the H register by 1. This will affect SF, SF=CF. Decrement instruction. Decrement the contents of the B register by 1. This will affect SF, SF=CF. Increment instruction. Increment the contents of the LL register by 1. This will affect SF, SF=/CF. Subtract 1 from the content in register LL. SF is affected, SF=/CF. The contents of the accumulator and RAM pointed at by the LL register are ANDed and the results are stored in the accumulator. SF changed, SF=/Z. The contents of the accumulator and RAM pointed at by the LL register are ORed and the results are stored in the accumulator. SF changed, SF=/Z. The contents of the accumulator and RAM pointed at by the LL register are XORed and the results are stored in the accumulator. SF changed, SF=/Z. 11. 12. 13. 14. 15. 16. 17. 18. DEC D DEC H DEC B INC LL DEC LL AND A, @LL OR A, @LL XOR A,@LL 4. Bit operation instructions Instruction CLR @LL, b SET @LL, b TEST @LL, b a. b. c. CLR @LL, b SET @LL, b TEST @LL, b Operation RAM(LL)b←0 RAM(LL)b←1 SF←/RAM(LL)b CF ------SF 1 1 * Cycle 2 2 2 Clear the B-bit of the RAM pointed at by the LL register. Set the B-bit of the RAM pointed at by the LL register to be 1. Test the B-bit of the RAM pointed at by the LL register. If this bit is1, the SF is set to 0; otherwise, the SF is set to 1. 5. Carry operation instructions Instruction CLR CF SET CF TESTP CF a. b. c. CLR CF SET CF TESTP CF CF←0 CF←1 SF←CF Clear the carry flag to logic zero. Set the carry flag to logic 1. Test the carry flag, send the carry flag to SF. Operation CF 0 1 --SF 1 1 * Cycle 2 2 1 HANGZHOU SILAN MICROELECTRONICS CO.,LTD Http: www.silan.com.cn REV:1.4 2009.08.03 Page 14 of 22 SC73P1601 6. Branch instructions Instruction BSS label JMPS label instruction Set for details. BSS label Jump to destination address label with range of 128 bytes JMPS label Jump to destination address label with range of 2K program. Symbol description of above instructions: a. b. c. d. label #k b %p Destination address of jump Immediate (0~15) Bit addressing (0~3) Port address Operation CF ----SF 1 1 Cycle 2 3 Jump instruction is active only when SF is 1, or else next instruction is executed. Please read the Pseudo- 7. Subroutine instructions Instruction CALLS label RET 01FH. 8. Other instructions Instruction HOLD NOP TMRST a. b. c. HOLD NOP TMRST Reset timer counter Operation CF ------SF 1 ----Cycle 1 1 1 Operation CF ----SF ----Cycle 2 2 When executing subroutine call and return instructions, the subroutine starting address is limited from 000H to After executing this instruction, MCU is in the power–save mode, the clock stops oscillation and power consumption reduces dramatically. Null operation. It doesn’ affect anything. t Timer clear command. It will clear all values of the timer to 0. This instruction is often used to reset WDT in program. 9. Pseudoinstruction ORG Format: [Label:] ORG address Function: Redefine following start address Expression: Label: selectable Address: redefined address, can be binary, decimal or hexadecimal. Redefined address is an absolute address which could not be returned back. That is, the redefined address HANGZHOU SILAN MICROELECTRONICS CO.,LTD Http: www.silan.com.cn REV:1.4 2009.08.03 Page 15 of 22 SC73P1601 should be higher than that above, or a fault is occurred during compiling. 000H is defaulted if no address is set by ORG instruction. Example: ORG 0100H EQU Format: Symbol EQU digital Function: Define a digital as a symbol. Symbol ＝ digital. Expression: Symbol should be legal, and digital should be binary, decimal or hexadecimal. There is no colone before EQU in definition, and it can only useful after the definition. Example: Data1 EQU 12H Data2 EQU 1001B DB Format: [Label:] [num] DB data Function: Define data with number of num. Expression: Label: selectable Num: indicates number of data, default value is 1. Data: data to be written to ROM. It should smaller than 0X200 as ROM is only 9-bit.lower 9-bit value of data is taken with warning if it is more than 0x200.( only lower 8-bit is taken if the instruction is used for data table) Example: DB 12H ; Define one data ; Define one data DB 10010B 12H DB 55H ; Define continuous 18 data JMPS Format: [Label:] JMPS address Function: Jump in ROM. Expression: Label: selectable Address can be a digital, symbol defined by EQU or the address symbol. Combined by: LD MBR, #k BSS label HANGZHOU SILAN MICROELECTRONICS CO.,LTD Http: www.silan.com.cn REV:1.4 2009.08.03 Page 16 of 22 SC73P1601 The instruction is 2-byte long, and it can jump to any position in the ROM. Example: JMPS MAIN JMPS 100H VENT Format: VENT label Function: Define the entry and reset address of sub-program. Expression: Label is the sub-program name or the address symbol. Use VENT to specify the entry and reset address of the sub-program, and it must be at the beginning of the program. The first VENT denotes the reset address and the following VENT instructions denote the entry of the sub-program. In general, 16 sub-programs can be defined at most. All the sub-programs called by CALL instruction should be defined in VENT, or else errors will occur in assembly. Example: VENT MAIN VENT SUB1 VENT SUB2 … … … … .. ORG 100H MAIN: NOP NOP CALLS SUB1 CALLS SUB2 …………. SUB1: …………. SUB2: …………. END Format: END Function: Use the END instruction to end the assembly of a program. Expression: END pseudoinstruction ends the assembly of a program and the content after END will not be processed by assembler. If END is omitted, the assembler will process all the lines of the source file. Example: END HANGZHOU SILAN MICROELECTRONICS CO.,LTD Http: www.silan.com.cn REV:1.4 2009.08.03 Page 17 of 22 SC73P1601 Remote control flow chart: HANGZHOU SILAN MICROELECTRONICS CO.,LTD Http: www.silan.com.cn REV:1.4 2009.08.03 Page 18 of 22 SC73P1601 TYPICAL APPLICATION CIRCUIT HANGZHOU SILAN MICROELECTRONICS CO.,LTD Http: www.silan.com.cn SC73P1601 REV:1.4 2009.08.03 Page 19 of 22 SC73P1601 PACKAGE OUTLINE SSOP-20-300-0.65 Unit: mm SOP-20-300-1.27 Unit: mm 0.15± 0.05 1.27 12.70± 0.25 0.45 2.25MAX 11.43 HANGZHOU SILAN MICROELECTRONICS CO.,LTD Http: www.silan.com.cn REV:1.4 2009.08.03 Page 20 of 22 SC73P1601 PACKAGE OUTLINE (Continued) SSOP-20-225-0.65 Unit: mm SOP-20-375-1.27 Unit: mm HANGZHOU SILAN MICROELECTRONICS CO.,LTD Http: www.silan.com.cn REV:1.4 2009.08.03 Page 21 of 22 SC73P1601 MOS DEVICES OPERATE NOTES: Electrostatic charges may exist in many things. Please take following preventive measures to prevent effectively the MOS electric circuit as a result of the damage which is caused by discharge: l l l l The operator must put on wrist strap which should be earthed to against electrostatic. Equipment cases should be earthed. All tools used during assembly, including soldering tools and solder baths, must be earthed. MOS devices should be packed in antistatic/conductive containers for transportation. Disclaimer: • • Silan reserves the right to make changes to the information herein for the improvement of the design and performance without further notice! All semiconductor products malfunction or fail with some probability under special conditions. When using Silan products in system design or complete machine manufacturing, it is the responsibility of the buyer to comply with the safety standards strictly and take essential measures to avoid situations in which a malfunction or failure of such Silan products could cause loss of body injury or damage to property. • Silan will supply the best possible product for customers! HANGZHOU SILAN MICROELECTRONICS CO.,LTD Http: www.silan.com.cn REV:1.4 2009.08.03 Page 22 of 22