SC92031L

SC92031 10/100 MBPS INTEGRATED PCI ETHERNET MEDIA ACCESS CONTROLLER AND PHYSICAL LAYER DESCRIPTION The SC92031 is a highly-integrated and cost-effective single-chip Fast Ethernet NIC controller. It fully complies with PCI 2.2 and IEEE 802.3u 100Base-T specifications. It supports both half-duplex and full duplex operation, as well as for full-duplex flow control. It also supports Advanced Configuration Power management Interface (ACPI), PCI power management and remote wake-up events including AMD Magic Packet, Link Change, and Microsoft® wake-up frame. The SC92031 provides glue less 32-bit bus master interface for PCI, boot ROM interface, as well as physical media interface for 100BASETX of IEEE 802.3u and 10BASE-T of 802.3. It also supports shared Boot ROM pins & clock run pin. The SC92031 supports Analog Auto-Power-down, that is, the analog part of the SC92031 can be shut down temporarily according to user requirement or when the SC92031 is in a power down state with the wakeup function disabled. PCI Vital Product Data (VPD) is also supported to provide the information that uniquely identifies hardware. The information may consist of part number, serial number, and other detailed information. To provide cost down, the SC92031 is capable of using a 25MHz crystal or OSC as its internal clock source. The SC92031 includes a PCI and Expansion Memory Share Interface for a boot ROM and can be used in diskless workstations, providing maximum network security and ease of management. The SC92031 provides a flexible multi-function mode to incorporate other PCI master devices. When in multi-function mode, the SC92031 acts as an arbiter to distinguish LAN signals from those of other devices. LQFP-100-14x14-0.5 QFP-100-14x20-0.65 ORDERING INFORMATION Device SC92031 Package QFP-100-14 X 20-0.65 SC92031L LQFP-100-14 X 14-0.5 APPLICATIONS * 10/100Mbps PCI fast Ethernet adaptor FEATURES * Integrated Fast Ethernet MAC, Physical layer and transceiver in one chip * 10 Mbps and 100 Mbps data rates * Both half duplex and full duplex available * IEEE 802.3 compliant Auto-Negotiation * Supports PCI multi-function capabilities * PCI local bus Ø Compliant to PCI Revision 2.2 Ø Supports PCI clock 15 MHz-40 MHz Ø Supports PCI target fast back-to-back transaction Ø Provides PCI bus master data transfers and PCI memory space or I/O space mapped data transfers of HANGZHOU SILAN MICROELECTRONICS CO.,LTD Http: www.silan.com.cn REV:1.0 2004.08.03 Page 1 of 38 SC92031 SC92031's operational registers Ø Supports PCI VPD (Vital Product Data) Ø Supports ACPI 1.0 and PCI power management Ver.1.1 compliant Ø Supports PCI multi-function to incorporate with other PCI master device * Supports 25MHz crystal or 25MHz OSC as the internal clock source. * Compliant to PC99 and PC2001 standards * Supports Wake-On-LAN function and remote wake-up (Magic Packet*, Link Change and Microsoft® wake-up frame) * Supports 4 Wake-On-LAN (WOL) signals (active high, active low, positive pulse, and negative pulse) * Supports auxiliary power auto-detect, and sets the related capability of power management registers in PCI configuration space * Includes a programmable, PCI burst size and early Tx/Rx threshold * Supports a 32-bit general-purpose timer with the external PCI clock as clock source, to generate timerinterrupt * Contains two large (2Kbyte) independent receive and transmit FIFOs * Advanced power saving mode when LAN function or wakeup function is not used * Uses serial EEPROM to store resource configuration, ID parameter, and VPD data * Extensive LED status support * Supports loop back capability * Supports Full Duplex Flow Control * Low-power 0.25u CMOS technology * 3.3V power supply with 5V tolerant I/Os * 100-pin QFP/LQFP package * Third-party brands and names are the property of their respective owners. BLOCK DIAGRAM HANGZHOU SILAN MICROELECTRONICS CO.,LTD Http: www.silan.com.cn REV:1.0 2004.08.03 Page 2 of 38 SC92031 ABSOLUTE MAXIMUM RATINGS (unless otherwise stated, Tamb=25°C, VSS=0V) Characteristics Supply Voltage Input/Output Voltage Operating Temperature Storage Temperature Symbol VDD VI , VO Topr Tstg Value 0 ~ 4.0 -0.5 ~ VDD+0.5 0 ~ 70 -40 ~ 125 Unit V V DC ELECTRICAL CHARACTERISTICS Characteristics Minimum High Level Output Voltage Maximum Low Level Output Voltage Minimum High Level Input Voltage Minimum Low Level Input Voltage Input Current Tri-state Output Leakage Current Average operating Supply Current Symbol VOH VOL VIH VIL IIN IOZ ICC VIN=VDD or GND VOUT=VDD or GND IOUT=0mA Test Condition IOH=-8mA IOL=8mA 0.5VDD -0.5 -1.0 -1.0 Min. 0.9VDD Typ. Max. VDD 0.1VDD VDD+0.5 0.3VDD 1.0 10 330 Unit V V V V µA µA mA Supply voltage VDD=3.0V min. to 3.6V max. PIN CONFIGURATION HANGZHOU SILAN MICROELECTRONICS CO.,LTD Http: www.silan.com.cn REV:1.0 2004.08.03 Page 3 of 38 SC92031 PIN CONFIGURATION 75 ACT 76 G_RST 77 REQB2 78 GNTB2 79 SE 80 INTAB 81 RSI_RST 82 PCI_CLK 83 VDD 84 GNTB 85 REQB 86 PMEB 87 AD31 88 AD30 89 GND 90 AD29 91 AD28 92 AD27 93 AD26 94 AD25 95 AD24 96 VDD 97 C/BE3B 98 IDSEL 99 AD23 100 1 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 CLKR 49 AUX 48 EECS 47 EECK 46 EEDI 45 EEDO 44 AD0 43 AD1 42 VDD 41 AD2 40 AD3 39 GND SC92031L 38 GND 37 AD4 36 AD5 35 AD6 34 ROM_OE 33 VDD 32 AD7 31 C/BE0B 30 GND 29 AD8 28 AD9 27 AD10 26 AD11 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 PIN DESCRIPTION Pin No. PCI Interface 82 PCI_RST When RSTB is asserted low, the SC92031 performs internal system hardware reset. RSTB must be held for a minimum of 120 ns. This PCI Bus clock provides timing for all transactions and bus phases, and 83 88, 89, 91-96, 100, 1, 3-5, 7-9, 22-29, 32, 3537, 40, 41, 43, 44 (To be continued) Symbol Description PCI_CLK is input to PCI devices. The rising edge defines the start of each phase. The clock frequency ranges from 0 to 33MHz. PCI address and data multiplexed pins. AD31-0 Pins AD31-24 are shared with Boot ROM data pins, while AD16-0 are shared with Boot ROM address pins. HANGZHOU SILAN MICROELECTRONICS CO.,LTD Http: www.silan.com.cn REV:1.0 2004.08.03 Page 4 of 38 SC92031 (Continued) Pin No. 98, 10, 20, 31 14 11 85 86 99 Symbol C/BE3-0B DEVSELB FRAMEB GNTB REQB IDSEL Description PCI bus command and byte enables. Device Select, target is driving to indicate the address is decoded. Begin and duration of bus access, driven by master device. PCI bus granted. This signal indicates that the PCI bus request of SC92031 has been accepted. PCI bus request, the SC92031 will assert this signal low to request the ownership of the bus from the central arbiter. Initialization Device Select. This pin allows the SC92031 to identify when configuration read/write transactions are intended for it. PCI interrupt request. It is asserted low when an interrupt condition occurs, as defined by the Interrupt Status, Interrupt Mask and Interrupt Enable registers. Master device is ready to data transaction. Slave device is ready to data transaction. Parity, this signal indicates even parity across AD31-0 and C/BE3-0 including the PAR pin. As a master, PAR is asserted during address and write data phases. As a target, PAR is asserted during read data phases. Data parity error is detected, driven by the agent receiving data. Address parity error. The current target is requesting the master to stop the current transaction. Power Management Event, Open drain, active low. Used by the SC92031 to 81 12 13 19 16 18 15 INTAB IRDYB TRDYB PAR PERRB SERRB STOPB Power Management/Isolation Interface 87 PMEB request a change in its current power management state and/or to indicate that a power management event has occurred. LAN WAKE-UP signal, This signal is used to inform the motherboard to execute the wake-up process. The motherboard must support Wake-On71 LWAKE LAN (WOL). There are 4 choices of output, including active high, active low, positive pulse, and negative pulse, that may be asserted from the LWAKE pin. EEPROM Interface This pin is used to notify the SC92031 of the existence of Aux. power during initial power-on or a PCI reset. This pin should be pulled high to the Aux. 49 AUX power via a resistor to detect the Aux. power. Doing so, will enable wakeup support from ACPI D3 cold or APM power-down. If this pin is not pulled high, the SC92031 assumes that no Aux. power exists. EEPROM Interface 47 46 45 48 EECK EEDI EEDO EECS EEPROM chip serial clock EEPROM chip serial data in EEPROM chip serial data out EEPROM chip select (To be continued) HANGZHOU SILAN MICROELECTRONICS CO.,LTD Http: www.silan.com.cn REV:1.0 2004.08.03 Page 5 of 38 SC92031 (Continued) Pin No. Power Pins 6,21,33,42, 84,97 67 52,60,66 2,17, 30,38,39, 51 55, 58, 63 LED Interface Symbol Description VDD VDD_IR VDDAH_RX VDDAH_CM AVDD GND VSA_RX VSA_CM AGND +3.3V (Digital) +3.3V (Analog) Ground Ground (Analog) LED0 displays for activity status. This pin will be driven with 5 Hz frequency ACT, LINK, 76,75,74,72 SPEED,DUPL EX when either effective receiving or transmitting is detected. LED1 displays for link status. LED2 displays for 100 M link status. LED3 displays for full-duplex mode. 64 65 54 53 62 61 TX+ TXRX+ RXXTAL25I XTAL25O 100/10BASE-T transmit (Tx) data 100/10BASE-T receive (Rx) data 25 MHz crystal/OSC. Input Crystal feedback output, This output is used in crystal connection only. It must be left open when X1 is driven with an external 25 MHz oscillator. Multi-Function Interface 78 79 73 REQB2 GNTB2 IDSEL2 Request2, The 2nd device will assert this pin low to request the ownership of the PCI bus. Grant2, This signal is asserted low to indicate that the central arbiter has granted ownership of the bus to the 2nd device. Initialization device select 2, Used as a chip-select during configuration read and write transactions to the 2nd device. Test And Other Pins 70 69 34 TM0 TM1 ROM_OE Chip test pin ROM Chip Select and Output Enable, This is the chip select signal and output enable for the Boot PROM. (To be continued) HANGZHOU SILAN MICROELECTRONICS CO.,LTD Http: www.silan.com.cn REV:1.0 2004.08.03 Page 6 of 38 SC92031 (Continued) Pin No. Symbol Description Clock run for PCI system. In normal operation situation, Host should assert this signal to indicate SC92031 about the normal situation. On the other hand, when the host will dessert this signal when the clock is going down to 50 CLKR a non-operating frequency. When SC92031 recognizes the de-asserted status of clockrun, then it will assert clockrun to request host to maintain the normal clock operation. When clockrun function is disabled then the SC92031 will set clockrun in tri-state. 80 56 57 68 77 SE ANTEST_A ANTEST_B PORXRS G_RST Scan chain test enable Analog test pin Power on reset output Global reset input pin REGISTER DESCRIPTION The chip provides the following set of operational registers mapped into PCI memory space or I/O space. Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 R/W R/W R/W R R R/W R/W R/W R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R Tag CONFIG0 CONFIG1 RBW_PTR INT_STATUS INT_MASK RBSA RBR_PTR TX_STATUS TX_ STATUS0 TX_ STATUS1 TX_ STATUS2 TX_ STATUS3 TX_ADDR0 TX_ADDR1 TX_ADDR2 TX_ADDR3 RX_CONFIG MAC_ADDR0 MAC_ADDR1 MULTI_GROUP0 MULTI_GROUP1 RX_STATUS0 Bit Width 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Software Reset Select Rx Buffer Size Rx buffer write pointer Interrupt status register Interrupt mask register Rx buffer start address Rx buffer read pointer Transmit Status of All Descriptors Transmit Status of Descriptor 0 Transmit Status of Descriptor 1 Transmit Status of Descriptor 2 Transmit Status of Descriptor 3 Transmit Start Address of Descriptor 0 Transmit Start Address of Descriptor 1 Transmit Start Address of Descriptor 2 Transmit Start Address of Descriptor 3 Receive Configuration Register MAC Address 0 MAC Address 1 Multicast Group 0 Multicast Group 1 Receive Status Register 0 Reserved (To be continued) Description HANGZHOU SILAN MICROELECTRONICS CO.,LTD Http: www.silan.com.cn REV:1.0 2004.08.03 Page 7 of 38 SC92031 (Continued) Offset 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W - Tag TX_CONFIGURATION FLOW_CONTROL MIIM_COMMAND0 MIIM_COMMAND1 MIIM_STATUS TimerCnt TimerInt PM_CONFIG CRC CRC WAKEUP0 WAKEUP0 WAKEUP1 WAKEUP1 WAKEUP2 WAKEUP2 WAKEUP3 WAKEUP3 WAKEUP4 WAKEUP4 WAKEUP5 WAKEUP5 WAKEUP6 WAKEUP6 WAKEUP7 WAKEUP7 LastByte LastByte - Bit Width 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Reserved Description Transmit Configuration Register Flow Control Configuration Register MIIM Command Register 0 MIIM Command Register 1 MIIM Status Register Timer Counter Register Timer Interrupt Register Power Management configuration register Power Management CRC reg - crc3~crc0 Power Management CRC reg - crc7~crc4 Power Management reg - wakeup0[31:0] Power Management reg - wakeup0[63:32] Power Management reg - wakeup1[31:0] Power Management reg – wakeup1[63:32] Power Management reg – wakeup2[31:0] Power Management reg – wakeup2[63:32] Power Management reg – wakeup3[31:0] Power Management reg – wakeup3[63:32] Power Management reg – wakeup4[31:0] Power Management reg – wakeup4[63:32] Power Management reg – wakeup5[31:0] Power Management reg – wakeup5[63:32] Power Management reg – wakeup6[31:0] Power Management reg – wakeup6[63:32] Power Management reg – wakeup7[31:0] Power Management reg – wakeup7[63:32] Power Management Lastbyte reg Power Management Lastbyte reg Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved REV:1.0 2004.08.03 Page 8 of 38 HANGZHOU SILAN MICROELECTRONICS CO.,LTD Http: www.silan.com.cn SC92031 1 Config 0: Configuration Register 0 (Offset 0000h, R/W) Bit R/W Symbol Description Reset: Setting to 1 forces the chip to a software reset state which disables the transmitter and receiver, reinitializes the FIFOs, resets the system buffer pointer to the initial value (Tx buffer is at TSAD0, Rx 31 R/W Software Reset buffer is empty). The values of IDR0-5 and MAR0-7 and PCI configuration space will have no changes. This bit is 1 during the reset operation, and is cleared to 0 by the driver when the reset operation is complete. 30 R/W Analog Power Down Analog Power Down: 1: Turn off the analog power of the chip internally. 0: Normal working state. This is also power-on default value. Power Saving Mode: 1: Disable. 29 R/W Power Saving 0: Enable. When cable is disconnected, the analog part will power down itself automatically except PHY Rx part and part of twister to monitor SD signal in case that cable is re-connected and Link should be established again. 28-0 Reserved 2 Config 1: Configuration Register 1 (Offset 0004h, R/W) Bit 31 30 29-24 R/W R/W R/W Symbol Early Reception Description Set to 1 indicates enable early reception Reserved Rx FIFO Threshold: Specifies Rx FIFO Threshold level. When the number of the received data bytes from a packet, which is being received into Rx FIFO, has reached to this level (or the FIFO has contained a complete packet), the receive PCI bus master function will 23-21 R/W Rx FIFO Threshold begin to transfer the data from the FIFO to the host memory. This field sets the threshold level according to the following fomula: Threshold_Level = 16 * 2 ** Rx_FIFO_Threshold The chip begins the transfer of data after having received a whole packet in the FIFO. 20-4 Reserved Rx Buffer Length: This field indicates the size of the Rx ring buffer. 3-0 R/W Rx Buffer Length 0000 = 8k Bytes 0011 = 32k Bytes 1111 = 128k Bytes 0001 = 16k Bytes 0111 = 64k Bytes Early Transmission Set to 1 enable early transmission when reach TX threshold HANGZHOU SILAN MICROELECTRONICS CO.,LTD Http: www.silan.com.cn REV:1.0 2004.08.03 Page 9 of 38 SC92031 3 Interrupt Status Register (Offset 000Ch, R) The interrupt Status Register reflects all current pending interrupts, regardless of the state of the corresponding mask bit in the IMR. Reading the ISR clears all interrupts. Writing to the ISR has no effect. Bit 31 30 29 28-7 6 5 4-1 0 R/W R R R R R R Symbol Link fail Link OK Time Out Rx OK Tx OK Description Link Status is changed to Failure Link Status is changed to Success Time Out: Set to 1 when the TCTR register reaches to the value of the TimerInt register. Reserved Receive OK Reserved Transmit OK Rx Buffer Overflow Receive Buffer Overflow 4 Interrupt Mask Register (Offset 0010h, R/W) Bit 31 30 29 28-7 6 5 4-1 0 R/W R R R R R R Symbol Link fail Link OK Time Out Rx Buffer Overflow Rx OK Tx OK Description Link Fail Interrupt: 1 => Enable, 0 => Disable. Link OK Interrupt: 1 => Enable, 0 => Disable. Time Out Interrupt: 1 => Enable, 0 => Disable. Reserved Receive Buffer Overflow: 1 => Enable, 0 => Disable. Receive OK Interrupt: 1 => Enable, 0 => Disable. Reserved Transmit OK Interrupt: 1 => Enable, 0 => Disable. 5 Receive Buffer Start Address Register (Offset 0014h, R/W) Bit 31-0 R/W R/W Symbol RBSTART Receive Buffer Start Address Description 6 TX_STATUS: Transmit Status of All Descriptors (Offset 001Ch, R) Bit 31-16 15 14 13 12 11 10 9 8 7 R/W R R R R R R R R R TOK3 TOK2 TOK1 TOK0 TUN3 TUN2 TUN1 TUN0 TABT3 Symbol Reserved TOK bit of Descriptor3 TOK bit of Descriptor2 TOK bit of Descriptor1 TOK bit of Descriptor0 TUN bit of Descriptor3 TUN bit of Descriptor2 TUN bit of Descriptor1 TUN bit of Descriptor0 TABT bit of Descriptor3 (To be continued) Description HANGZHOU SILAN MICROELECTRONICS CO.,LTD Http: www.silan.com.cn REV:1.0 2004.08.03 Page 10 of 38 SC92031 (Continued) Bit 6 5 4 3 2 1 0 R/W R R R R R R R Symbol TABT2 TABT1 TABT0 OWN3 OWN2 OWN1 OWN0 TABT bit of Descriptor2 TABT bit of Descriptor1 TABT bit of Descriptor0 OWN bit of Descriptor3 OWN bit of Descriptor2 OWN bit of Descriptor1 OWN bit of Descriptor0 Description 7 Tansmit Status Register (TX_STATUS0-3)(Offset 0020h-002Fh, R/W) The read-only bits will be cleared by the chip when the Transmit Byte Count (bits 12-0) in the corresponding Tx descriptor is written. It is not affected when software writes to these bits. Bit 3130 29 28 27 26 25-22 R/W R R R R CRS TABT Later Collision Collision Counter Symbol Reserved Carrier Sense Lost: This bit is set to 1 when the carrier is lost during transmission of a packet. Transmit Abort: This bit is set to 1 if the transmission of a packet was aborted. Later Collision: This bit is set to 1 if the chip encountered an later collision during the transmission of a packet. Reserved Collision Count: Indicates the number of collisions encountered during the transmission of a packet. Early Tx Threshold: Specifies the threshold level in the Tx FIFO to 2116 R/W Early Threshold Tx begin the transmission. When the byte count of the data in the Tx FIFO reaches this level, (or the FIFO contains at least one complete packet) the chip will transmit this packet. These fields count from 000001 to 111111 in unit of 32 bytes. 15 14 R R TOK TUN Transmit Success: This bit is set to 1 if the transmission of a packet was successed. Tx FIFO Underrun: Set to 1 if the Tx FIFO was exhausted during the transmission of a packet. OWN: The chip sets this bit to 1 when the Tx DMA operation of this 13 12-0 R/W R/W OWN SIZE descriptor was completed. The driver must set this bit to 0 when the Transmit Byte Count (bits 0-12) is written. The default value is 1. Descriptor Size: The total size in bytes of the data in this descriptor. Description 8 Tansmit Start Address of Descriptor Register (TX_ADDR0-3)(Offset 0030h-003Fh, R/W) Bit 31-0 R/W R/W Symbol TSAD Description Transmit Start Address of Descriptor HANGZHOU SILAN MICROELECTRONICS CO.,LTD Http: www.silan.com.cn REV:1.0 2004.08.03 Page 11 of 38 SC92031 9 Receive Configuration Register (Offset 0040h, R/W) Bit 31 30 29 28 27 26 25 24 23-22 21-12 11-2 1-0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Symbol Rx_FullDX En_Rx Rcv Small Rcv_Huge Rcv_Error_Frame Rcv_All Rcv_Multi Rcv_Broad Lp_Bck Low_Threshold High_Threshold Description Set to 1 indicates work in full duplex mode Receive Enable Set to 1 indicates receive small packets (less than 64 bytes) Set to 1 indicates receive long packets (more than 1518 bytes) Set to 1 indicates receive error packets Set to 1 indicates receive all packets seen Set to 1 indicates receive multicast packets Set to 1 indicates receive broadcast packets “ indicates normal mode, else indicates loop back mode 00” Low Threshold of Rx FIFO High Threshold of Rx FIFO Reserved 10 MAC Address Register (Offset 0044h-004Bh, R/W) Bit 63-16 15-0 R/W R/W Symbol Eth_Addr Ethernet MAC Address Reserved Description 11 Multicast Address Group Register (Offset 004Ch-0053h, R/W) Bit 63-0 R/W R/W Symbol Multi_Group Description Multicast Address Group Configuration Register 12 Receive Status Register 0 (Offset 0054h, R) Bit 31-17 15-0 R/W R R Symbol FIFO_Over_Cnt Lost_Cnt FIFO Overflow Counter Rx Lost Frame Counter Description 13 Transmit Configuration Register (Offset 005Ch, R/W) Bit 31 30 29 28 27 26 25 24-0 R/W R/W R/W R/W R/W R/W R/W R/W Symbol Tx_Fulldx En_Tx En_PAD En_Huge En_FCS No_Backoff En_Premble Description Set to 1 indicates work in full duplex mode Transmit Enable Set to 1 indicates PAD when transmit small packets Set to 1 indicates enable long packets transmission Setting to 1 means that there is CRC appended at the end of a packet. Set to 1 indicates retransmit at once after a collision Set to 1 indicates always transmit preamble before valid data Reserved HANGZHOU SILAN MICROELECTRONICS CO.,LTD Http: www.silan.com.cn REV:1.0 2004.08.03 Page 12 of 38 SC92031 14 Flow Control Configuration Register (Offset 0064h, R/W) Bit 31 30 29 28 27 26 25-0 R/W R/W R/W R/W R/W R/W R/W Symbol Fulldx En_FC PASSALL En_Pause Tx_Pause_F Tx_Pause_0 Description Set to 1 indicates work in full duplex mode Enable Flow Control Set to 1 indicates that flow control function is implemented by software Set to 1 indicates prohibit send packets Set to 1 will send a PAUSE packet with parameter FFFF Set to 1 will send a PAUSE packet with parameter 0000 Reserved 15 MIIM Command Register 0 (Offset 0068h, R/W) Bit 3124 23 22 21 20 19 18-0 R/W R/W R/W R/W R/W R/W R/W Symbol Divider No_Pre Write Read Scan Tx_Mode Description Clock Divider to generate MDC signal Set to 1 indicates send frame without preamble Uprise indicates send a write command Uprise indicates send a read command Uprise indicates send a scan command Set to 1 indicates turn around time is 2 bits, else 1.5 bits Reserved 16 MIIM Command Register 1 (Offset 006Ch, R/W) Bit 3127 2611 10-6 5-0 R/W R/W R/W R/W Symbol PHY_Addr Ctrl_Data Reg_Addr PHY Address Control Data Register Address Reserved Description 17 MIIM Status Register (Offset 0070h, R) Bit 31 30-29 28-13 12-0 R/W R R Busy Status Symbol Description Set to 1 indicates MIIM module is busy Reserved Status of PHY Reserved HANGZHOU SILAN MICROELECTRONICS CO.,LTD Http: www.silan.com.cn REV:1.0 2004.08.03 Page 13 of 38 SC92031 18 Power Management Configuration Register (Offset 007Ch, R/W) Bit 31 R/W R/W Symbol PMEn detected support aux power. Enable Long Wake-up Frame: Set to 1: The chip supports up to 5 wake-up frames, each with 16-bit 30 R/W En_LongWF CRC algorithm for MS Wakeup Frame. Set to 0: The chip supports up to 8 wake-up frames, each with 8-bit CRC algorithm for MS Wakeup Frame. Magic Packet: This bit is valid when the PMEn bit is set. The chip will 29 R/W En_Magic assert the PMEB signal to wakeup the operating system when the Magic Packet is received. LANWake signal enable/disable: 28 R/W LANWake 1: Enable LANWake signal. 0: Disable LANWake signal. Lwake Output Signal Type: According to the combination of these two bits, there may be 4 choices of LWAKE signal, i.e., active high, active low, positive (high) pulse, and negative (low) pulse. The output pulse width is about 150ms. The default value of each of these two bits is 0, i.e., the default output signal of LWAKE pin is an active high signal. 27-26 R/W LOST LOST 00 01 10 11 Link Up: 25 R/W LinkUp This bit is valid when the PWEn bit is set. The chip, in adequate power state, will assert the PMEB signal to wakeup the operating system when the cable connection is reestablished. Wakeup Packet: This bit is valid when the PMEn bit is set. The chip will 24 23-0 R/W WakeUp assert the PMEB signal to wakeup the operating system when a valid Wakeup Packet is received. Reserved LWAKE output Active high Active low Positive pulse Negative pulse Description Power Management Enable: Writable only when the motherboard is HANGZHOU SILAN MICROELECTRONICS CO.,LTD Http: www.silan.com.cn REV:1.0 2004.08.03 Page 14 of 38 SC92031 INTERNAL PHY REGISTER DESCRIPTION Basic Mode Control Register (Offset 00, R/W) Bit 15 14 13 R/W R/W R/W Reset Spd_Set Name Description/Usage This bit sets the status and control registers of the PHY (register 00) in a default state. This bit is self-clearing. 1=software reset; 0=normal operation. Reserved This bit sets the network speed. 1=100Mbps; 0=10Mbps. This bit’ initial value comes from 93C46. s This bit enables/disables the Nway auto-negotiation function. Set to 1 12 R/W Auto negotiation to enable auto-negotiation, bit13 will be ignored. Set to 0 disables auto-negotiation, bit13 and bit8 will determine the link speed and the data transfer mode, respectively. This bit’ initial value s comes from 93C46. 11-10 9 R/W Restart Negotiation Auto Reserved This bit allows the Nway auto-negotiation function to be reset. 1=re-start auto-negotiation; 0=normal operation. This bit sets the duplex mode. 0=normal operation; 1=full-duplex. This 8 R/W Duplex Mode bit’ initial value come from 93C46. s If bit12 = 1, read = status write = register value. If bit12 = 0, read = write = register value. 7-0 Reserved Enable (ANE) Basic Mode Status Registers (Offset 01, R) Bit 15 14 13 12 11 10-6 5 4 R/W R R R R R R R Name 100Base-T4 100Base_TX_FD 100BASE_TX_HD 10Base_T_FD 10BASE_T_HD Auto Negotiation Complete Remote Fault Description/Usage 1 = enable 100Base-T4 support; 0 = suppress 100Base- T4 support. 1 = enable 100Base-TX full duplex support; 0 = suppress 100Base-tx full duplex support; 1 = enable 100Base-TX half-duplex support; 0 = suppress 100Base-TX half-duplex support; 1 = enable 10Base_T full duplex support; 0 = suppress 10Base_T full duplex support; 1 = enable 10BASE_T half-duplex support; 0 = suppress 10BASE_T half-duplex support; Reserved 1 = auto-negotiation process completed; 0 = auto-negotiation process not completed. 1 = remote fault condition detected (cleared on read); 0 = no remote fault condition detected. (To be continued) HANGZHOU SILAN MICROELECTRONICS CO.,LTD Http: www.silan.com.cn REV:1.0 2004.08.03 Page 15 of 38 SC92031 (Continued) Bit 3 2 1 0 R/W R R R R Name Auto Negotiation Link Status Jabber Detect Extended Capability Description/Usage 1 = link had not been experienced fail state. 0 = link had been experienced fail state. 1 = valid link established; 0 = no valid link established. 1 = jabber condition detected; 0 = no jabber condition detected. 1 = extended register capability; 0 = basic register capability only. Auto-negotiation Advertisement Register (Offset 04, R/W) This register contains the advertised abilities of this device as they will be transmitted to its link partner during Auto-negotiation. Bit 15 R/W R NP Name Next Page bit. 1 = transmitting the protocol specific data page; 0 = transmitting the primary capability data page. 14 13 12-10 9 8 7 6 5 4-0 R R/W R ACK RF T4 TXFD TX 10FD 10 Selector 1 = acknowledge reception of link partner capability data word. 1 = advertise remote fault detection capability; 0 = do not advertise remote fault detection capability. Reserved 1 = 100Base-T4 is supported by local node; 0 = 100Base-T4 not supported by local node. 1 = 100Base-TX full duplex is supported by local node; 0 = 100Base-TX full duplex not supported by local node. 1 = 100Base-TX is supported by local node; 0 = 100Base-TX not supported by local node. 1 = 10Base-T full duplex supported by local node; 0 = 10Base-T full duplex not supported by local node. 1 = 10Base-T is supported by local node; 0 = 10Base-T not supported by local node; Binary encoded selector supported by this node. Currently only CSMA/CD is specified. No other protocols are supported. Description/Usage R/W R/W R/W R/W R HANGZHOU SILAN MICROELECTRONICS CO.,LTD Http: www.silan.com.cn REV:1.0 2004.08.03 Page 16 of 38 SC92031 Auto-Negotiation Link Partner Ability Register (Offset 05, R) This register contains the advertised abilities of the Link Partner as received during Auto-negotiation. The content changes after the successful Auto-negotiation if Next-pages are supported. Bit 15 R/W R NP Name Next Page bit. 1 = transmitting the protocol specific data page; 0 = transmitting the primary capability data page. 14 13 12-10 9 8 7 6 5 4-0 R R R T4 TXFD TX 10FD 10 Selector ACK RF 1 = link partner acknowledge reception of local node’ capability data s word. 1 = link partner is indicating a remote fault. Reserved 1 = 100Base-T4 is supported by link partner; 0 = 100Base-T4 not supported by link partner. 1 = 100Base-TX full duplex is supported by link partner; 0 = 100Base-TX full duplex not supported by link partner. 1 = 100Base-TX is supported by link partner; 0 = 100Base-TX not supported by link partner. 1 = 10Base-T full duplex supported by link partner; 0 = 10Base-T full duplex not supported by link partner. 1 = 10Base-T is supported by link partner; 0 = 10Base-T not supported by link partner; Link Partner’ s binary encoded node selector. Currently only CSMA/CD is specified. Description/Usage R R R R R Auto-negotiation Expansion Register (Offset 06, R) This register contains additional status for Nway auto-negotiation. Bit 15 4 3 2 R/W R R -LP_NP_ABLE NP_ABLE Name Description/Usage Reserved, This bit is always set to 0. Status indicating if the link partner supports Next Page negotiation. 1 = supported; 0 = not supported. This bit indicates if the local node is able to send additional Next Pages. This bit is set when a new Link Code Word Page has been received. 1 0 R R PAGE _RX LP_NW_ABLE The bit is automatically cleared when the auto-negotiation link partner’ s ability register (register 5) is read by management. 1 = link partner supports NWay auto-negotiation. Disconnect Counter (Offset 10, R) Bit 15 0 R/W R Name DCNT Description/Usage This 16-bit counter increments by 1 for every disconnect event. It rolls over when becomes full. It is cleared to zero by read command. HANGZHOU SILAN MICROELECTRONICS CO.,LTD Http: www.silan.com.cn REV:1.0 2004.08.03 Page 17 of 38 SC92031 False Carrier Sense Counter (Offset 11, R) This counter provides information required to implement the “ FalseCarriers”attribute within the MAU managed object class of Clause 30 of IEEE 802.3u specification. Bit 15 0 R/W R Name FCSCNT Description/Usage This 16-bit counter increments by 1 for each false carrier event. It is cleared to zero by read command. Nway Test Register (Offset 13, R/W) Bit 15-8 7 6-4 3 2 1 0 R/W R/W R/W R R R -NWLPBK -ENNWLE FLAGABD FLAGPDF FLAGLSC Name Reserved 1 = set Nway to loopback mode. Reserved 1 = LED0 Pin indicates link pulse 1 = Auto-neg experienced ability detect state 1=Auto-neg experienced parallel detection fault state 1 = Auto-neg experienced link status check state Description/Usage RX_ER Counter (Offset 14, R) Bit 15 0 R/W R Name RXERCNT Description/Usage This 16-bit counter increments by 1 for each valid packet received. It is cleared to zero by read command. CS Configuration Register (Offset 15, R/W) Bit 15-9 8 7 6 5 4-3 2 1 0 R/W R/W R/W R/W R/W R/W R/W HEART BEAT JBEN F_LINK_100 F_Connect Con_status_En PASS_SCR Name Reserved 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. 1 = enable jabber function; 0 = disable jabber function. Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. Assertion of this bit forces the disconnect function to be bypassed. Reserved Assertion of this bit configures LED1 pin to indicate connection status. Reserved Bypass Scramble Description/Usage HANGZHOU SILAN MICROELECTRONICS CO.,LTD Http: www.silan.com.cn REV:1.0 2004.08.03 Page 18 of 38 SC92031 FUNCTION DESCRIPTION Ø Transmit operation The host CPU initiates a transmission by storing an entire packet of data in one of the descriptors in the main memory. When the entire packet has been transferred to the Tx buffer, the SC92031 is instructed to move the data from the Tx buffer to the internal transmit FIFO in PCI bus master mode. When the transmit FIFO contains a complete packet or is filled to the programmed threshold level, the SC92031 begins packet transmission. Ø Receive Operation The incoming packet is placed in the SC92031's Rx FIFO. Concurrently, the SC92031 performs address filtering of multicast packets according to its hash algorithms. When the amount of data in the Rx FIFO reaches the level defined in the Receive Configuration Register, the SC92031 requests the PCI bus to begin transferring the data to the Rx buffer in PCI bus master mode. Ø Auto-negotiation The Auto-Negotiation function is designed to provide the means to exchange information between the transceiver and the network partner to automatically configure both to take maximum advantage of their abilities, and both are setup accordingly. The Auto-Negotiation exchanges information with the network partner using the Fast Link Pulses (FLPs) - a burst of link pulses. There are 16 bits of signaling information contained in the burst pulses to advertise all remote partner’ capabilities which are determined by PHY register 4. According to this s information they find out their highest common capability by following the priority sequence as below: 1. 100BASE-TX full duplex 2. 100BASE-TX half duplex 3. 10BASE-T full duplex 4. 10BASE-T half duplex During power-up or reset, if Auto-Negotiation is found enabled then FLPs will be transmitted and the AutoNegotiation function will process. Otherwise, the Auto-Negotiation will not occur. When the Auto-Negotiation is disabled, then the Network Speed and Duplex Mode are selected by programming PHY register 0. Ø Transceiver The transmitter operation in 100 Mbps mode consists of a MLT-3 encoder, waveform generator and line driver. The MLT-3 encoder converts the NRZI data into a three level MLT-3 code required by IEEE 802.3u. MLT-3 coding uses three levels and converts 1's to transitions between the three levels, and converts 0's to no transitions or changes in level. The purpose of the waveform generator is to shape the transmit output pulse. The waveform generator eliminates the need for any external filters on the TP transmit output. The line driver converts the shaped and smoothed wave-form to a current output that can drive 100 meters of category 5 unshielded twisted pair cable or 150 Ohm shielded twisted pair cable. The transmitter operation in 10 Mbps mode is much different than the 100 Mbps transmitter. Even so, the transmitter still consists of a waveform generator and line driver. The receiver either in 10Mbps or 100Mbps mode is mainly a reverse procedure of transmitter Ø Clock and Data Recovery The Clock and Data Recovery (CDR) module uses a DPLL to lock onto the incoming data stream and to extracts the recovered clock that will be used to re-time the data stream and set the data boundaries. HANGZHOU SILAN MICROELECTRONICS CO.,LTD Http: www.silan.com.cn REV:1.0 2004.08.03 Page 19 of 38 SC92031 Ø Loopback Operation Loopback mode is normally used to verify that the logic operations up to the Ethernet cable function correctly. In loopback mode for 100Mbps, the SC92031 takes frames from the transmit descriptor and transmits them up to internal Twister logic. Ø Tx En/decoder While operating in 100Base-TX mode, the SC92031 performs typically encoding steps of 4B5B encoder, scrambler, parallel-to-serial converter, NRZ-to-NRZI converter and NRZI-to-MLT3. While operating in 10Base-T mode, the SC92031 typically performs parallel-to-serial converter and Manchester process which combines clock and NRZ data such that the first half of the data bit contains the complement of the data, and the second half of the data bit contains the true data. The decoder procedure either in 10Mbps or 100Mbps mode is just a reverse of encoder. Ø Collision If the SC92031 is not in the full-duplex mode, a collision event occurs when the receive input is not idle while the SC92031 transmits. If the collision was detected during the preamble transmission, the jam pattern is transmitted after completing the preamble (including the JK symbol pair). Ø Flow Control The SC92031 supports IEEE802.3X flow control to improve performance in full-duplex mode. It detects PAUSE packet to achieve flow control task. 1. Control Frame Transmission When the SC92031 detects that its free receive buffer is less than 3K bytes, it sends a PAUSE packet with pause_time(=FFFFh) to inform the source station to stop transmission for the specified period of time. After the driver has processed the packets in the receive buffer and updated the boundary pointer, the SC92031 sends the other PAUSE packet with pause_time(=0000h) to wake up the source station to restart transmission. 2. Control Frame Reception The SC92031 enters a back off state for a specified period of time when it receives a valid PAUSE packet with pause_time(=n). If the PAUSE packet is received while the SC92031 is transmitting, the SC92031 starts to back off after current transmission completes. The SC92031 is free to transmit the next packets when it receives a valid PAUSE packet with pause_time(=0000h) or the back off timer(=n*512 bit time) elapses. EEPROM (93C46) Contents The 93C46 is a 1K-bit serial EEPROM, it can be organized by 64 words or 128 bytes. Now we list its contents by words showed as below for convenience. After the valid duration of the RSTB pin or auto-load command in the 93C46, the SC92031 performs a series of EEPROM read operations from the 93C46 addresses 00H to 3FH. HANGZHOU SILAN MICROELECTRONICS CO.,LTD Http: www.silan.com.cn REV:1.0 2004.08.03 Page 20 of 38 SC92031 Words 00h 01h 02h 03h 04h 05h 06h 07h 08h-0Ah 0Bh-0Dh 0Eh-1Fh 20h-3Fh Contents 1904 2031 Device ID Vendor ID MAXLAT MINGNT INTR PIN INTR LINE Sub ID Sub Vendor ID Ethernet Address VPD DATA Description These 4 bytes contain the ID code word for the SC92031 These 4 bytes contain the ID code word for the chip. The chip will load the contents of EEPROM into the corresponding location if the ID word is right, otherwise, the chip will not proceed with the EEPROM autoload process. PCI Maximum Latency Timer, PCI configuration space offset 3Fh. PCI Minimum Grant Timer, PCI configuration space offset 3Eh. Interrupt Pin Interrupt Line Selection. PCI Subsystem ID, PCI configuration space offset 2Eh-2Fh. PCI Subsystem Vendor ID, PCI configuration space offset 2Ch-2Dh. Reserved Ethernet ID, After auto-load command or hardware reset, the chip loads Ethernet ID to I/O registers. Reserved VPD data field. Offset 20h is the start address of the VPD data. PCI Configuration Space Registers 1 PCI Configuration Space Table No. 00h 01h 02h 03h 04h Command 05h 06h 07h Status Name VID Type R R R R R W R W R R W Revision ID PIFR SCR BCR CLS LTR HTR R R R R R R W R Bit7 VID7 VID15 DID7 DID15 0 0 FBBC DPERR DPERR 0 0 0 0 0 LTR7 LTR7 0 Bit6 VID6 VID14 DID6 DID14 PERRSP PERRSP 0 0 SSERR SSERR 0 0 0 0 0 LTR6 LTR6 0 Bit5 VID5 VID13 DID5 DID13 0 0 0 RMABT RMABT 0 0 0 0 0 LTR5 LTR5 0 Bit4 VID4 VID12 DID4 DID12 0 0 NewCap RTABT RTABT 0 0 0 0 0 LTR4 LTR4 0 Bit3 VID3 VID11 DID3 DID11 0 0 STABT STABT 0 0 0 0 0 LTR3 LTR3 0 0 DST1 0 0 0 0 0 LTR2 LTR2 0 Bit2 VID2 VID10 DID2 DID10 BMEN BMEN 0 Bit1 VID1 VID9 DID1 DID9 MEMEN MEMEN Bit0 VID0 VID8 DID0 DID8 IOEN IOEN DID FBTBEN SERREN 0 DST0 0 0 0 1 0 LTR1 LTR1 0 SERREN 0 DPD DPD 0 0 0 0 0 LTR0 LTR0 0 (To be continued) 08H 09h 0Ah 0Bh 0Ch 0Dh 0Eh HANGZHOU SILAN MICROELECTRONICS CO.,LTD Http: www.silan.com.cn REV:1.0 2004.08.03 Page 21 of 38 SC92031 (Continued) No. 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h2Bh 2Ch 2Dh 2Eh 2Fh Name BIST Type R R W Bit7 0 0 IOAR15 IOAR23 IOAR31 0 MEM15 MEM23 MEM31 Bit6 0 0 IOAR14 Bit5 0 0 - Bit4 0 0 - Bit3 0 0 - Bit2 0 0 - Bit1 0 0 IOAR9 IOAR17 IOAR25 0 MEM9 MEM17 MEM25 Bit0 0 IOIN IOAR8 IOAR16 IOAR24 MEMIN MEM8 MEM16 MEM24 IOAR R/W R/W R/W R IOAR13 IOAR12 IOAR11 IOAR10 IOAR19 IOAR18 IOAR27 IOAR26 0 MEM11 MEM19 MEM27 0 MEM10 MEM18 MEM26 IOAR22 IOAR21 IOAR20 IOAR30 IOAR29 IOAR28 0 MEM14 MEM22 MEM30 0 MEM13 MEM21 MEM29 0 MEM12 MEM20 MEM28 MEMAR W R/W MEMAR R/W R/W Reserved SVID R R R R R SVID7 SVID15 SMID7 SMID15 0 SVID6 SVID14 SMID6 SVID5 SVID13 SMID5 SVID4 SVID12 SMID4 SVID3 SVID11 SMID3 SVID2 SVID10 SMID2 SVID1 SVID9 SMID1 SMID9 0 0 SVID0 SVID8 SMID0 SMID8 BROMEN BROM EN R W R/W R/W Cap_Ptr Reserved ILR IPR MNGNT MXLAT Reserved PMID NextPtr PMC R R R R 0 0 0 1 0 1 DSI 0 0 0 0 0 0 0 0 1 0 R/W R R R IRL7 0 0 0 IRL6 0 0 0 IRL5 0 1 1 IRL4 0 0 0 IRL3 0 0 0 IRL2 0 0 0 IRL1 0 0 0 IRL0 1 0 0 R BMAR15 BMAR14 BMAR13 BMAR12 BMAR11 BMAR15 BMAR14 BMAR13 BMAR12 BMAR11 0 0 - SMID SMID14 SMID13 SMID12 0 0 0 - SMID11 SMID10 0 0 - 30h W BMAR 31h 32h 33h 34h 35h3Bh 3Ch 3Dh 3Eh 3Fh 40h4Fh 50h 51h 52h 53h BMAR23 BMAR22 BMAR21 BMAR20 BMAR19 BMAR18 BMAR17 BMAR16 BMAR31 BMAR30 BMAR29 BMAR28 BMAR27 BMAR26 BMAR25 BMAR24 0 1 0 1 0 0 0 0 Aux_I_b1 Aux_I_b0 Reserved PMECLK Version D2 D1 Aux_I_b2 PME_D3c PME_D3h PME_D2 PME_D1 PME_D0 (To be continued) HANGZHOU SILAN MICROELECTRONICS CO.,LTD Http: www.silan.com.cn REV:1.0 2004.08.03 Page 22 of 38 SC92031 (Continued) No. Name Type R Bit7 0 PME_ status PME_ status Bit6 0 - Bit5 0 - Bit4 0 - Bit3 0 - Bit2 0 - Bit1 Power State Power State - Bit0 54h PMCSR W R PME_En PME_En 55h PMCSR W 56h5Fh 60h 61h 62h 63h 64h 65h 66h 67h 68hFFh Reserved VPDID NextPtr Flag VPD Address R R R/W R/W R/W VPD Data R/W R/W R/W Reserved 0 0 R7 Flag Data7 Data15 Data23 Data31 0 0 R6 R14 Data6 Data14 Data22 Data30 0 0 R5 R13 Data5 Data13 Data21 Data29 0 0 R4 R12 Data4 Data12 Data20 Data28 0 0 R3 R11 Data3 Data11 Data19 Data27 0 0 R2 R10 Data2 Data10 Data18 Data26 1 0 R1 R9 Data1 Data9 Data17 Data25 1 0 R0 R8 Data0 Data8 Data16 Data24 VPDADD VPDADD VPDADD VPDADD VPDADD VPDADD VPDADD VPDADD VPDADD VPDADD VPDADD VPDADD VPDADD VPDADD VPDADD 2 PCI Configuration Space functions The PCI configuration space is intended for configuration, initialization, and catastrophic error handling functions. The functions of the SC92031's configuration space are described below. VID: Vendor ID. This field will default to a value of SILAN Semiconductor's PCI Vendor ID. DID: Device ID. This field will default to a value of SILAN Semiconductor's PCI Device ID. Command: The command register is a 16-bit register used to provide coarse control over a device's ability to generate and respond to PCI cycles. HANGZHOU SILAN MICROELECTRONICS CO.,LTD Http: www.silan.com.cn REV:1.0 2004.08.03 Page 23 of 38 SC92031 Bit 15-10 Symbol Reserved Fast Back-To-Back Enable: When =0, read as a zero. write operation has no effect. The SC92031 will not generate Fast Back-to-back cycles. When =1, This read/write bit controls whether or not a master can do fast 9 FBTBEN back-to-back transactions to different devices. Initialization software will set the bit if all targets are fast back-to-back capable. A value of one means the master is allowed to generate fast back-to-back transaction to different agents. A value of zero means fast back-to-back transactions are only allowed to the same agent. This bit’ state after RSTB is zero. s System Error Enable: When set a one, the SC92031 drive the SERRB line when it 8 SERREN detects a parity error on the address phase (AD and CBEB ); A zero disables the SC92031’ SERRB output driver. s 7 ADSTEP Address/Data Stepping: Read as zero, write operation has no effect. The SC92031 disable to perform address/data stepping. Parity Error Response: When set to a one, the SC92031 will assert the PERRB pin on the detection of a data parity error when acting as the target, and will sample 6 PERRSP the PERRB pin as the master. When cleared to a zero, any detected parity error is ignored and the SC92031 continues normal operation. Parity checking is disabled after hardware reset (RSTB). 5 4 3 VGASNOOP MWIEN SCYCEN VGA palette SNOOP: Read as a zero, write operation has no effect. Memory Write and Invalidate cycle Enable: Read as a zero, write operation has no effect. Special Cycle Enable: Read as a zero, write operation has no effect. The SC92031 ignores all special cycle operation. Bus Master Enable: When set to a one, the SC92031 is capable of acting as a bus 2 BMEN master. When cleared to a zero, it is prohibited from acting as a PCI bus master. For the normal operation, this bit must be set by the system BIOS. Memory Space Access: When set to a one, the SC92031 responds to memory 1 MEMEN space accesses. When cleared to a zero, the SC92031 ignores memory space accesses. 0 IOEN I/O Space Access: When set to a one, the SC92031 responds to I/O space access. When cleared to a zero, the SC92031 ignores I/O space access. Description Status: The status register is a 16-bit register used to record status information for PCI bus related events. Reads to this register behave normally. Writes are slightly different in that bits can be reset, but not set. HANGZHOU SILAN MICROELECTRONICS CO.,LTD Http: www.silan.com.cn REV:1.0 2004.08.03 Page 24 of 38 SC92031 Bit 15 14 13 12 11 Symbol DPERR SSERR RMABT RTABT STABT Description Detected Parity Error: When set indicates that the SC92031 detected a parity error, even if parity error handling is disabled in command register PERRSP bit. Signaled System Error: When set indicates that the SC92031 asserted the system error pin, SERRB. Writing a one clears this bit to zero. Received Master Abort: When set indicates that the SC92031 terminated a master transaction with master abort. Writing a one clears this bit to zero. Received Target Abort: When set indicates that the SC92031 master transaction was terminated due to a target abort. Writing a one clears this bit to zero. Signaled Target Abort: Set to a one whenever the SC92031 terminates a transaction with target abort. Writing a one clears this bit to zero. Device Select Timing: These bits encode the timing of DEVSELB. They are set to 10-9 DST1-0 01b (medium), indicating the SC92031 will assert DEVSELB two clocks after FRAMEB is asserted. Data Parity error Detected: This bit sets when the following conditions are met: Ø 8 DPD Ø Ø The SC92031 asserts parity error (PERRB pin) or it senses the assertion of PERRB pin by another device. The SC92031 operates as a bus master for the operation that caused the error. The Command register PERRSP bit is set. Writing a one clears this bit to zero. 7 6 5 4 3-0 FBBC UDF 66MHz NewCap Fast Back-To-Back Capable: =0, Read as zero, write operation has no effect. =1, Read as one. User Definable Features Supported: Read as zero, write operation has no effect. The SC92031 does not support UDF. 66 MHz Capable: Read as zero, write operation has no effect. The SC92031 has no 66MHz capability. New Capability: =0, Read as zero, write operation has no effect. =1, Read as one. Reserved RID: Revision ID Register The Revision ID register is an 8-bit register that specifies the SC92031 controller revision number. PIFR: Programming Interface Register The programming interface register is an 8-bit register that identifies the programming interface of the SC92031 controller. Because the PCI version 2.1 specification does not define any specific value for network devices, PIFR = 00h. SCR: Sub-Class Register The Sub-class register is an 8-bit register that identifies the function of the SC92031. SCR = 00h indicates that the SC92031 is an Ethernet controller. BCR: Base-Class Register The Base-class register is an 8-bit register that broadly classifies the function of the SC92031. BCR = 02h indicates that the SC92031 is a network controller. HANGZHOU SILAN MICROELECTRONICS CO.,LTD Http: www.silan.com.cn REV:1.0 2004.08.03 Page 25 of 38 SC92031 CLS: Cache Line Size Read will return a zero, write are ignored. LTR: Latency Timer Register Specifies, in units of PCI bus clocks, the value of the latency timer of the SC92031. When the SC92031 asserts FRAMEB, it enables its latency timer to count. If the SC92031 deasserts FRAMEB prior to count expiration, the content of the latency timer is ignored. Otherwise, after the count expires, the SC92031 initiates transaction termination as soon as its GNTB is deasserted. Software is able to read or write, and the default value is 00H. HTR: Header Type Register Read will return a zero, write are ignored. BIST: Built-in Self Test Read will return a zero, write are ignored. IOAR: This register specifies the BASE I/O address which is required to build an address map during configuration. It also specifies the number of bytes required as well as an indication that it can be mapped into I/O space. Bit 31-8 7-2 1 0 Symbol IOAR31-8 IOSIZE IOIN operational register map. Size Indication: Read back as a zero. This allows the PCI bridge to determine that the SC92031 requires 256 bytes of I/O space. Reserved IO Space Indicator: Read only. Set to a one by the SC92031 to indicate that it is capable of being mapped into IO space. Description BASE I/O Address: This is set by software to the Base I/O address for the MEMAR: This register specifies the base memory address for memory accesses to the SC92031 operational registers. This register must be initialized prior to accessing any SC92031's register with memory access. Bit 31-8 7-4 3 2-1 Symbol MEM31-8 MEMSIZE MEMPF MEMLOC operational register map. Memory Size: These bits return a zero, which indicates that the SC92031 requires 256 bytes of Memory Space. Memory Prefetchable: Read only. Set to a zero by the SC92031. Memory Location Select: Read only. Set to a zero by the SC92031. This indicates that the base register is 32-bit wide and can be placed anywhere in the 32-bit memory space. 0 MEMIN Memory Space Indicator: Read only. Set to a zero by the SC92031 to indicate that it is capable of being mapped into memory space. Description Base Memory Address: This is set by software to the base address for the SVID: Subsystem Vendor ID. This field will be set to a value corresponding to PCI Subsystem Vendor ID in the external EEPROM. If there is no EEPROM, this field will default to a value of SILAN Semiconductor's PCI Subsystem Vendor ID. SMID: Subsystem ID. This field will be set to value corresponding to PCI Subsystem ID in the external EEPROM. If there is no EEPROM, this field will default to a value of 2031h. BMAR: This register specifies the base memory address for memory accesses to the SC92031 operational registers. This register must be initialized prior to accessing any SC92031 's register with memory access. HANGZHOU SILAN MICROELECTRONICS CO.,LTD Http: www.silan.com.cn REV:1.0 2004.08.03 Page 26 of 38 SC92031 Bit 31-18 Symbol BMAR31-18 Boot ROM Base Address These bits indicate how many Boot ROM spaces to be supported. The Relationship between and BMAR17-11 is the following: BS2 BS1 BS0 Description 000 001 17-11 ROMSIZE 010 011 100 101 110 111 10-1 0 BROMEN No Boot ROM, BROMEN=0 (R) 8K Boot ROM, BROMEN (R/W), BMAR12-11 = 0 (R), BMAR17-13 (R/W) 16K Boot ROM, BROMEN (R/W), BMAR13-11 = 0 (R), BMAR17-14 (R/W) 32K Boot ROM, BROMEN (R/W), BMAR14-11 = 0 (R), BMAR17-15 (R/W) 64K Boot ROM, BROMEN (R/W), BMAR15-11 = 0 (R), BMAR17-16 (R/W) 128K Boot ROM, BROMEN(R/W), BMAR16-11=0 (R), BMAR17 (R/W) unused unused Description Read back a zero Boot ROM Enable: This is used by the PCI BIOS to enable accesses to Boot ROM. ILR: Interrupt Line Register The Interrupt Line Register is an 8-bit register used to communicate with the routing of the interrupt. It is written by the POST software to set interrupt line for the SC92031. IPR: Interrupt Pin Register The Interrupt Pin register is an 8-bit register indicating the interrupt pin used by the SC92031. The SC92031 uses INTA interrupt pin. Read only. IPR = 01H. MNGNT: Minimum Grant Timer: Read only Specifies how long a burst period the SC92031 needs at 33 MHz clock rate in units of 1/4 microsecond. This field will be set to a value from the external EEPROM. If there is no EEPROM, this field will default to a value of 20h. MXLAT: Maximum Latency Timer: Read only Specifies how often the SC92031 needs to gain access to the PCI bus in unit of 1/4 microsecond. This field will be set to a value from the external EEPROM. If there is no EEPROM, this field will default to a value of 20h. 3 The Default Value after Power-on (RSTB asserted) The Default Value of PCI Configuration No. 00h 01h 02h 03h 04h Command 05h Name VID DID Type R R R R R W R W Bit7 VID7 VID15 DID7 DID15 0 0 Bit6 VID6 VID14 DID6 DID14 0 PERRSP 0 Bit5 VID5 VID13 DID5 DID13 0 0 Bit4 VID4 VID12 DID4 DID12 0 0 Bit3 VID3 VID11 DID3 DID11 0 Bit2 VID2 VID10 DID2 DID10 0 BMEN 0 Bit1 VID1 VID9 DID1 DID9 0 MEMEN 0 Bit0 VID0 VID8 DID0 DID8 0 IOEN 0 SERREN (To be continued) HANGZHOU SILAN MICROELECTRONICS CO.,LTD Http: www.silan.com.cn REV:1.0 2004.08.03 Page 27 of 38 SC92031 (Continued) No. 06h 07h 08H 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h2Bh 2Ch Name Status Type R R W R R R R R R W R R R R/W R/W R/W R R/W R/W R/W Bit7 0 0 DPERR 0 0 0 0 0 0 LTR7 0 0 0 0 0 0 0 0 0 0 Bit6 0 0 SSERR 0 0 0 0 0 0 LTR6 0 0 0 0 0 0 0 0 0 0 Bit5 0 0 RMABT 0 0 0 0 0 0 LTR5 0 0 0 0 0 0 0 0 0 0 Bit4 NewCap 0 RTABT 0 0 0 0 0 0 LTR4 0 0 0 0 0 0 0 0 0 0 Bit3 0 0 STABT 0 0 0 0 0 0 LTR3 0 0 0 0 0 0 0 0 0 0 Bit2 0 0 0 0 0 0 0 0 LTR2 0 0 0 0 0 0 0 0 0 0 Bit1 0 1 0 0 0 1 0 0 LTR1 0 0 0 0 0 0 0 0 0 0 Bit0 0 0 DPD 0 0 0 0 0 0 LTR0 0 0 1 0 0 0 0 0 0 0 Revision ID PIFR SCR BCR CLS LTR HTR BIST IOAR MEMAR Reserved (All 0) R SVID R R SMID R R W R BMAR W R/W R/W SVID7 SVID15 SMID7 SVID6 SVID14 SMID6 SVID5 SVID13 SMID5 SVID4 SVID12 SMID4 SVID3 SVID11 SMID3 SVID2 SVID10 SMID2 SVID1 SVID9 SMID1 SMID9 0 0 0 0 SVID0 SVID8 SMID0 SMID8 0 BROMEN 0 0 0 2Dh 2Eh 2Fh 30h 31h 32h 33h SMID15 SMID14 SMID13 SMID12 SMID11 SMID10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BMAR15 BMAR14 BMAR13 BMAR12 BMAR11 0 0 0 0 0 0 0 0 0 0 (To be continued) HANGZHOU SILAN MICROELECTRONICS CO.,LTD Http: www.silan.com.cn REV:1.0 2004.08.03 Page 28 of 38 SC92031 (Continued) No. 34h 35h3Bh 3Ch 3Dh 3Eh 3Fh 40hFFh Name Cap_Ptr Type R Bit7 Ptr7 Bit6 Ptr6 Bit5 Ptr5 Bit4 Ptr4 Bit3 Ptr3 Bit2 Ptr2 Bit1 Ptr1 Bit0 Ptr0 Reserved (All 0) ILR IPR MNGNT MXLAT R/W R R R 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 Reserved (All 0) PCI Power Management functions The SC92031 supports power management mechanism, it complies with the ACPI Specification Rev 1.1, PCI Power Management Rev 1.1, and Device Class Power Management Reference Specification V1.0a, such as to support OS Directed Power Management (OSPM) environment. These features allow a PCI device to save power when programmed to do so, and to signal the system that the device needs the system to return to a normal operating state to service a wake event. This document details the hardware operation of the family of devices. Software operation (i.e. drivers or operating systems) should comply with this document. The Power Management Specification presents a low-level hardware interface to PCI devices for the purpose of saving power. The SC92031 supports power states D0, D1, D2, D3hot, and D3cold as defined in the PCI Power Management Specification. In PCI Power Management mode, three Wake-up events are supported, including Wake-up Frame Received, Magic Packet Received and Link Status Changed. When the PME Enable bit is set to 1, incoming packets are filtered based on settings in the Receive Configuration Register. If the device detects a wake event while in Power Management mode, it will assert the PMEB pin low to signal the system that a wake event has occurred and the device requires service. The system should then bring the device out of Power Management mode. The chip also supports LAN WAKE-UP function. The LWAKE pin is used to notify the motherboard to execute wake-up process whenever the chip receives a wakeup event, such as Magic Packet. HANGZHOU SILAN MICROELECTRONICS CO.,LTD Http: www.silan.com.cn REV:1.0 2004.08.03 Page 29 of 38 SC92031 LED INTERFACE 1 LED_ACTIVE The LED_ACTIVE pin indicates the presence of transmit or receive activity. 2 LED_SPEED The LED_SPEED pin indicates a good link at 100 Mb/s data rate. HANGZHOU SILAN MICROELECTRONICS CO.,LTD Http: www.silan.com.cn REV:1.0 2004.08.03 Page 30 of 38 SC92031 3 LED_DUPLEX_COL The LED_DUPLEX_COL pin indicates a FULL DUPLEX link or collisions in a HALF DUPLEX link. Power On LED=Low Full Duplex Yes LED=High No No Collisiion status Yes LED=Blinked at intervels of 50ns PCI BUS OPERATION TIMING Target Read HANGZHOU SILAN MICROELECTRONICS CO.,LTD Http: www.silan.com.cn REV:1.0 2004.08.03 Page 31 of 38 SC92031 Target Write Configuration Read HANGZHOU SILAN MICROELECTRONICS CO.,LTD Http: www.silan.com.cn REV:1.0 2004.08.03 Page 32 of 38 SC92031 Configuration Write Bus Arbitration Memory Read HANGZHOU SILAN MICROELECTRONICS CO.,LTD Http: www.silan.com.cn REV:1.0 2004.08.03 Page 33 of 38 SC92031 Memory Write Target Initiated Termination - Retry 1 2 3 4 5 6 7 CLK FRAMEB AD31~0 IRDYB TRDYB STOPB DEVSELB ADRESS DATA1 DATA2 Target Initiated Termination - Disconnect HANGZHOU SILAN MICROELECTRONICS CO.,LTD Http: www.silan.com.cn REV:1.0 2004.08.03 Page 34 of 38 SC92031 Target Initiated Termination - Abort Master Initiated Termination - Abort CLK FRAMEB 1 2 3 4 5 6 7 8 IRDYB DEVSELB FAST MED SLOW SUB Parity Operation - one example HANGZHOU SILAN MICROELECTRONICS CO.,LTD Http: www.silan.com.cn REV:1.0 2004.08.03 Page 35 of 38 SC92031 TYPICAL APPLICATION CIRCUIT HANGZHOU SILAN MICROELECTRONICS CO.,LTD Http: www.silan.com.cn REV:1.0 2004.08.03 Page 36 of 38 SC92031 PACKAGE OUTLINE QFP-100-14×20-0.65 UNIT: mm LQFP-100-14×14-0.50 UNIT: mm HANGZHOU SILAN MICROELECTRONICS CO.,LTD Http: www.silan.com.cn REV:1.0 2004.08.03 Page 37 of 38 SC92031 HANDLING MOS DEVICES: Electrostatic charges can exist in many things. All of our MOS devices are internally protected against electrostatic discharge but they can be damaged if the following precautions are not taken: • Persons at a work bench should be earthed via a wrist strap. • Equipment cases should be earthed. • All tools used during assembly, including soldering tools and solder baths, must be earthed. • MOS devices should be packed for dispatch in antistatic/conductive containers. HANGZHOU SILAN MICROELECTRONICS CO.,LTD Http: www.silan.com.cn REV:1.0 2004.08.03 Page 38 of 38