SC9256S

Silan Semiconductors PLL FOR DTS DESCRIPTION The SC9256 is phase-locked loop (PLL) LSIs for digital tuning systems (DTS) with built in 2 modulus prescalers. All functions ate controlled through 3 serial bus lines. These LSIs are used to configure high-performance digital tuning system. SC9256 DIP-16-300-2.54 FEATURES * Optimal for configuring digital tuning systems in high-fi tuners and car stereos. * built-in prescalers. Operate at input frequency ranging from 30~150 MHz during FMIN input (with 2 modulus prescaler) and at 0.5~40MHz during AMIN input (with 2 modulus prescaler or direct dividing). * 16 bit programmable counter, dual parallel output phase comparator, crystal oscillator and reference counter. * 3.6MHz, 4.5MHz, 7.2MHz or 10.8MHz crystal oscillators can be used. * 15 possible reference frequencies. ( When using 4.5MHz crystal) * Built-in 20 bit general-purpose counter for such uses as measuring intermediate frequencies (IFIN1 and IFIN2) * High-precision (±0.55~±7.15µs) PLL phase error detection. * Numerous general-purpose I/O pins for such uses as peripheral circuit control. * 3 N-channel open-drain output ports (OFF withstanding voltage:12V) for such uses as control signal output. * Standby mode function (turns off FM, AM and IF amps) to save current consumption. * All functions controlled through 3 serial bus lines. * CMOS structure with operating power supply range of VDD=5.0±0.5V. SOP-16-300-1.27 ORDERING INFORMATION Device SC9256 SC9256S Package DIP-16-300-2.54 SOP-16-300-1.27 PIN CONFIGURATION XT XT PERIOD CLOCK DATA OT-1 OT-2 OT-3 1 2 3 4 5 6 7 8 16 DO2/OT-4 15 DO1 14 I/O-5/IFIN1 SC9256 13 I/O-6/IFIN2 12 GND 11 FMIN 10 AMIN 9 VDD HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 2002.01.30. 1 Silan Semiconductors BLOCK DIAGRAM VDD FML AMP FMIN 1/2 FMH HF AMIN FM XT XT OSC CIRCUIT LF MODE 12bit PROGRAMMABLE COUNTER 4 12 MAX 15 1ms OSC 24bit REGISTER 5 DATA CLOCK 8 ADDRESS DECODER PERIOD 24bit REGISTER 4 OUTPUT PORT SC9256 GND PSC 2 MODULUS PERSCALER 4bit SWALLOW COUNTER POWER ON RESET PHASE COMPARATOR RESET TRI-STATE BUFFER DO1 REFERENCE COUNTER TRI-STATE BUFFER OT4 DO2/OT-4 4 UNLOCK 24bit SHIFT REGISTER TEST 5 24 22 10 I/O PORT I/O-6/IFIN2 AMP GATE AMP I/O-5/IFIN1 4 20bit BINARY COUNTER UNIVERSAL COUNTER CONTROL XT 1ms OT-1 OT-2 OT-3 ABSOLUTE MAXIMUM RATINGS (Ta=25°C) Characteristic Supply Voltage Input Voltage N-ch Open-Drain Off withstanding Voltage Power Dissipation Operating Temperature Storage Temperature ( ): Flat package Symbol VCC VIN VOFF PD TOPR TSTG Value -0.3~6.0 -0.3~VDD+0.3 13 300(200) -40~85 -65~150 Unit V V V mW °C °C HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 2002.01.30. 2 Silan Semiconductors SC9256 Test Condition/Pin PLL operation (normal operating) VDD=5.0V, XT=10.8MHz, ELECTRICAL CHARACTERISTICS (unless otherwise specified, Ta= -40~85°C, VDD=4.5~5.58V.) Characteristic Operating Power Supply Voltage Symbol VDD1 Min 4.5 Typ. 5.0 Max 5.5 Unit V Operating Power Supply Current Stand-by mode Crystal Oscillation Frequency IDD1 FMIN=150MHz -- 7 15 mA PLL OFF VDD2 (Operating crystal oscillation) IDD2 IDD3 VDD=5.0V, XT =10.8MHz PLL OFF VDD=5.0V, XT stop, PLL OFF Connect crystal resonator to XT- XT terminal FMH, FML mode, VIN=0.2Vp-p FML mode, VIN=0.3Vp-p HF mode, VIN=0.2Vp-p LF mode, VIN=0.2Vp-p VIN=0.2Vp-p VIH=0.7VDD, VIL=0.3VDD, square wave input. FMH, FML mode, fIN=30~130MHz FML mode, fIN=30~150MHz HF mode, fIN=1~40MHz LF mode, fIN=0.5~20MHz FIN=0.1~15MHz VOL=1.0V VOFF=12V --0.8 120 1.5 240 mA µA 4.0 5.0 5.5 V Supply Voltage Operating Power Supply Current Operating Power Supply Current Operating frequency range Crystal Oscillation Frequency FMIN (FMH, FML) FMIN (FML) AMIN (HF) AMIN (LF) IFIN1, IFIN2 SCIN Operating input amplitude range FMIN (FMH, FML) FMIN (FML) AMIN (HF) AMIN (LF) IFIN1, IFIN2 OT1~OT4 N-ch open drain Output Current OFF-leak Current “L” level fXT fFM fFML fHF fLF fIF fSC 3.6 30 30 1 0.5 0.1 -- ~ ~ ~ ~ ~ ~ ~ 10.8 130 150 40 20 15 100 MHz MHz MHz MHz MHz MHz kHz VFM VFML VHF VLF VIF IOL1 IOEF 0.2 0.3 0.2 0.2 0.2 5.0 -- ~ ~ ~ ~ ~ 10.0 --- VDD-0.5 VDD-0.5 VDD-0.5 VDD-0.5 VDD-0.5 -2.0 Vp-p Vp-p Vp-p Vp-p Vp-p mA µA (To be continued) HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 2002.01.30. 3 Silan Semiconductors (Continued) SC9256 Test Condition/Pin Min 0.7VDD 0 VIH=5V VIL=0V VOH=4.0V (expect SCIN) VOL=1.0V (expect SCIN) ---2.0 2.0 Characteristic I/O-5~I/O-9, SCIN Input Voltage “H” level “L” level Input Current “H” level “L” level Output Current “H” level “L” level PERIOD, CLOCK, DATA Input Voltage “H” level “L” level Input Current “H” level “L” level Output Current “H” level “L” level DO1, DO2 Input Current “H” level “L” level Tri-State Lead Current XT Symbol VIH1 VIL1 IIH IIL IOH4 IOL4 Typ. ~ ~ ---4.0 4.0 Max VDD 0.3VDD 2.0 -2.0 --- Unit V µA mA VIH2 VIL2 IIH IIL IOH5 IOL5 VIH=5V VIL=0V VOH=4.0V (DATA) VOL=1.0V (DATA) 0.8VDD 0 ---1.0 1.0 ~ ~ ---3.0 3.0 VDD 0.2VDD 2.0 -2.0 --- V µA mA IOH3 IOL3 ITL VOH=4.0V VOL=1.0V VTLH=5V, VTLL=0V -2.0 2.0 -- -4.0 4.0 -- --±1.0 mA µA Output Current “H” level “L” level IOH2 IOL2 VOH=4.0V VOL=1.0V -0.1 0.1 -0.3 0.3 --- mA Input feedback resistance Input Feedback Resistance “L” level “H” level Rf1 Rf2 FMIN, AMIN, IFIN (Ta=25°C) XT- XT (Ta=25°C) 350 500 700 1000 1400 4000 kΩ PIN DESCRIPTION Pin No. 1 Symbol XT Pin name Description Connects 3.6MHz, 4.5MHz, 7.2MHz Circuit diagram VDD Crystal oscillator 2 XT or 10.8MHz crystal oscillator to supply reference frequency and internal clock XT XT pins (To be continued) HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 2002.01.30. 4 Silan Semiconductors (Continued) SC9256 Description VDD Pin No. 3 4 Symbol PERIOD CLOCK Pin name Circuit diagram Period signal input Serial I/O ports. These pins transfer Clock signal input Serial data input/output data to and from the controller to set divisions and dividing modes, and to control the general-purpose counter and general-purpose I/O ports. N channel open drain port pins, for General-purpose output ports such uses as control signal output. These pins are set to the OFF state when power is turned on. These pins input FM and AM band Programmable local oscillator signals by capacitor coupling. FMIN and AMIN operate at low amplitude. General-purpose I/O port input 5 DATA Schmitt input DATA Schmitt input CLOCK,PERIOD 6 7 8 10 OT-1 OT-2 OT-3 AMIN N-channel open drain VDD 11 FMIN counter input /output pins. Can be switched for use as input pins to measure general 13 I/O6/IFIN2 General-purpose I/O ports/Generalpurpose frequency measurement input 14 I/O-5 /IFIN1 counter purpose counter frequencies. The VDD frequency measurement function has such uses as measuring inter- mediate frequencies (IF). These pins feature built-in amps. Data are input by capacitor coupling. FMIN and AMIN operate at low amplitude. (note) Pins are set for input when power is turned on. VDD 15 DO1 Phase comparator output (Generaloutput These pins are for phase comparator tri-state output. DO1 and DO2 are output in parallel. 16 DO2/OT-4 purpose ports) 12 9 GND VDD Power supply pins Applies 5.0V±10% HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 2002.01.30. 5 Silan Semiconductors FUNCTION DESCRIPTION Serial I/O ports SC9256 As the block diagram shows, the functions are controlled by setting data in the 48 bits contained in each of the 2 sets of 24 bit registers. Each bit of data in these register is transferred through the serial ports between the controller and the DATA, CLOCK and PERIOD pins. Each serial transfer consists of a total of 32 bits, with 8 address bits and 24 data bits. Since all functions are controlled in units of registers, the explanation in this manual focuses on the 8 bit address and functions of each register. These registers consist of 24 bits and are selected by an 8 bit address. A list of the address assignment for each register is given below under register assignments. Register Address Contents of 24 bits PLL divisor setting Reference frequency setting No. of bit 16 4 2 2 total 24 4 3 1 1 1 5 9 total 24 22 2 total 24 5 5 4 5 5 total 24 Input register 1 D0H PLL input and mode setting Crystal oscillator selection General=purpose counter control (including lock detection bit control) I/O port and general-purpose counter switching bits I/O-5/CLK pin switching bit Input register 2 D2H DO pin control Test bit I/O port control (also used as general-purpose counter input selection bits) Output data General-purpose counter numeric data Output register 1 D1H Not used Lock detection data I/O port control data Output register 2 D3H Output data Input data (undefined during output port selection) Not used When the PERIOD signal falls, the input data are latched in register 1 or register 2 and the function is performed. When the CLOCK signal falls for 9 time, the output data are latched in parallel in the output registers. The data are subsequently output serially from the data pin. HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 2002.01.30. 6 Silan Semiconductors REGISTER ASSIGMENTS Address=D0H LSB P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 R0 R1 R2 SC9256 LSB R3 FM MODE OSC1 OSC2 Input registers Programmable counter data Reference frequency code data Programmable counter mode Crystal oscillator selection bits Address=D2H (*2) G0 G1 -IF1 IF2 O4C DOHZ RESET START TEST XT --M5 M6 O1 O2 O3 O4 ---O5 O6 TEST RESET CLK Gate I/O port bit bit time and general-purpose bit START select counter switching bits DOHZ bit bit Also used as general-purpose counter input selection bits I/O port control Output port output data Address=D1H LSB Input registers f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 OVER BUSY "0" "0" General-purpose counter data Address=D3H ENA- UN PE1 BLE LOCK PE2 PE3 "0" "0" "0" "0" "0" 0 0 0 M5 M6 O1 O2 O3 O4 0 0 0 Not used I5 I6 Lock detection data Not used I/O port control data Output data Input data When power is turned on, the input registers are set as shown below. Address=D0H LSB MSB (*1) (*1) (*1) (*1) (*1) (*1) (*1) (*1) (*1) (*1) (*1) (*1) (*1) (*1) (*1) 1 1 1 1 1 1 0 0 Input registers (*1) Address=D2H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Note: 1. Data are undefined. 2. Set data to “0” for test bit. HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 2002.01.30. 7 Silan Semiconductors Serial transfer format SC9256 End The serial transfer format consists of 8 address bits and 24 data bits (Fig. 1). Addresses D0H~D3H are used. Start PERIOD t3 t4 t1 t2 9 clock signal fall CLOCK t8 (*) (*) DATA LSB t5 t6 t7 0 0 1 0 1 1 MSB LSB MSB 8 address bits 24 data bits (24bit register) Fig.1 • Serial data transfer serial data are transferred in sync with the clock signal. In the idle state, the PERIOD, CLOCK and DATA pin lines are all set to “H” level. When the period signal is at “L” level, the falling of the clock signal initiates serial data transfer. Data transfer ceases when the period signal is set to “L” level when the clock signal is at “H” level. Once serial data transfer has begun, however, no more than 8 falls of the clock signal can occur during the time the period signal is at “L” level. Since the receiving side receives the serial data as valid data when the clock signal rises, it is effective for the sending side to produce output in sync with the clock signal fall. To receive serial data from the output registers (D1H, D3H), set the serial data output to high impedance after the 8 bit address is output but before the next clock signal falls. Data reception subsequently continues until the period signal becomes “L” level; data transfer ends just before the period signal rises. Therefore, the data pin must have an open-drain or tristate interface. Note: 1. when power is turned on, some internal circuit have undefined states. To set internal circuit states, execute a dummy data transfer before performing regular data transfer. 2. times t1~t8 have the following value: t1≥1.0µs t2≥1.0µs t3≥0.3µs t4≥0.3µs t5≥0.3µs t6≥1.0µs t7≥1.0µs t8≥0.3µs 3. Asterisks represent numbers taken from addresses, as in D*H. HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 2002.01.30. 8 Silan Semiconductors Crystal oscillator pins (XT, XT ) SC9256 As fig.2 shows, the clock necessary for internal operation is produced by connecting a crystal oscillator between capacitors. Use the crystal oscillator selection bit to select an oscillating frequency of 3.6MHz, 4.5MHz, 7.2MHz or 10.8MHz which matches that of the crystal oscillator used. LSB Address D0H MSB OSC1 OSC2 OSC1 0 1 0 1 OSC2 0 0 1 1 OSCILLATOR FREQUENCY 3.6MHz 4.5MHz 7.2MHz 10.8MHz Divider XT C X'tal XT C C=30pF Typ. Fig.2 Note: set to 3.6MHz (OSC1=”0” and OSC2=”0”) when power is turned on. The crystal is not oscillating at this time because the system is in standby mode. Reference counter (Reference frequency divider) The reference counter section consists of a crystal oscillator and a counter. A crystal oscillator frequency of 3.6MHZ, 7.2MHZ or 10.8MHZ can be selected .A maximum of 15 reference frequencies can be generated. 1. Setting reference frequency The reference frequency is set using bits R0~R3. LSB Address D0H R0 R1 R2 R3 MSB R0 R1 R2 R3 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 REFERENCE FREQUENCY 0.5 KHz 1 KHz 2.5 KHz 3 KHz 3.125 KHz *3.90654 KHz 5 KHz 6.25 KHz R0 R1 R2 R3 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 REFERENCE FREQUENCY *7.8125 KHz 9 KHz 10 KHz 12.5 KHz 25 KHz 50 KHz 100 KHz Standby mode (*1) HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 2002.01.30. 9 Silan Semiconductors SC9256 Note: 1. Reference frequencies marked with an asterisk “*”can only be generated with a 4.5MHZ crystal oscillator. 2. (*1)Standby mode Standby mode occurs when bits R0,R1,R2,and R3 are all set to “1”.In standby mode, the programmable counter stops, and FM, AM and IFIN(when selected IFIN) are set to “amp off” state (pins at “L” level). This saves current consumption when the radio is turned off. The DO pins become high impedance during standby mode. During standby mode, the I/O ports (I/O-5~I/O-6) and output ports (OT1~OT4) can be controlled and the crystal oscillator can be turned on and off. 3.The system is set to standby mode when power is turned on. At this time, the crystal oscillator is not oscillating and the I/O ports are set to input mode. Programmable counter The programmable counter section consists of a 1/2 prescaler, a 2 modulus prescaler and a 4bit +12bit programmable binary counter. 1. Setting programmable counter 16 bits of divisor data and 2 bits, which indicate the dividing mode, are set in the programmable counter. (1) Setting dividing mode The FM and MODE bits are used to select the input pin and the dividing mode (pulses wallow mode or direct dividing mode). There are 4 possible choices, shown in the table below .Select one based on the frequency band used. LSB Address D0H FM MODE MSB MODE FM MODE DIVIDING MODE LF HF FML FMH 0 0 1 1 0 1 0 1 Direct dividing mode Pulse swallow mode 1/2 + pulse swallow mode INPUT FREQUENCY TYPICAL RANGE RECEIVING BAND LW,MW,SWL SWH FM FM 0.5 ~ 20MHz 1 ~ 40MHz 30 ~ 130MHz 30 ~ 150MHz 30 ~ 130MHz INPUT FREQUENCY PIN AMIN n FMIN 2n (2) Setting divisor The divisor for the programmable counter is set as binary data in bits P0~P15. • Pulse swallow mode (16 bits) LSB Address D0H P0 20 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 215 MSB Divisor setting range (pulse swallow mode):n=210H~FFFH (528~65535) (Note) With the 1/2+pulse swallow mode, the actual divisor is twice the programmed value. HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 2002.01.30. 10 Silan Semiconductors • Direct dividing mode (12 bits) LSB Address D0H P0 P1 P2 P3 P4 20 Don't care P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 211 SC9256 MSB Divisor setting range (direct dividing mode):n=10H~FFFH(16~4095) With the direct dividing mode, data p0~p3 are don’t-care and bit p4 is the LSB. 2. Prescaler and programmable counter circuit configuration (1) Pulse swallow mode circuit configuration PSC P0-P3 4bit swallow counter FMIN 1/2 FML AMIN HF FM,MODE P4-P15 Prescaler section FMH 2 modulus prescaler Preset 12bit programmable counter To phase comparator Fig.3 This circuit consists of a 2 modulus prescaler, a 4 bit swallow counter and a 12bit programmable counter. During FMIN(FMIN mode),a 1/2 prescaler is added to the preceding step. (2) Direct dividing method circuit configuration Preset Amp AMIN 12bit program counter To phase comparator P4-P15 Fig.4 With the direct dividing mode, the prescaler section is bypassed and the 12bit programmable counter is used. (3) Both FMIN and AMIN have built-in amps. Data are input by capacitor coupling. FMIN and AMIN operate at low amplitude. General-purpose counter The general-purpose counter is a 20bit counter. It has such uses as counting AM/FM band intermediate frequencies (IF) and detecting auto-stop signals during auto-search tuning. General-purpose counter pins can also be used as I/O ports. 1. General-purpose counter control bits (1) Bits G0 and G1 … Used for selecting the general-purpose counter gate time. HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 2002.01.30. 11 Silan Semiconductors LSB Address D2H G0 G1 SC9256 MSB G0 G1 GATE TIME 0 1 0 1 0 0 1 1 1ms 4ms 16ms 64ms CYCLE MEASUREMENT PULSE 50 KHz 150 KHz 900 KHz Crystal oscillator frequency (2) Bits SC,IF1 and IF2 …I/O port and general-purpose counter switching bits. (*) The functions of the following pins are switched by data. LSB Address D2H IF1 IF2 MSB IF1 1 0 I/O-5/IFIN1 IF2 1 0 I/O-6/IFIN2 IFIN2 I/O-6 IFIN1 I/O-5 (3) Bits M5 sets the state for pin I/O-5/IFIN1; M6, for pin I/O-6/IFIN2. These operations are valid when bits SC, IF1 and IF2 are all set to 1. LSB Address D2H M5 M6 MSB M5 0 (*) 1 0 M6 0 1 0 0 PIN STATES (When bits sc, IF1 and IF2 are all set to "1") IFIN1 INPUT pulled down INPUT enabled INPUT pulled down IFIN2 INPUT pulled down INPUT enabled INPUT pulled down Note: Bits marked with an asterisk “(*)” are don’t care (4) Bits f0~f9…The general-purpose counter results can be read in binary from bits f0~f9 of the output register (D1H). LSB Address D1H f0 20 General-purpose counter data f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 219 OVER BUSY MSB "0" "0" (5) OVER and BUSY bits…Detect the operating state of the general-purpose counter. HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 2002.01.30. 12 Silan Semiconductors Address D1H OVER BUSY SC9256 MSB "0" "0" BIT DATA = "1" General-purpose counter option monitor bit General-purpose counter overflow detection bit General-purpose counter busy Counted value in generalpurpose counter 220 (Overflow state) BIT DATA = "0" General-purpose counter ended counting Counted value in generalpurpose counter 220 -1 Note: When using the general-purpose counter, before referring to the contents of the general-purpose counter result bit (f0~f9), confirm that the busy bit is “0” (counting is ended) and the OVER bit is “0” (general-purpose counter data are normal). (6) START bit…When the data are set to “1”, the general-purpose counter is reset then counting begins. LSB Address D2H start MSB 0 1 Counting continues uninterrupted. Counting begins after general - purpose counter is reset. 2. General-purpose counter circuit configuration The general-purpose counter section consists of input amps, a gate time control circuit and a 20 bit binary counter. Amp IFIN1 f0-f19 20bit binary counter OVER Overflow detection IFIN2 Cycle measurement pulse Gate Gate time control circuit START G0 fXT SCIN (CMOS input) SC IF1 IF2 G1 BUSY Fig.5 3. General-purpose counter measurement timing HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD REV: 1.0 2002.01.30. 13 ‚ ƒ Silan Semiconductors PERIOD End SC9256 T1 START bit set to "1" IFIN1 OR IFIN2 BUSY bit T2 Gate Binary counter input Clock pulse to be measured Frequency measurement timing chart 0