SII1160

® Technology SiI 1160 PanelLink Transmitter Data Sheet Document # SiI-DS-0126-B SiI 1160 PanelLink Transmitter Data Sheet Silicon Image, Inc. SiI-DS-0126-B March 2005 Application Information To obtain the most updated Application Notes and other useful information for your design, please visit the Silicon Image web site at www.siliconimage.com or contact your local Silicon Image sales office. Copyright Notice This manual is copyrighted by Silicon Image, Inc. Do not reproduce, transform to any other format, or send/transmit any part of this documentation without the expressed written permission of Silicon Image, Inc. Silicon Image, the Silicon Image logo, PanelLink® and the PanelLink® Digital logo are registered trademarks of Silicon Image, Inc. TMDSTM is a trademark of Silicon Image, Inc. I2C is a trademark of Philips Semiconductor. All other trademarks are the property of their respective holders. Trademark Acknowledgment Disclaimer This document provides technical information for the user. Silicon Image, Inc. reserves the right to modify the information in this document as necessary. The customer should make sure that they have the most recent data sheet version. Silicon Image, Inc. holds no responsibility for any errors that may appear in this document. Customers should take appropriate action to ensure their use of the products does not infringe upon any patents. Silicon Image, Inc. respects valid patent rights of third parties and does not infringe upon or assist others to infringe upon such rights. All information contained herein is subject to change w ithout notice. Revision History Revision A B Date 07/07/04 03/01/05 Comment Data Sheet – 1st release Data Sheet – 2nd release – added I2C registers and pins, added dual zone PLL information, corrected recommended REXT_SW ING value from 380Ω to 510Ω, corrected package JEDEC code, added reset description. © 2005 Silicon Image. Inc. SiI-DS-0126-B ii SiI 1160 PanelLink Transmitter Data Sheet TABLE OF CONTENTS General Description ........................................................................................................................................ 1 Features ...................................................................................................................................................... 1 Functional Description .................................................................................................................................... 3 Electrical Specifications .................................................................................................................................. 4 Absolute Maximum Conditions ................................................................................................................... 4 Normal Operating Conditions ..................................................................................................................... 4 Digital I/O Specifications ............................................................................................................................. 4 DC Specifications ........................................................................................................................................ 5 AC Specifications ........................................................................................................................................ 5 Input Timing Diagrams ................................................................................................................................ 6 Pin Descriptions .............................................................................................................................................. 8 Input Pins .................................................................................................................................................... 8 Control and Configuration Pins ................................................................................................................... 8 Power Management Pins ............................................................................................................................ 9 Differential Signal Data Pins ....................................................................................................................... 9 Local Control (I2C) Interface ....................................................................................................................... 9 Reserved Pins ........................................................................................................................................... 10 Power and Ground Pins ............................................................................................................................ 10 Feature Information ...................................................................................................................................... 11 I2C Interface .............................................................................................................................................. 11 I2C Register Mapping ................................................................................................................................ 12 Dual Zone PLL .......................................................................................................................................... 13 Manual Zone Control ............................................................................................................................. 13 Automatic Zone Control......................................................................................................................... 14 Reset Description ...................................................................................................................................... 14 TFT Panel Data Mapping .......................................................................................................................... 15 Design Recommendations ........................................................................................................................... 20 Differences Between SiI 160 and SiI 1160 ............................................................................................... 20 EXT_SWING Selection ............................................................................................................................. 20 PCB Ground Planes .................................................................................................................................. 20 Voltage Ripple Regulation......................................................................................................................... 20 Spread Spectrum Support ......................................................................................................................... 21 Reset Circuit for I2C Application ................................................................................................................ 22 Power Control ........................................................................................................................................... 22 Decoupling Capacitors .............................................................................................................................. 23 Series Damping Resistors on Outputs...................................................................................................... 24 Source Termination Resistors on Differential Outputs .............................................................................. 24 Differential Trace Routing ......................................................................................................................... 25 Package Dimensions .................................................................................................................................... 28 Package .................................................................................................................................................... 28 Ordering Information ................................................................................................................................. 28 iii SiI-DS-0126-B SiI 1160 PanelLink Transmitter Data Sheet LIST OF TABLES Table 1. General I C Register Bits ................................................................................................................ 13 Table 2. Dual Zone PLL I2C Control Register Bits ........................................................................................ 14 Table 3. One Pixel/Clock Input/Output TFT Mode ........................................................................................ 15 Table 4. Two Pixels/Clock Input/Output TFT Mode ...................................................................................... 16 Table 5. 24-bit One Pixel/Clock Input with 24-bit Two Pixels/Clock Output TFT Mode ................................ 17 Table 6. 18-bit One Pixel/Clock Input with 18-bit Two Pixels/Clock Output TFT Mode ................................ 18 Table 7. Two Pixels/Clock Input with One Pixel/Clock Output TFT Mode .................................................... 19 Table 8. New Pin Functions for SiI 1160 Tx .................................................................................................. 20 Table 9. Power Consumption Characteristics .............................................................................................. 22 Table 10. Recommended Components for Bypass and Decoupling Circuits............................................... 23 Table 11. Routing Guidelines for DVI Traces................................................................................................ 27 2 LIST OF FIGURES Figure 1. System Block Diagram – Typical Application .................................................................................. 1 Figure 2. Pin Diagram for SiI 1160 ................................................................................................................. 2 Figure 3. Functional Block Diagram ............................................................................................................... 3 Figure 4. Clock Cycle High/Low Times........................................................................................................... 6 Figure 5. Input Data Setup/Hold Time to IDCK .............................................................................................. 6 Figure 6. VSYNC, HSYNC and CTL[3:1] Delay Time from DE ...................................................................... 6 Figure 7. DE High and Low Times .................................................................................................................. 6 Figure 8. Reset Timing at Power-Up or Prior to First I2C Access ................................................................... 7 Figure 9. I2C Byte Read ................................................................................................................................ 11 Figure 10. I2C Byte Write .............................................................................................................................. 11 Figure 11. Voltage Regulation using LM317EMP ......................................................................................... 20 Figure 12. Planned Spread Spectrum Support Circuit ................................................................................. 21 Figure 13. Typical Reset Circuit.................................................................................................................... 22 Figure 14. Decoupling and Bypass Capacitor Placement ............................................................................ 23 Figure 15. Decoupling and Bypass Schematic............................................................................................. 23 Figure 16. Series Input Damping Resistors for Driving Source ................................................................... 24 Figure 17. Differential Output Source Terminations .................................................................................... 24 Figure 18. Source Termination Layout Illustration ........................................................................................ 25 Figure 19. Example of Incorrect Differential Signal Routing ........................................................................ 26 Figure 20. Example of Correct Differential Signal Routing ........................................................................... 26 Figure 21. Differential Trace Routing to DVI Connector (Top Side View) .................................................... 26 Figure 22. 100-pin TQFP Package Dimensions (JEDEC code MS-026-AED) ............................................ 28 SiI-DS-0126-B iv SiI 1160 PanelLink Transmitter Data Sheet General Description The SiI 1160 transmitter uses PanelLink Digital technology to support displays up to UXGA resolution. It supports up to true-color panels (24 bits per pixel, 16.7M colors) in 1 or 2 pixels-per-clock mode. All PanelLink products are designed on scaleable CMOS architecture to support future performance requirements while maintaining the same logical interface. The SiI 1160 transmitter follows this strategy by offering a pin-compatible upgrade to the SiI 160 transmitter that also brings longer cable support. PanelLink Digital technology simplifies the PC & display interface by resolving many of the system level issues associated with high-speed digital design, providing the system designer with a digital solution that is quicker to market and lower in cost. Features • • • • • • • • Scaleable Bandwidth: 25-165 MHz (VGA to UXGA) Backwards compatible replacement for the SiI 160 transmitter High Skew Inter pair Tolerance: 1 full input clock cycle (6ns at 165 MHz) Flexible interface: single or dual pixel input at up to 48 bits Cable Distance Support: over 20m DVI cable Fully DVI 1.0 compliant Advanced on-chip input clock jitter filter to ensure clean output to receiver Available in Universal package for both standard and Pb-Free (environmentally-friendly) applications. control Video Processor even pixel data 24 / odd pixel data 24 / clock SiI 1160 TMDS Tx TMDS over DVI cable or flat cable control even pixel data 24 / odd pixel data 24 / clock Panel Controller SiI 1161 TMDS Rx Figure 1. System Block Diagram – Typical Application 1 SiI-DS-0126-B SiI 1160 PanelLink Transmitter Data Sheet O D D 8 -b its B L U E IVCC O D D 8 -b its G R E E N DIO18 DIO17 DIO16 DIO15 DIO14 DIO13 DIO12 DIO11 DIO10 DIO9 DIO8 DIO7 O D D 8 -b its R E D DIO20 DIO19 GND DIO0 75 DIO6 DIO5 DIO4 DIO3 DIO2 73 DIO1 74 GND 67 VCC 56 51 52 53 54 55 57 58 59 60 61 62 63 64 65 66 68 69 70 71 72 CONTROLS HSYNC VSYNC DE GND ID C K IV C C CTL3 CTL2 CTL1 PVCC2 PGND2 VCC GND D IE 2 3 D IE 2 2 D IE 2 1 D IE 2 0 D IE 1 9 D IE 1 8 D IE 1 7 D IE 1 6 IV C C D IE 1 5 D IE 1 4 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 50 49 48 47 46 45 44 43 42 41 D IO 2 1 D IO 2 2 D IO 2 3 AGND TX2+ TX2AVCC IN P U T CLOCK GPI DIFFERENTIAL SIGNALS TX1+ TX1AGND TX0+ TX0RSVD AGND AVCC TXC+ TXCAGND PLL IS E L /R S T S iI 1 1 6 0 1 0 0 -P in T Q F P ( T o p V ie w ) 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 EVEN 8-bits RED E X T _ S W IN G GND VCC RSVD RSVD RSVD PD PIXS EDGE SDA RSVD MSEN SCL PGND1 PVCC1 IVCC DIE0 DIE1 DIE2 DIE3 DIE4 DIE5 DIE6 DIE7 VCC GND DIE8 DIE9 DIE10 DIE11 DIE12 E V E N 8 - b it s G R E E N DIE13 E V E N 8 -b its B L U E PLL CONTROL C O N F IG U R A T IO N P IN S Figure 2. Pin Diagram for SiI 1160 SiI-DS-0126-B 2 SiI 1160 PanelLink Transmitter Data Sheet Functional Description The SiI 1160 Tx is a DVI 1.0 compliant PanelLink transmitter in a compact package. It provides 48 bits for data input to allow for panel support up to UXGA. Figure 3 shows the functional blocks of the chip. EXT_SWING DIE[23:0] DIO[23:0] DE HSYNC VSYNC CTL3 CTL2 CTL1 I2C Registers ----------Configuration Logic ----------Message Encoder Logic CTL0 DATA Data Capture Logic CTL1 Encoder 1 24 24 DATA HSYNC VSYNC Swing Control Tx0+ Tx0 Tx0- Encoder 0 Tx1+ Tx1 Tx1- EDGE PIXS SDA SCL DATA CTL2 CTL3 config info Encoder 2 Tx2+ Tx2 Tx2- IDCK Jitter Filter Main PLL TxC TxC+ TxC- Figure 3. Functional Block Diagram 3 SiI-DS-0126-B SiI 1160 PanelLink Transmitter Data Sheet Electrical Specifications Absolute Maximum Conditions Symbol VCC1 VI VO2 Tj TSTG Parameter Supply Voltage 3.3V Input Voltage Input Voltage Junction Temperature (with power applied) Storage Temperature Min -0.3 -0.3 -0.3 -65 Typ Max 4.0 VCC+ 0.3 VCC+ 0.3 125 150 Units V V V °C °C Note 1. Permanent device damage may occur if absolute maximum conditions are exceeded. 2. Functional operation should be restricted to the conditions described under normal operating conditions. Normal Operating Conditions Symbol VCC VCCN TA θJA Note 1. Airflow at 0m/s. Parameter Supply Voltage Supply Voltage Noise Ambient Temperature (with power applied) Thermal Resistance (junction to ambient)1 Min 3.0 0 Typ 3.3 25 Max 3.6 100 70 53 Units V mVP-P °C °C/W Digital I/O Specifications Under normal operating conditions unless otherwise specified. Symbol VIH VIL VOH VOL VCINL VCIPL VCONL VCOPL IOL Parameter High-level Input Voltage Low-level Input Voltage High-level Input Voltage Low-level Input Voltage Input Clamp Voltage1 Input Clamp Voltage1 Input Clamp Voltage1 Input Clamp Voltage1 Input Leakage Current Conditions Min 2 Typ Max 0.8 Units V V V V V V V V µA 2.4 ICL = -18mA ICL = 18mA ICL = -18mA ICL = 18mA High Impedance 0.4 GND -0.8 IVCC + 0.8 GND -0.8 OVCC + 0.8 10 -10 Note 1. Guaranteed by design. Voltage undershoot or overshoot cannot exceed absolute maximum conditions for a pulse of greater than 3 ns or one third of the clock cycle. SiI-DS-0126-B 4 SiI 1160 PanelLink Transmitter Data Sheet DC Specifications Under normal operating conditions, with REXT_SWING = 510Ω and using source termination, unless otherwise specified. Symbol VOD Parameter Differential Voltage Single ended peak to peak amplitude Differential High-level Output Voltage1 Differential Output Short Circuit Current1 Power-down Current2 Transmitter Supply Current Conditions RLOAD = 50Ω Min 510 Typ 550 AVCC Max 590 Units mV V VDOH IDOS IPD ICCT VOUT = 0 V 5 5 µA mA mA IDCK= 165 MHz, two pixel per clock mode IVCC = VCC, Worst Case Pattern3 140 200 Notes 1. Guaranteed by design. 2. Assumes all inputs to the transmitter are not toggling. 3. The Worst Case Pattern consists of a black and white checkerboard pattern, each checker one pixel wide. AC Specifications Under normal operating conditions with source termination and the recommended REXT_SWING value unless otherwise specified. Symbol TCIP FCIP TCIP FCIP TCIH TCIL TSIDF THIDF TSIDR THIDR TDDF TDDR THDE TLDE TI2CDVD TRESET Parameter IDCK Period, 1 Pixel/Clock IDCK Frequency, 1 Pixel/Clock IDCK Period, 2 Pixels/Clock IDCK Frequency, 2 Pixels/Clock IDCK High Time at 165MHz IDCK Low Time at 165MHz Data, DE, VSYNC, HSYNC, and CTL[3:1] Setup Time to IDCK falling edge Data, DE, VSYNC, HSYNC, and CTL[3:1] Hold Time from IDCK falling edge Data, DE, VSYNC, HSYNC, and CTL[3:1] Setup Time to IDCK rising edge Data, DE, VSYNC, HSYNC, and CTL[3:1] Hold Time from IDCK rising edge VSYNC, HSYNC, and CTL[3:1] Delay from DE falling edge1 VSYNC, HSYNC, and CTL[3:1] Delay to DE rising edge1 DE high time1 DE low time1 SDA Data Valid Delay from SCL high to low transition ISEL/RST Signal High Time required for valid I2C reset Conditions Min 6 25 12 12 2 2 1.5 1.5 1.5 1.5 TCIP TCIP Max 40 165 80 81 Units ns MHz ns MHz ns ns ns ns ns ns ns ns ns ns ns µs EDGE = 0 EDGE = 0 EDGE = 1 EDGE = 1 8191TCIP 128TCIP CL = 400pf 50 1000 Notes 1. Guaranteed by design. 2. All TMDS signaling is guaranteed to meet the DVI 1.0 specifications. 2 3. All Standard mode I C (100kHz and 400kHz) timing requirements are guaranteed by design. 5 SiI-DS-0126-B SiI 1160 PanelLink Transmitter Data Sheet Input Timing Diagrams TCIP TCIH 80% VCC 80% VCC 80% VCC 20% VCC TCIL 20% VCC Figure 4. Clock Cycle High/Low Times IDCK TSIDF D[23:0], DE, HSYNC,VSYNC 50 % 50 % THIDF 50 % 50 % TSIDR THIDR Figure 5. Input Data Setup/Hold Time to IDCK DE 20% VCC DE 20% VCC TDDF VSYNC, HSYNC, CTL[3:1] 20% VCC VSYNC, HSYNC, CTL[3:1] TDDR 20% VCC Figure 6. VSYNC, HSYNC and CTL[3:1] Delay Time from DE THDE DE 80% VCC 80% VCC 20% VCC 20% VCC TLDE Figure 7. DE High and Low Times SiI-DS-0126-B 6 SiI 1160 PanelLink Transmitter Data Sheet VCCmax VCCmin VCC TRESET ISEL/RST Figure 8. Reset Timing at Pow er-Up or Prior to First I2C Access TRESET 7 SiI-DS-0126-B SiI 1160 PanelLink Transmitter Data Sheet Pin Descriptions Input Pins Pin Name DIE23DIE0 Pin # See SiI 1160 Pin Diagram Type Description In Input Even Data[23:0] corresponds to 24-bit pixel data for 1-pixel/clock input mode and to the first 24-bit pixel data for 2-pixels/clock mode. Input data is synchronized with Input data clock (IDCK). Data can be latched on the rising of the falling edge of IDCK depending on whether EDGE is high or low, respectively. Refer to TFT Panel Data Mapping in this document and DSTN Panel Data Mapping application note (SiI-AN-0007-A), which tabulates the relationship between the input data to the transmitter and output data from the Receiver In Input Odd Data[23:0] corresponds to the second 24-bit pixel data for 2-pixels/clock mode. Tie all pins to low when not in use. Input data is synchronized with Input data clock (IDCK). Data can be latched on the rising of the falling edge of IDCK depending on whether EDGE is high or low, respectively. Dual Link is not supported. In Input Data Clock. Input data and control signals can be valid either on the falling or the rising edge of IDCK as selected by the EDGE pin. In Input Data Enable. This signal qualifies the active data area. DE is always required by the transmitter and must be high during active display time and low during blanking time. In Horizontal Sync input control signal. In Vertical Sync input control signal. DIO23DIO0 See SiI 1160 Pin Diagram IDCK DE HSYNC VSYNC 80 78 76 77 Control and Configuration Pins Pin Name EDGE Pin # 24 Type Description In Data/Control Latching Edge. A LOW level indicates that all input signals(DIE/DIO[23:0], HSYNC, VSYNC, DE and CTL[3:1] are latched on the falling edge of IDCK, while a HIGH level(3.3V) indicates that all input signals are latched on the rising edge of IDCK. When the I2C interface is enabled (ISEL/RST=LOW), this pin is ignored and the EDGE register bit is used instead. In Pixel Select. A LOW level indicates one pixel (up to 24-bits) per clock mode using DIE[23:0]. A HIGH level (3.3V) indicates two pixels (up to 48-bits) per clock mode using DIE[23:0] for the first pixel and DIO[23:0] for the second pixel. In General Input control signal 1. Spread Spectrum Clock Input (future). A planned future variation of this device will allow a spread spectrum version of SS_CLK_OUT to be driven into this pin, at which time pin 29 will become CTL1. In General Input control signal 2. Out Spread Spectrum Clock Output (future). A planned future variation of this device will allow a clock to be driven out of this pin for conditioning by a spread spectrum device, at which time pin 28 will become CTL2. In General Input control signal 3. In Reserved. Must be tied HIGH for normal operation. Spread Spectrum Enable. A planned future variation of this device will use this pin to enable pins 83 and 84 to handle spread spectrum clock. Low = Spread Spectrum feature enabled on pins 83 and 84 High = Pins 83 and 84 are CTL2 and CTL1 outputs (default) PIXS 25 CTL1 SS_CLK_IN 84 CTL2 SS_CLK_OUT 83 CTL3 RSVD SS_EN# 82 27 SiI-DS-0126-B 8 SiI 1160 PanelLink Transmitter Data Sheet Power Management Pins Pin Name PD Pin # 26 Type Description In Power Down (active LOW). A HIGH level indicates normal operation. A LOW level indicates power down mode. During power down mode, all data (DIE/DIO[23:0]), data enable (DE), clock (IDCK) and control signals (HSYNC, VSYNC, CTL[3:1]), input buffers are disabled, all output buffers are tri-stated and all internal circuitry is powered down. When the I2C interface is enabled (ISEL/RST=LOW), this pin is ignored and the PD register bit is used instead. Tie this pin low if not used. Differential Signal Data Pins Pin Name TX0+ TX0TX1+ TX1TX2+ TX2TXC+ TXCEXT_SWING Pin # 40 39 43 42 46 45 35 34 32 Type Analog Analog Analog Analog Analog Analog Analog Analog Analog Description TMDS Low Voltage Differential Signal input data pairs. These pins are tri-stated when PD is asserted. TMDS Low Voltage Differential Signal input clock pair. These pins are tri-stated when PD is asserted. Voltage Swing Adjust. A resistor should tie this pin to AVCC. This resistor determines the amplitude of the voltage swing. A smaller resistor value sets a larger voltage swing and vice versa. For remote display applications with source termination, a 510Ω resistor is recommended (see page 24). Without the source termination, use a 560Ω resistor. Local Control (I2C) Interface The transmitter can operate with or without an I2C interface connection. Refer to the Feature Information section for details on using the I2C registers. Pin Name ISEL/RST Pin # 87 Type In Description I2C Interface Select. If LOW, then the I2C interface is active. If HIGH, the interface is inactive and chip configuration is taken from strap and default settings. This pin also acts as an asynchronous reset to the I2C interface controller. Switching this input from HIGH to LOW after a minimum TRESET high time resets the I2C logic. Monitor Sense. The behavior of this output depends on whether the I2C interface is enabled or disabled. No I2C (ISEL = HIGH) MSEN=HIGH: a powered on receiver is detected at the TMDS outputs. MSEN=LOW: a powered on receiver is not detected. This Receiver Sense function can only be used in DC-coupled systems. 2 I C enabled (ISEL = LOW) 2 The output is programmable through the I C interface and can indicate the Hot Plug or Receiver Sense signal state, or can instead generate a status change interrupt for those signals. This pin is an open collector output. An external pull-up resistor (5KΩ recommended) is required on this pin if the MSEN signal will be used. Otherwise the signal should be tied low. I2C Clock. When the I2C interface is enabled (ISEL=LOW), this pin acts as the I2C clock input. This pin is an open collector output. It must be pulled high to VCC through a resistor; a value of 2.2KΩ is recommended for I2C applications, 2-5KΩ otherwise. This pin is not 5V-tolerant. I2C Data. When the I2C interface is enabled (ISEL=LOW), this pin acts as the I2C data input and output. This pin is an open collector output. It must be pulled high to VCC through a resistor; a value of 2.2KΩ is recommended for I2C applications, 2-5KΩ otherwise. This pin is not 5V-tolerant. MSEN 21 Out SCL 20 In SDA 23 In/Out 9 SiI-DS-0126-B SiI 1160 PanelLink Transmitter Data Sheet Reserved Pins It is preferable to tie indicated pins HIGH through a 2-5KΩ resistor; direct connection to VCC is not recommended. Pin Name RSVD RSVD RSVD RSVD Pin # 22 28 29 38 Type In In In -Description Reserved. Must be tied HIGH for normal operation. Reserved. Must be tied HIGH for normal operation. Reserved. Must be tied HIGH for normal operation. Reserved. Should be left unconnected (but can be tied to AVCC for existing SiI 160 designs). Power and Ground Pins Pin Name VCC GND IVCC AVCC AGND PVCC1 PVCC2 PGND1 Pin # 8,30,56,88 7,31,57,67,79,89 17,66,81,98 36,44 33,37,41,47 18 85 19 Type Power Ground Power Power Ground Power Power Ground Description Digital Core VCC, must be set to 3.3V. Digital Core GND. Input VCC, must be set to 3.3V. Analog VCC must be set to 3.3V. Analog GND. Primary PLL Analog VCC must be set to 3.3V. Filter PLL Analog VCC must be set to 3.3V. PLL Analog GND. PGND1 should not be directly connected to PGND2 before being connected to the GROUND plane. They should be connected individually to the GROUND plane. PLL Analog GND. PGND2 should not be directly connected to PGND1 before being connected to the GROUND plane. They should be connected individually to the GROUND plane. PGND2 86 Ground SiI-DS-0126-B 10 SiI 1160 PanelLink Transmitter Data Sheet Feature Information I2C Interface The SiI 1160 Tx provides an I2C slave interface for more precise control of the chip features. Use of this interface is optional and is selected by the ISEL/RST pin. If not used, the chip register settings return to a default state; the EDGE and PD features then come under the control of the respective strap pins instead. The I2C slave state machine operates from an internal clock derived from the incoming SCL signal. No video clock and input is required to read and write to the I2C registers from address 0x00 to 0x0F. These accesses can also take place using only the SCL clock in power down mode. The transmitter responds to the seven-bit binary I2C address of 0x70. A read or write transaction is determined by bit 0 of the I2C address. Setting this bit to 0 will enable a write transaction and setting this bit to 1 will enable a read transaction. The I2C read operation is shown in Figure 9, and the write operation in Figure 10. Page mode is not supported. Start Start Bus Activity : Master Slave Address Register Address Slave Address SDA S A C K A C K S A C K Data No A C K Figure 9. I2C Byte Read Start Bus Activity : Master Slave Address Register Address Data Stop SDA S A C K A C K A C K P Figure 10. I2C Byte Write 11 SiI-DS-0126-B Stop P SiI 1160 PanelLink Transmitter Data Sheet I2C Register Mapping Addr. 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB0xD 0xE 0xF RSVD write to 00 EZONE RSVD write to 00 VEN RSVD RSVD write to 1000000 RSVD ZONEF ZONEO RSVD write to 001 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 VND_IDL VND_IDH DEV_IDL DEV_IDH DEV_REV RSVD FRQ_LOW FRQ_HIGH HEN RSVD write to 01 RSEN EDGE RSVD CTL0 PD 0x19 0x64 00110100 read only 10000001 5, 6 4 00000001 4 3, 5, 6 Default Value 0x01 0x00 0x06 0x00 0x00 4 Notes RSVD Notes: 1. Hexadecimal values use a prefix of ‘0x’. All values use bit 7 as most significant, bit 0 as least significant. 2. Read-only or read/write capabilities are noted on the next page. 3. On any reset assertion event, registers that have default values lose their previously programmed value and are set back to the default values listed. 4. Registers listed as RSVD and shaded gray are reserved for factory use and should not be accessed. 5. Write RSVD bits to the values indicated when writing other bits in the register. 6. Write PD to 1 for normal operation; write CTL0 to 0 for HDMI applications. SiI-DS-0126-B 12 SiI 1160 PanelLink Transmitter Data Sheet Table 1. General I2C Register Bits Register Name VND_IDL VND_IDH DEV_IDL DEV_IDH DEV_REV FRQ_LOW FRQ_HIGH HEN Access RO RO RO RO RO RO RO RW Description Vendor ID Low byte (0x01) Vendor ID High byte (0x00) Device ID Low byte (0x06) Device ID High byte (0x00) Device Revision (0x00) IDCK. Low frequency limit is 25MHz. (0x19) IDCK High frequency limit is 165MHz. Value is offset over 65MHz. (0x64) Horizontal Sync Enable 0 – HSYNC input is transmitted as fixed LOW 1 – HSYNC input is transmitted as input. → Default Vertical Sync Enable 0 – VSYNC input is transmitted as fixed LOW 1 – VSYNC input is transmitted as input. → Default Edge Select (same function as EDGE pin) 0 – Input data low order bits latched first → Default 1 – Input data high order bits latched first Power Down mode (same function as PD# pin) 0 – Power Down. → Default after RESET 1 – Normal operation Receiver Sense. This bit is HIGH if a powered on receiver is connected to the transmitter outputs, LOW otherwise. This function is only available for use in DC-coupled systems. Control 0. CTL0, CTL1, CTL2, CTL3 are sent over TMDS interface when DE is LOW. CTL1-3 are driven in from external pins, but CTL0 is not available externally and therefore must be set through this register. Set to 0 for HDMI applications. 0 – Transmit CTL0 as LOW 1 – Transmit CTL0 as HIGH Note that when not in I2C mode, CTL0 is always transmitted as HIGH. VEN RW EDGE RW PD RW RSEN CTL0 RO RW Notes: 1. RO = Read Only Registers 2. RW = Read/Write Registers 3. ‘Default’ indicates value set after a reset event. Not all bits default to a defined state after reset. Dual Zone PLL The SiI 1160 Tx offers a dual-zone PLL that changes its operational parameters depending on the frequency zone selected. In the low zone, operation is ideal in the low frequency range, from 20MHz to around 120MHz. High zone operation is optimized in the high frequency range, above 100MHz. In the overlapping range, either low zone or high zone operation can be used. Operating zone optimization contributes to robust operation over long cables. For example, optimized PLL characteristics account for the ability of the transmitter to send video at UXGA over 20m cables. PLL zone selection is controlled either manually or automatically. Manual zone control is the preferred mode of operation. Manual Zone Control Whenever the application allows it, PLL zone selection should be made manually. The I2C register bits ZONEF and EZONE allow the host graphics controller to set the optimal zone for the current video resolution being transmitted. For frequencies over 100MHz, the controller should select high zone PLL operation. Table 2 describes the relevant register bits. 13 SiI-DS-0126-B SiI 1160 PanelLink Transmitter Data Sheet Automatic Zone Control For applications that are not able to program the I2C registers, the chip incorporates an automatic zone control circuit. This circuit determines whether the input pixel clock is operating in the low frequency range or the high frequency range, and sets the PLL zone selection accordingly. The chip defaults to the automatic mode of zone selection after reset. The zone determination depends primarily on input frequency, but is also affected by operating voltage and chip temperature. Therefore, it is possible for an automatic zone switch to occur while video input is stable, causing momentary (~1µs) unevenness in the video output clock and data streams. This could occur, for example, while the chip is still warming up to its normal operating temperature. However, the automatic selection circuit provides wide hysteresis to ensure that there will not be any oscillation around the zone switch point. Table 2. Dual Zone PLL I2C Control Register Bits Register Name ZONEF Access RW Description Zone Force. Enable external selection of main PLL operating zone. When ZONEF=1, the main PLL zone is selected by EZONE. 0 – Automatic zone selection – EZONE bit disabled (default) 1 – Manual zone selection – EZONE bit enabled External Zone Select. Selects operating zone of main PLL, but only when ZONEF=1 (disabled by default). 0 – Low zone (recommended for 20-120MHz) 1 – High zone (recommended for > 100MHz) Zone Output – indicates current operating zone. When ZONEF=0 (automatic), ZONEO indicates that PLL is operating in zone optimized for: 0 = Lower frequencies 1 = Higher frequencies. When ZONEF=1 (manual), ZONEO information is not used. EZONE RW ZONEO RO Reset Description The input pin ISEL/RST serves as an asynchronous reset for the I2C slave controller in I2C mode. The programming registers, which are accessible over the I2C bus, lose their previously programmed values as soon as ISEL/RST is switched from HIGH to LOW. I2C registers whose default values are not correct for normal operation must then be manually set to their appropriate value. ISEL/RST serves only to set the registers to their default values, and to restore the interface to a known initial state. Without an initial reset, the I2C interface may not respond properly. The minimum ISEL/RST high time for proper reset, after nominal VCC values have been reached, is TRESET. Register bit function PD is disabled after reset to eliminate any unexpected chip output before initialization. The state of this bit is set during the reset period according to the following rule: After a reset, the chip is turned off; the power down control bit, PD, is forced to 0. When the chip comes out of reset (ISEL/RST goes LOW), the TMDS outputs will be disabled and the transmitter will be turned off. To turn the transmitter back on, the PD bit must be set to 1 over the I2C bus. SiI-DS-0126-B 14 SiI 1160 PanelLink Transmitter Data Sheet TFT Panel Data Mapping The following TFT data mapping tables are strictly listed for single link TFT applications only. For DSTN mapping please refer to Application Note SiI-AN-0007-A. SiI 1151 and SiI 1161 have the same pinout. Table 3. One Pixel/Clock Input/Output TFT Mode TFT VGA Output 24-bpp 18-bpp B0 B1 B2 B3 B4 B5 B6 B7 G0 G1 G2 G3 G4 G5 G6 G7 R0 R1 R2 R3 R4 R5 R6 R7 Shift CLK VSYNC HSYNC DE Tx Input Data Rx Output Data TFT Panel Input 1160 164 1161 141B 24-bpp 18-bpp DIE0 DIE1 DIE2 DIE3 DIE4 DIE5 DIE6 DIE7 DIE8 DIE9 DIE10 DIE11 DIE12 DIE13 DIE14 DIE15 DIE16 DIE17 DIE18 DIE19 DIE20 DIE21 DIE22 DIE23 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 QE0 QE1 QE2 QE3 QE4 QE5 QE6 QE7 QE8 QE9 QE10 QE11 QE12 QE13 QE14 QE15 QE16 QE17 QE18 QE19 QE20 QE21 QE22 QE23 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17 Q18 Q19 Q20 Q21 Q22 Q23 B0 B1 B2 B3 B4 B5 B6 B7 G0 G1 G2 G3 G4 G5 G6 G7 R0 R1 R2 R3 R4 R5 R6 R7 B0 B1 B2 B3 B4 B5 B0 B1 B2 B3 B4 B5 G0 G1 G2 G3 G4 G5 G0 G1 G2 G3 G4 G5 R0 R1 R2 R3 R4 R5 R0 R1 R2 R3 R4 R5 Shift IDCK IDCK ODCK ODCK Shift CLK Shift CLK CLK VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC VSYNC HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC HSYNC DE DE DE DE DE DE DE For 18-bit mode, the Flat Panel Graphics Controller interfaces to the transmitter exactly the same as in the 24-bit mode; however, 6 bits per channel (color) are used instead of 8. It is recommended that unused data bits be tied low. As can be seen from the above table, the data mapping for less than 24-bit per pixel interfaces are MSB justified. The data is sent during active display time while the control signals are sent during blank time. Note that the three data channels (CH0, CH1, CH2) are mapped to Blue, Green and Red data respectively. 15 SiI-DS-0126-B SiI 1160 PanelLink Transmitter Data Sheet Table 4. Tw o Pixels/Clock Input/Output TFT Mode TFT VGA Output 24-bpp 18-bpp B0 - 0 B1 - 0 B2 - 0 B3 - 0 B4 - 0 B5 - 0 B6 - 0 B7 - 0 G0 - 0 G1 - 0 G2 - 0 G3 - 0 G4 - 0 G5 - 0 G6 - 0 G7 - 0 R0 - 0 R1 - 0 R2 - 0 R3 - 0 R4 - 0 R5 - 0 R6 - 0 R7 - 0 B0 - 1 B1 - 1 B2 - 1 B3 - 1 B4 - 1 B5 - 1 B6 - 1 B7 - 1 G0 - 1 G1 - 1 G2 - 1 G3 - 1 G4 - 1 G5 - 1 G6 - 1 G7 - 1 R0 - 1 R1 - 1 R2 - 1 R3 - 1 R4 - 1 R5 - 1 R6 - 1 R7 - 1 ShiftClk/2 VSYNC HSYNC DE Tx Input Data Rx Output Data 1160 1161 DIE0 DIE1 DIE2 DIE3 DIE4 DIE5 DIE6 DIE7 DIE8 DIE9 DIE10 DIE11 DIE12 DIE13 DIE14 DIE15 DIE16 DIE17 DIE18 DIE19 DIE20 DIE21 DIE22 DIE23 DIO0 DIO1 DIO2 DIO3 DIO4 DIO5 DIO6 DIO7 DIO8 DIO9 DIO10 DIO11 DIO12 DIO13 DIO14 DIO15 DIO16 DIO17 DIO18 DIO19 DIO20 DIO21 DIO22 DIO23 IDCK VSYNC HSYNC DE QE0 QE1 QE2 QE3 QE4 QE5 QE6 QE7 QE8 QE9 QE10 QE11 QE12 QE13 QE14 QE15 QE16 QE17 QE18 QE19 QE20 QE21 QE22 QE23 QO0 QO1 QO2 QO3 QO4 QO5 QO6 QO7 QO8 QO9 QO10 QO11 QO12 QO13 QO14 QO15 QO16 QO17 QO18 QO19 QO20 QO21 QO22 QO23 ODCK VSYNC HSYNC DE TFT Panel Input 24-bpp 18-bpp B0 - 0 B1 - 0 B2 - 0 B3 - 0 B4 - 0 B5 - 0 B6 - 0 B7 - 0 G0 - 0 G1 - 0 G2 - 0 G3 - 0 G4 - 0 G5 - 0 G6 - 0 G7 - 0 R0 - 0 R1 - 0 R2 - 0 R3 - 0 R4 - 0 R5 - 0 R6 - 0 R7 - 0 B0 - 1 B1 - 1 B2 - 1 B3 - 1 B4 - 1 B5 - 1 B6 - 1 B7 - 1 G0 - 1 G1 - 1 G2 - 1 G3 - 1 G4 - 1 G5 - 1 G6 - 1 G7 - 1 R0 - 1 R1 - 1 R2 - 1 R3 - 1 R4 - 1 R5 - 1 R6 - 1 R7 - 1 Shift CLK VSYNC HSYNC DE B0 - 0 B1 - 0 B2 - 0 B3 - 0 B4 - 0 B5 - 0 B0 - 0 B1 - 0 B2 - 0 B3 - 0 B4 - 0 B5 - 0 G0 - 0 G1 - 0 G2 - 0 G3 - 0 G4 - 0 G5 - 0 G0 - 0 G1 - 0 G2 - 0 G3 - 0 G4 - 0 G5 - 0 R0 - 0 R1 - 0 R2 - 0 R3 - 0 R4 - 0 R5 - 0 R0 - 0 R1 - 0 R2 - 0 R3 - 0 R4 - 0 R5 - 0 B0 - 1 B1 - 1 B2 - 1 B3 - 1 B4 - 1 B5 - 1 B0 - 1 B1 - 1 B2 - 1 B3 - 1 B4 - 1 B5 - 1 G0 - 1 G1 - 1 G2 - 1 G3 - 1 G4 - 1 G5 - 1 G0 - 1 G1 - 1 G2 - 1 G3 - 1 G4 - 1 G5 - 1 R0 - 1 R1 - 1 R2 - 1 R3 - 1 R4 - 1 R5 - 1 ShiftClk/2 VSYNC HSYNC DE R0 - 1 R1 - 1 R2 - 1 R3 - 1 R4 - 1 R5 - 1 Shift CLK VSYNC HSYNC DE SiI-DS-0126-B 16 SiI 1160 PanelLink Transmitter Data Sheet Table 5. 24-bit One Pixel/Clock Input w ith 24-bit Tw o Pixels/Clock Output TFT Mode TFT VGA Output 24-bpp B0 B1 B2 B3 B4 B5 B6 B7 G0 G1 G2 G3 G4 G5 G6 G7 R0 R1 R2 R3 R4 R5 R6 R7 Tx Input Data 1160 164 DIE0 DIE1 DIE2 DIE3 DIE4 DIE5 DIE6 DIE7 DIE8 DIE9 DIE10 DIE11 DIE12 DIE13 DIE14 DIE15 DIE16 DIE17 DIE18 DIE19 DIE20 DIE21 DIE22 DIE23 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 Rx Output Data TFT Panel Input 1161 24-bpp QE0 QE1 QE2 QE3 QE4 QE5 QE6 QE7 QE8 QE9 QE10 QE11 QE12 QE13 QE14 QE15 QE16 QE17 QE18 QE19 QE20 QE21 QE22 QE23 QO0 QO1 QO2 QO3 QO4 QO5 QO6 QO7 QO8 QO9 QO10 QO11 QO12 QO13 QO14 QO15 QO16 QO17 QO18 QO19 QO20 QO21 QO22 QO23 ODCK VSYNC HSYNC DE B0 - 0 B1 - 0 B2 - 0 B3 - 0 B4 - 0 B5 - 0 B6 - 0 B7 - 0 G0 - 0 G1 - 0 G2 - 0 G3 - 0 G4 - 0 G5 - 0 G6 - 0 G7 - 0 R0 - 0 R1 - 0 R2 - 0 R3 - 0 R4 - 0 R5 - 0 R6 - 0 R7 - 0 B0 - 1 B1 - 1 B2 - 1 B3 - 1 B4 - 1 B5 - 1 B6 - 1 B7 - 1 G0 - 1 G1 - 1 G2 - 1 G3 - 1 G4 - 1 G5 - 1 G6 - 1 G7 - 1 R0 - 1 R1 - 1 R2 - 1 R3 - 1 R4 - 1 R5 - 1 R6 - 1 R7 - 1 Shift CLK/2 VSYNC HSYNC DE Shift CLK VSYNC HSYNC DE IDCK VSYNC HSYNC DE IDCK VSYNC HSYNC DE 17 SiI-DS-0126-B SiI 1160 PanelLink Transmitter Data Sheet Table 6. 18-bit One Pixel/Clock Input w ith 18-bit Tw o Pixels/Clock Output TFT Mode TFT VGA Output 18-bpp Tx Input Data 1160 164 DIE0 DIE1 DIE2 DIE3 DIE4 DIE5 DIE6 DIE7 DIE8 DIE9 DIE10 DIE11 DIE12 DIE13 DIE14 DIE15 DIE16 DIE17 DIE18 DIE19 DIE20 DIE21 DIE22 DIE23 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 Tx Output Data 1161 141B QE0 QE1 QE2 QE3 QE4 QE5 QE6 QE7 QE8 QE9 QE10 QE11 QE12 QE13 QE14 QE15 QE16 QE17 QE18 QE19 QE20 QE21 QE22 QE23 QO0 QO1 QO2 QO3 QO4 QO5 QO6 QO7 QO8 QO9 QO10 QO11 QO12 QO13 QO14 QO15 QO16 QO17 QO18 QO19 QO20 QO21 QO22 QO23 ODCK VSYNC HSYNC DE TFT Panel Input 18-bpp B0 B1 B2 B3 B4 B5 Q0 Q1 Q2 Q3 Q4 Q5 B0 - 0 B1 - 0 B2 - 0 B3 - 0 B4 - 0 B5 - 0 G0 G1 G2 G3 G4 G5 Q6 Q7 Q8 Q9 Q10 Q11 G0 - 0 G1 - 0 G2 - 0 G3 - 0 G4 - 0 G5 - 0 R0 R1 R2 R3 R4 R5 Q12 Q13 Q14 Q15 Q16 Q17 R0 - 0 R1 - 0 R2 - 0 R3 - 0 R4 - 0 R5 - 0 Q18 Q19 Q20 Q21 Q22 Q23 B0 - 1 B1 - 1 B2 - 1 B3 - 1 B4 - 1 B5 - 1 Q24 Q25 Q26 Q27 Q28 Q29 G0 - 1 G1 - 1 G2 - 1 G3 - 1 G4 - 1 G5 - 1 Shift CLK VSYNC HSYNC DE IDCK VSYNC HSYNC DE IDCK VSYNC HSYNC DE Q30 Q31 Q32 Q33 Q34 Q35 Shift CLK/2 VSYNC HSYNC DE R0 - 1 R1 - 1 R2 - 1 R3 - 1 R4 - 1 R5 - 1 Shift CLK/2 VSYNC HSYNC DE SiI-DS-0126-B 18 SiI 1160 PanelLink Transmitter Data Sheet Table 7. Tw o Pixels/Clock Input w ith One Pixel/Clock Output TFT Mode TFT VGA Output 24-bpp 18-bpp B0 - 0 B1 - 0 B2 - 0 B3 - 0 B4 - 0 B5 - 0 B6 - 0 B7 - 0 G0 - 0 G1 - 0 G2 - 0 G3 - 0 G4 - 0 G5 - 0 G6 - 0 G7 - 0 R0 - 0 R1 - 0 R2 - 0 R3 - 0 R4 - 0 R5 - 0 R6 - 0 R7 - 0 B0 - 1 B1 - 1 B2 - 1 B3 - 1 B4 - 1 B5 - 1 B6 - 1 B7 - 1 G0 - 1 G1 - 1 G2 - 1 G3 - 1 G4 - 1 G5 - 1 G6 - 1 G7 - 1 R0 - 1 R1 - 1 R2 - 1 R3 - 1 R4 - 1 R5 - 1 R6 - 1 R7 - 1 ShiftClk/2 VSYNC HSYNC DE Tx Input Data 1160 DIE0 DIE1 DIE2 DIE3 DIE4 DIE5 DIE6 DIE7 DIE8 DIE9 DIE10 DIE11 DIE12 DIE13 DIE14 DIE15 DIE16 DIE17 DIE18 DIE19 DIE20 DIE21 DIE22 DIE23 DIO0 DIO1 DIO2 DIO3 DIO4 DIO5 DIO6 DIO7 DIO8 DIO9 DIO10 DIO11 DIO12 DIO13 DIO14 DIO15 DIO16 DIO17 DIO18 DIO19 DIO20 DIO21 DIO22 DIO23 IDCK VSYNC HSYNC DE Rx Output Data 1161 141B QE0 QE1 QE2 QE3 QE4 QE5 QE6 QE7 QE8 QE9 QE10 QE11 QE12 QE13 QE14 QE15 QE16 QE17 QE18 QE19 QE20 QE21 QE22 QE23 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17 Q18 Q19 Q20 Q21 Q22 Q23 TFT Panel Input 24-bpp 18-bpp B0 B1 B2 B3 B4 B5 B6 B7 G0 G1 G2 G3 G4 G5 G6 G7 R0 R1 R2 R3 R4 R5 R6 R7 B0 - 0 B1 - 0 B2 - 0 B3 - 0 B4 - 0 B5 - 0 B0 B1 B2 B3 B4 B5 G0 - 0 G1 - 0 G2 - 0 G3 - 0 G4 - 0 G5 - 0 G0 G1 G2 G3 G4 G5 R0 - 0 R1 - 0 R2 - 0 R3 - 0 R4 - 0 R5 - 0 R0 R1 R2 R3 R4 R5 B0 - 1 B1 - 1 B2 - 1 B3 - 1 B4 - 1 B5 - 1 G0 - 1 G1 - 1 G2 - 1 G3 - 1 G4 - 1 G5 - 1 R0 - 1 R1 - 1 R2 - 1 R3 - 1 R4 - 1 R5 - 1 ShiftClk/2 VSYNC HSYNC DE ODCK VSYNC HSYNC DE ODCK VSYNC HSYNC DE ShiftClk VSYNC HSYNC DE ShiftClk VSYNC HSYNC DE 19 SiI-DS-0126-B SiI 1160 PanelLink Transmitter Data Sheet Design Recommendations Differences Between SiI 160 and SiI 1160 The SiI 1160 Tx is a pin-compatible upgrade to the SiI 160 Tx. It provides improved cable length support without any changes to the pinout. Interrupt capability is also a new option using the optional MSEN pin. The SiI 1160 Tx can also act as to repeat HDMI signals when its internal registers are programmed appropriately; this application requires the use of an I2C interface, optionally available on the SDA and SCL pins. Table 8. New Pin Functions for SiI 1160 Tx Pin 20 21 23 87 SiI 160 RSVD – Tied HIGH RSVD – Tied LOW RSVD – Tied HIGH RSVD – Tied HIGH SiI 1160 Optional I2C interface pin SCL Optional interrupt output MSEN Optional I2C interface pin SDA ISEL/RST EXT_SWING Selection The recommended REXT_SWING resistor value for the EXT_SWING pin is provided in the Pin Descriptions section. This value can be adjusted as needed to optimize the DVI signal swing levels according to the needs of the application. This adjustment might become necessary, for example, when deviating from the recommended source termination values (described in the Source Termination Resistors on Differential Outputs section) to optimize for a specific cabling environment. PCB Ground Planes All ground pins on the device should be connected to the same, contiguous ground plane in the PCB. This helps to avoid ground loops and inductances from one ground plane segment to another. Such low-inductance ground paths are critical for return currents, which affect EMI performance. The entire ground plane surrounding the PanelLink transmitter should be one piece, and include the ground vias for the DVI connector. Voltage Ripple Regulation The power supply to PVCC is very important to the proper operation of the Transmitter chips. PVCC does not draw much current so any voltage regulator that can supply 50mA or more is sufficient. A suggested regulator circuit using a low-dropout regulator is shown in Figure 11. Note that alternative voltage regulator circuits should be considered only if they meet the LM317 standards of line/load regulation. Decoupling and bypass capacitors are also involved with power supply connections, as described in detail in Figure 14 and Figure 15. LM317EMP Vin 12V Vin ADJ Vout 240 Ω 1% Vout 3.3V 390 Ω 1% Figure 11. Voltage Regulation using LM317EMP SiI-DS-0126-B 20 SiI 1160 PanelLink Transmitter Data Sheet Spread Spectrum Support TMDS architecture is inherently jitter-tolerant. Spread spectrum clocking can be applied to the clock and parallel data inputs of the SiI 1160 to allow for reduced EMI. The spread will be propagated throughout the system due to TMDS clock architecture, which passes nearly all low-frequency components of the incoming clock without attenuation. The amount of spread that can be applied without affecting the DVI eye is limited to ±0.5% with the current part, depending on the spreading algorithm employed by the external spread spectrum device. A planned future variation of this chip will allow its internal clock to be coupled directly to a spread spectrum device. The expected result will be the ability to accommodate larger amounts of spread, and it will also work in 48-bit mode as well as 24-bit mode. Designs should make accommodations using pins 27, 83, and 84 as noted in the Pin Descriptions section so that the planned part can become a drop-in replacement for the SiI 1160. Figure 12 illustrates how a design can anticipate the expected future chip version. Contact PhaseLink Corporation for additional information on their spread spectrum device. 3.3V 1160: Stuff SS: Stuff 27-SS_EN# SiI 1160 / or future SS version 83-SS_CLK_OUT 84-SS_CLK_IN 1160: No Stuff SS: Stuff 0Ω PhaseLink PLL701-21 1-FIN VDD-8 S3-7 2-S2 3-S1 FOUT-6 4-S0 GND-5 3.3V 3.3V Figure 12. Planned Spread Spectrum Support Circuit 21 SiI-DS-0126-B SiI 1160 PanelLink Transmitter Data Sheet Reset Circuit for I2C Application If the design uses the I2C interface to control the transmitter features, it must also provide a means of toggling the ISEL/RST pin to achieve the correct TRESET timing. If a local microcontroller is hosting the I2C connection, the easiest way to provide the reset is to connect a GPIO pin from the microcontroller to the transmitter chip as shown in Figure 13. The reset pulse can then be commanded either at power-up time or just prior to initial use of the I2C interface as shown in Figure 8. uC SiI 1160 SCL SDA ISEL/RST Figure 13. Typical Reset Circuit Power Control The low-power standby state feature of the chip provides a design option of leaving the chip always powered, as opposed to powering it on and off. Leaving the chip powered and using the PD pin to put it in a lower power state may result in faster system response time, depending on the system Vcc supply ramp-up delay. Table 9 provides information on chip functional mode current requirements. These values are not specifications, but are representative of typical chip power consumption. PVCC1 and PVCC2 are the power planes that are most sensitive to excessive noise. Noise on these planes can be more easily controlled when they are regulated separately from digital VCC. Table 9. Pow er Consumption Characteristics Symbol ICCT IAVCC IPVCC1 IPVCC2 IVCC + IIVCC IVCCPD + IIVCCPD Parameter Total Transmitter Operating Current Current on AVCC Current on PVCC1 Current on PVCC2 Current on digital core VCC and input plan IVCC Standby mode current on VCC and IVCC Conditions 165MHz Typ 17-19 31-33 10-11 38-41 >97 Units see spec. % of total ICCT % of total ICCT % of total ICCT % of total ICCT % of total IPD PD pin driven low1 DVI clock stopped Note 2 1. For I C mode: bit PD=0. SiI-DS-0126-B 22 SiI 1160 PanelLink Transmitter Data Sheet Decoupling Capacitors Designers should include decoupling and bypass capacitors at each power pin in the layout. These are shown schematically in Figure 15. Place these components as close as possible to the PanelLink device pins, and avoid routing through vias if possible, as shown in Figure 14, which is representative of the various types of power pins on the transmitter. VCC C1 C2 L1 VCC Ferrite GND Via to GND C3 Figure 14. Decoupling and Bypass Capacitor Placement VCC L1 VCCPIN C1 C2 C3 Figure 15. Decoupling and Bypass Schematic The values shown in Table 10 are recommendations that should be adjusted according to the noise characteristics of the specific board-level design. Pins in one group (such as IVCC) may share C2, L1, and C3, each pin having C1 placed as close to the pin as possible. PGND1 and PGND2 should be tied individually to ground. Table 10. Recommended Components for Bypass and Decoupling Circuits C1 100 – 300 pF C2 2.2 – 10 uF C3 10 uF L1 200+ Ω 23 SiI-DS-0126-B SiI 1160 PanelLink Transmitter Data Sheet Series Damping Resistors on Outputs Series resistors are often effective in lowering data-related emissions and reducing reflections. Series resistors with a value close to the impedance of the board traces are generally most effective in reducing reflections from the inputs of the transmitter. If used, resistors should be placed close to the output pins of the VGA Source or Graphics chip, as shown in Figure 16. DIE[0..23]/ DIO[0..23] VGA Figure 16. Series Input Damping Resistors for Driving Source Source Termination Resistors on Differential Outputs Source termination, consisting of a 300Ω resistor and a 0.1µF capacitor, may be used on the differential outputs of the SiI 1160 to improve signal swings. See Figure 17 for an illustration. Repeat the circuit for each of the four differential output pairs: TX0+, TX1+, TX2+, TXC+. Note that the specific value for the source termination resistor and capacitor will depend on the PCB layout and construction. Different values may be needed to create optimum DVI-compliant output waveforms from the transmitter. TX0+ TX0TX1+ TX2TX3+ TX3TXC+ TXC0.1uF 300 ohm 0.1uF 300 ohm 0.1uF 300 ohm 0.1uF 300 ohm Figure 17. Differential Output Source Terminations Source termination suppresses signal reflection to prevent non-DVI compliant receivers from erroneously sampling the TMDS signals at high frequencies (beyond 135MHz). The impact on DVI compliant receivers is minimal. Therefore Silicon Image recommends source termination for most applications. Note that the capacitor is required to meet DVI idle mode DC offset requirements and must not be omitted. Note also that the signal suppression requires the REXT_SWING value to be changed. Power consumption will be slightly higher when using source termination. SiI-DS-0126-B 24 SiI 1160 PanelLink Transmitter Data Sheet C R Detail of Source termination (magnified) R and C 0603 components installed. Figure 18. Source Termination Layout Illustration The layout in Figure 18 has been developed to minimize trace stubs on the differential TMDS lines, while providing pads for the source termination components (left-hand magnified view). Source termination components should be placed close to the transmitter pins. The resistor and capacitor are shown installed on the pads provided (right-hand magnified view). Differential Trace Routing The routing for the SiI 1160 chip is relatively simple since no spiral skew compensation is needed. However, a few small precautions are required to achieve the full performance and reliability of DVI. The Transmitter can be placed fairly far from the output connector, but care should be taken to route each differential signal pair together and achieve impedance of 100Ω between the differential signal pair. However, note that the longer the differential traces are between the transmitter and the output connector, the higher the chance that external signal noise will couple onto the low-voltage signals and affect image quality. Do not split or have asymmetric trace routing between the differential signal pair. Vias are very inductive and can cause phase delay problems if applied unevenly within a differential pair. Vias should be minimized or avoided if possible by placing all differential traces on the top layer of the PCB. Figure 19 illustrates an incorrect routing of the differential signal from the SiI 1160 to the DVI connector. Figure 20 illustrates the correct method to route the differential signal from the SiI 1160 to the DVI connector. Figure 21 illustrates recommended routing for differential traces at the DVI connector. 25 SiI-DS-0126-B SiI 1160 PanelLink Transmitter Data Sheet TX Figure 19. Example of Incorrect Differential Signal Routing TX Figure 20. Example of Correct Differential Signal Routing 24 16 8 17 9 1 TxCTxC+ Figure 21. Differential Trace Routing to DVI Connector (Top Side View ) Tx2Tx2+ Tx1Tx1+ Tx0Tx0+ SiI-DS-0126-B 26 SiI 1160 PanelLink Transmitter Data Sheet In addition to following the trace routing recommendations, length differences between intra-pair traces listed in column 2 of Table 11 and inter-pair traces listed in column 3 of Table 11, should be controlled to minimize DVI skew. Spacing between inter-pair DVI traces should be observed to reduce trace-to-trace couplings. For example, having wider gaps between inter-pair DVI traces will minimize noise coupling. It is also strongly advised that ground not be placed adjacent to the DVI traces on the same layer. Table 11 lists the recommended limits for the parameters listed above. Table 11. Routing Guidelines for DVI Traces Intra-pair (length of each trace within a pair) +0.75 inch Parameter Inter-pair (length of each pair compared to other pairs) +3 inch Recommended Inter–pair Trace Separation Based on 2 Layer Board Recommended Inter– pair Trace Separation Based on 4 Layer Board Max Min 2x trace width 2x trace width 27 SiI-DS-0126-B SiI 1160 PanelLink Transmitter Data Sheet Package Dimensions Package 100-pin TQFP Package Dimensions and Marking Specification L1 JEDEC Package Code MS-026-AED typ max 1.20 0.15 1.00 14.00 14.00 16.00 16.00 1.00 0.20 0.20 0.50 1.05 TMDS™ Device # Lot # Date Code Trace Code SiI1160CTU LLLLLL.LLLL YYWW TTTTTTm E1 F1 A A1 A2 D1 E1 F1 G1 L1 b c e Thickness Stand-off Body Thickness Body Size Body Size Footprint Footprint Lead Length Lead Width Lead Thickness Lead Pitch Dimensions in millimeters. Overall thickness A=A1+A2. D1 G1 c A2 A1 e b Package: SiI1160CTU Legend LLLLLL.LLLL YY WW TTTTTT m Description Lot Number Year of Mfr Week of Mfr Trace Code Maturity Code =0: engineering samples =1: pre-production >1: production Figure 22. 100-pin TQFP Package Dimensions (JEDEC code MS-026-AED) Ordering Information Standard Part Number: SiI1160CTU (‘U’ indicates Universal package usable in both standard and lead-free environments) SiI-DS-0126-B 28 SiI 1160 PanelLink Transmitter Data Sheet © 2005 Silicon Image. Inc. SiI-DS-0126-B Silicon Image, Inc. 1060 E. Arques Avenue Sunnyvale, CA 94085 USA Tel: Fax: E-mail: Web: (408) 616-4000 (408) 830-9530 salessupport@siimage.com www.siliconimage.com 29 SiI-DS-0126-B