CLC2011, CLC4011
Low Power, Low Cost, Rail-to-Rail I/O Amplifiers
FE ATU R E S
■■ 136μA supply current
■■ 4.9MHz bandwidth
■■ Output swings to within 20mV of either rail
■■ Input voltage range exceeds the rail by
>250mV
■■ 5.3V/μs slew rate
■■ 21nV/√Hz input voltage noise
■■ ±35mA linear output current
■■ Fully specified at 2.7V and 5V supplies
General Description
The CLC2011 (dual) and CLC4011 (quad) are ultra-low cost, low power,
voltage feedback amplifiers. At 2.7V, the CLCx011 family uses only 136μA
of supply current per amplifier and are designed to operate from a supply
range of 2.5V to 5.5V (±1.25 to ±2.75). The input voltage range exceeds the
negative and positive rails.
The CLCx011 family of amplifiers offer high bipolar performance at a low
CMOS prices. They offer superior dynamic performance with 4.9MHz small
signal bandwidths and 5.3V/μs slew rates. The combination of low power,
high bandwidth, and rail-to-rail performance make the CLCx011 amplifiers
well suited for battery-powered communication/computing systems.
A P P LICATION S
■■ Portable/battery-powered applications
■■ Mobile communications, cell phones,
pagers
■■ ADC buffer
■■ Active filters
■■ Portable test instruments
■■ Notebooks and PDA’s
■■ Signal conditioning
■■ Medical equipment
■■ Portable medical instrumentation
Ordering Information - back page
Output Swing vs. Load
Large Signal Frequency Response
1.35
Output Voltage (0.27V/div)
V s = 5V
Magnitude (1dB/div)
V o = 1Vpp
V o = 4Vpp
V o = 2Vpp
R L = 10kΩ
R L = 1kΩ
0
R L = 75Ω
R L = 100Ω
R L = 200Ω
R L = 75/100Ω
-1.35
0.01
0.1
1
-2.0
10
Frequency (MHz)
© 2009 - 2014 Exar Corporation
0
2.0
Input Voltage (0.4V/div)
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Rev 1D
CLC2011, CLC4011
Absolute Maximum Ratings
Operating Conditions
Stresses beyond the limits listed below may cause
permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect
device reliability and lifetime.
Supply Voltage Range....................................................2.5 to 5.5V
Operating Temperature Range................................-40°C to 125°C
Junction Temperature............................................................ 150°C
Storage Temperature Range....................................-65°C to 150°C
Lead Temperature (Soldering, 10s).......................................260°C
VS...................................................................................... 0V to 6V
VIN............................................................. -VS - 0.5V to +VS +0.5V
Package Thermal Resistance
Continuous Output Current...................................-40mA to +40mA
θJA (SOIC-8)......................................................................150°C/W
θJA (MSOP-8)................................................................... 200°C/W
θJA (SOIC-14)..................................................................... 90°C/W
θJA (TSSOP-14).................................................................100°C/W
Package thermal resistance (θJA), JEDEC standard, multi-layer
test boards, still air.
ESD Protection
CLC2011, CLC4011 (HBM)........................................................2kV
ESD Rating for HBM (Human Body Model).
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Rev 1D
CLC2011, CLC4011
Electrical Characteristics at +2.7V
TA = 25°C, VS = +2.7V, Rf = Rg = 5kΩ, RL = 10kΩ to VS/2; G = 2; unless otherwise noted.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Frequency Domain Response
UGBWSS
Unity Gain -3dB Bandwidth
G = +1, VOUT = 0.02Vpp
4.9
MHz
BWSS
-3dB Bandwidth
G = +2, VOUT = 0.2Vpp
3.2
MHz
BWLS
Large Signal Bandwidth
G = +2, VOUT = 2Vpp
1.4
MHz
GBWP
Gain Bandwidth Product
G = +11, VOUT = 0.2Vpp
2.5
MHz
Time Domain Response
tR, tF
Rise and Fall Time
VOUT = 1V step; (10% to 90%)
163
ns
tS
Settling Time to 0.1%
VOUT = 1V step
500
ns
OS
Overshoot
VOUT = 1V step
10kHz
21
nV/√Hz
XTALK
Crosstalk
Channel to Channel, VOUT = 2Vpp, f = 10kHz
82
dB
Channel to Channel, VOUT = 2Vpp, f = 50kHz
74
dB
0.5
mV
μV/°C
DC Performance
VIO
Input Offset Voltage
dVIO
Average Drift
5
IB
Input Bias Current
90
nA
dIB
Average Drift
32
pA/°C
PSRR
Power Supply Rejection Ratio
DC
83
dB
AOL
Open Loop Gain
VOUT = VS / 2
90
dB
IS
Supply Current
per channel
136
μA
Non-inverting
12
MΩ
2
pF
-0.25 to
2.95
V
81
dB
RL = 10kΩ to VS / 2
0.02 to
2.68
V
RL = 1kΩ to VS / 2
0.05 to
2.63
V
RL = 200Ω to VS / 2
0.11 to
2.52
V
±30
mA
55
Input Characteristics
RIN
Input Resistance
CIN
Input Capacitance
CMIR
Common Mode Input Range
CMRR
Common Mode Rejection Ratio
DC
Output Characteristics
VOUT
IOUT
Output Voltage Swing
Output Current
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Rev 1D
CLC2011, CLC4011
Electrical Characteristics at +5V
TA = 25°C, VS = +5V, Rf = Rg = 5kΩ, RL = 10kΩ to VS/2; G = 2; unless otherwise noted.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Frequency Domain Response
UGBWSS
Unity Gain -3dB Bandwidth
G = +1, VOUT = 0.02Vpp
4.3
MHz
BWSS
-3dB Bandwidth
G = +2, VOUT = 0.2Vpp
3.0
MHz
BWLS
Large Signal Bandwidth
G = +2, VOUT = 2Vpp
2.3
MHz
GBWP
Gain Bandwidth Product
G = +11, VOUT = 0.2Vpp
2.5
MHz
Time Domain Response
tR, tF
Rise and Fall Time
VOUT = 1V step; (10% to 90%)
110
ns
tS
Settling Time to 0.1%
VOUT = 2V step
470
ns
OS
Overshoot
VOUT = 1V step
10kHz
22
nV/√Hz
XTALK
Crosstalk
Channel to Channel, VOUT = 2Vpp, f = 10kHz
82
dB
Channel to Channel, VOUT = 2Vpp, f = 50kHz
74
dB
DC Performance
VIO
Input Offset Voltage
-8
dVIO
Average Drift
15
IB
Input Bias Current
90
dIB
Average Drift
40
pA/°C
PSRR
Power Supply Rejection Ratio
DC
85
dB
AOL
Open Loop Gain
VOUT = VS / 2
80
IS
Supply Current
per channel
160
Non-inverting
12
MΩ
2
pF
-0.25 to
5.25
V
58
80
dB
0.08 to
4.92
0.04 to
4.96
V
RL = 1kΩ to VS / 2
0.07 to
4.9
V
RL = 200Ω to VS / 2
0.14 to
4.67
V
±35
mA
55
1.5
8
mV
μV/°C
450
nA
dB
235
μA
Input Characteristics
RIN
Input Resistance
CIN
Input Capacitance
CMIR
Common Mode Input Range
CMRR
Common Mode Rejection Ratio
DC
Output Characteristics
RL = 10kΩ to VS / 2
VOUT
IOUT
Output Voltage Swing
Output Current
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Rev 1D
CLC2011, CLC4011
CLC2011 Pin Configurations
CLC2011 Pin Assignments
SOIC-8 / MSOP-8
SOIC-8 / MSOP-8
OUT1
1
-IN1
2
+IN1
3
-Vs
+
4
+
Pin No.
Pin Name
Description
1
OUT1
8
+Vs
2
-IN1
Negative input, channel 1
7
OUT2
3
+IN1
Positive input, channel 1
4
-VS
6
-IN2
5
+IN2
Positive input, channel 2
+IN2
6
-IN2
Negative input, channel 2
7
OUT2
8
+VS
5
Output, channel 1
Negative supply
Output, channel 2
Positive supply
CLC4011 Pin Configuration
CLC4011 Pin Assignments
SOIC-14 / TSSOP-14
SOIC-14 / TSSOP-14
OUT1
1
14
OUT4
-IN1
2
13
-IN4
+IN1
3
12
+IN4
+VS
4
11
-VS
+IN2
5
10
+IN3
-IN2
6
9
-IN3
OUT2
7
8
OUT3
© 2009 - 2014 Exar Corporation
Pin No.
Pin Name
1
OUT1
Description
2
-IN1
Negative input, channel 1
3
+IN1
Positive input, channel 1
4
+VS
Positive supply
5
+IN2
Positive input, channel 2
6
-IN2
Negative input, channel 2
7
OUT2
Output, channel 2
8
OUT3
Output, channel 3
9
-IN3
Negative input, channel 3
10
+IN3
Positive input, channel 3
Output, channel 1
11
-VS
12
+IN4
Positive input, channel 4
13
-IN4
Negative input, channel 4
14
OUT4
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Negative supply
Output, channel 4
exar.com/CLC2011
Rev 1D
CLC2011, CLC4011
Typical Performance Characteristics
TA = 25°C, VS = +2.7V, Rf = Rg = 5kΩ, RL = 10kΩ to VS/2; G = 2; unless otherwise noted.
V o = 0.2Vpp
Inverting Frequency Response at VS = 5V
Normalized Magnitude (1dB/div)
Normalized Magnitude (1dB/div)
Non-Inverting Frequency Response at VS = 5V
G=1
Rf = 0
G=2
R f = 5kΩ
R f = 5kΩ
G=5
R f = 5kΩ
0.01
0.1
1
V o = 0.2Vpp
R f = 5kΩ
R f = 5kΩ
R f = 5kΩ
R f = 5kΩ
0.01
10
0.1
Frequency (MHz)
G=1
Rf = 0
G=2
R f = 5kΩ
R f = 5kΩ
G=5
R f = 5kΩ
0.01
0.1
1
R f = 5kΩ
G = -2
G = -5
0.01
10
CL
R s = 0Ω
CL
R s = 0Ω
CL
R s = 0Ω
+
-
Rs
5kΩ
CL
1
10
Frequency Response vs RL
Magnitude (1dB/div)
Magnitude (1dB/div)
CL
R s = 100Ω
0.1
Frequency (MHz)
Frequency Response vs CL
V o = 0.05V
G = -1
G = -10
Frequency (MHz)
10
Inverting Frequency Response at VS = 2.7V
Normalized Magnitude (1dB/div)
Normalized Magnitude (1dB/div)
Non-Inverting Frequency Response at VS = 2.7V
V o = 0.2Vpp
1
Frequency (MHz)
RL
RL = 1kΩ
RL = 10kΩ
RL = 200Ω
RL = 50Ω
5kΩ
0.01
0.1
1
10
0.01
© 2009 - 2014 Exar Corporation
0.1
1
10
Frequency (MHz)
Frequency (MHz)
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Rev 1D
CLC2011, CLC4011
Typical Performance Characteristics
TA = 25°C, VS = +2.7V, Rf = Rg = 5kΩ, RL = 10kΩ to VS/2; G = 2; unless otherwise noted.
Frequency Response vs. VOUT
Open Loop Gain & Phase vs. Frequency
140
V s = 5V
Open Loop Gain (dB)
V o = 4Vpp
V o = 2Vpp
No load
100
80
60
0
40
-45
20
-90
0
R L = 10kΩ
-135
No load
-20
0.01
0.1
1
-180
10 0
10
Open Loop Phase (deg)
V o = 1Vpp
Magnitude (1dB/div)
V s = 5V
120 R L = 10kΩ
10 1
10 2
10 3
10 4
10 5
10 6
10 7
10 8
Frequency (Hz)
Frequency (MHz)
-20
-20
-30
-30
-40
-40
Distortion (dBc)
Distortion (dBc)
2nd Harmonic Distortion vs VOUT
3rd Harmonic Distortion vs VOUT
-50
50kHz
-60
100kHz
50kHz
-70
-50
100kHz
-60
20kHz
-70
10kHz
10kHz, 20kHz
-80
50kHz
-80
10kHz
-90
-90
0.5
1
1.5
2
0.5
2.5
Output Amplitude (Vpp)
2nd & 3rd Harmonic Distortion at VS = 2.7V
-20
-40
2
2.5
55
50
R L = 200Ω
R L = 1kΩ
-50
45
nV/√Hz
Distortion (dBc)
R L = 200Ω
1.5
Input Voltage Noise
V o = 1Vpp
-30
1
Output Amplitude (Vpp)
R L = 10kΩ
-60
-70
40
35
30
25
20
15
10
-80
R L = 10kΩ
-90
0
20
40
60
R L = 1kΩ
80
5
0
100
0.1k
Frequency (kHz)
© 2009 - 2014 Exar Corporation
1k
10k
100k
1M
Frequency (Hz)
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Rev 1D
CLC2011, CLC4011
Typical Performance Characteristics
TA = 25°C, VS = +2.7V, Rf = Rg = 5kΩ, RL = 10kΩ to VS/2; G = 2; unless otherwise noted.
PSRR
0
0
-10
-10
-20
-20
-30
-30
PSRR (dB)
CMRR (dB)
CMRR
-40
-50
-60
-40
-50
-60
-70
-70
-80
-80
-90
-90
10
100
1000
10000
100000
10
Frequency (Hz)
100
1000
10000
100000
Frequency (Hz)
Output Swing vs. Load
Pulse Response vs. Common Mode Voltage
R L = 10kΩ
Output Voltage (0.5V/div)
Output Voltage (0.27V/div)
1.35
R L = 1kΩ
0
R L = 75Ω
R L = 100Ω
R L = 200Ω
R L = 75/100Ω
1.2V offset
0.6V offset
No offset
-0.6V offset
-1.2V offset
-1.35
-2.0
0
2.0
Time (1µs/div)
Input Voltage (0.4V/div)
Crosstalk vs. Frequency
© 2009 - 2014 Exar Corporation
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exar.com/CLC2011
Rev 1D
CLC2011, CLC4011
Application Information
+Vs
General Description
The CLCx011 family of amplifiers are single supply, general
purpose, voltage-feedback amplifiers. They are fabricated
on a complimentary bipolar process, feature a rail-to-rail
input and output, and are unity gain stable.
Input
6.8μF
0.1μF
+
Output
RL
0.1μF
Basic Operation
Figures 1, 2, and 3 illustrate typical circuit configurations for
non-inverting, inverting, and unity gain topologies for dual
supply applications. They show the recommended bypass
capacitor values and overall closed loop gain equations.
Figure 4 shows the typical non-inverting gain circuit for
single supply applications.
+Vs
Input
6.8μF
-Vs
Figure 3: Unity Gain Circuit
+Vs
6.8μF
6.8μF
+
In
0.1μF
+
+
0.1μF
Out
Output
-
-
RL
0.1μF
Rg
6.8μF
-Vs
G=1
Rf
Rf
Rg
G = 1 + (Rf/Rg)
Figure 4: Single Supply Non-Inverting Gain Circuit
Figure 1: Typical Non-Inverting Gain Circuit
+Vs
R1
Input
Rg
Power Dissipation
6.8μF
0.1μF
+
Output
RL
0.1μF
6.8μF
-Vs
Rf
G = - (Rf/Rg)
For optimum input offset
voltage set R1 = Rf || Rg
Figure 2: Typical Inverting Gain Circuit
© 2009 - 2014 Exar Corporation
Power dissipation should not be a factor when operating
under the stated 10kΩ load condition. However, applications
with low impedance, DC coupled loads should be analyzed
to ensure that maximum allowed junction temperature is
not exceeded. Guidelines listed below can be used to verify
that the particular application will not cause the device to
operate beyond it’s intended operating range.
Maximum power levels are set by the absolute maximum
junction rating of 150°C. To calculate the junction
temperature, the package thermal resistance value ThetaJA
(θJA) is used along with the total die power dissipation.
TJunction = TAmbient + (θJA × PD)
Where TAmbient is the temperature of the working
environment.
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Rev 1D
CLC2011, CLC4011
In order to determine PD, the power dissipated in the load
needs to be subtracted from the total power delivered by the
supplies.
Maximum Power Dissipation (W)
2.5
PD = Psupply - Pload
Supply power is calculated by the standard power equation.
Psupply = Vsupply × IRMSsupply
Vsupply = VS+ - VS-
TSSOP-14
2
SOIC-14
1.5
SOIC-8
1
0.5
MSOP-8
Power delivered to a purely resistive load is:
0
-40
Pload = ((Vload)RMS2)/Rloadeff
-20
0
20
40
60
80
100
120
Ambient Temperature (°C)
Figure 5. Maximum Power Derating
The effective load resistor (Rloadeff) will need to include
the effect of the feedback network. For instance, Rloadeff in
Figure 3 would be calculated as:
RL || (Rf + Rg)
These measurements are basic and are relatively easy to
perform with standard lab equipment. For design purposes
however, prior knowledge of actual signal levels and load
impedance is needed to determine the dissipated power.
Here, PD can be found from
PD = PQuiescent + PDynamic - Pload
Input Common Mode Voltage
The common mode input range extends to 250mV below
ground and to 250mV above Vs, in single supply operation.
Exceeding these values will not cause phase reversal.
However, if the input voltage exceeds the rails by more
than 0.5V, the input ESD devices will begin to conduct. The
output will stay at the rail during this overdrive condition. If
the absolute maximum input voltage (700mV beyond either
rail) is exceeded, externally limit the input current to ±5mA
as shown in Figure 6.
10k
Input
Output
Quiescent power can be derived from the specified IS values
along with known supply voltage, Vsupply. Load power can
be calculated as above with the desired signal amplitudes
using:
-
Figure 6. Circuit for Input Current Protection
(Vload)RMS = Vpeak / √2
( Iload)RMS = ( Vload)RMS / Rloadeff
The dynamic power is focused primarily within the output
stage driving the load. This value can be calculated as:
PDynamic = (VS+ - Vload)RMS × ( Iload)RMS
Driving Capacitive Loads
Increased phase delay at the output due to capacitive loading
can cause ringing, peaking in the frequency response, and
possible unstable behavior. Use a series resistance, RS,
between the amplifier and the load to help improve stability
and settling performance. Refer to Figure 7.
Assuming the load is referenced in the middle of the power
rails or Vsupply/2.
Input
+
Rs
-
The CLC2011 is short circuit protected. However, this may
not guarantee that the maximum junction temperature
(+150°C) is not exceeded under all conditions. Figure 5
shows the maximum safe power dissipation in the package
vs. the ambient temperature for the packages available.
© 2009 - 2014 Exar Corporation
+
Rf
Output
CL
RL
Rg
Figure 7. Addition of RS for Driving Capacitive Loads
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Rev 1D
CLC2011, CLC4011
Table 1 provides the recommended RS for various capacitive
loads. The recommended RS values result in approximately
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