SP232AEN-L/TR

SP232A Enhanced RS-232 Line Drivers/Receivers FEATURES • Operates from a Single +5V Power Supply • Meets all RS-232F and ITU V.28 Specifications • Operates with 0.1μF Ceramic Capacitors • High Data rate - 120kbps under load • Low power CMOS Operation • +/-2kV Human Body Model ESD Protection • Lead Free packaging available DESCRIPTION The SP232A is a line driver and receiver pair that meets the specifications of RS-232 and V.28 serial protocols. This device is pin-to-pin compatible with popular industry standard pinouts. The SP232A offers 120kbps data rate under load, small ceramic type 0.1μF charge pump capacitors and overall ruggedness for comercial applications. The SP232A features Exar's BiCMOS design allowing for low power operation without sacrificing performance. This device is avaialble in plastic DIP, SOICW and nSOIC packages operating over the commercial and industrial temperature ranges. SOICW and nSOIC versions available, PDIP versions are obsolete. SP232A_101_032420 1 These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below are not implied. Exposure to absolute maximum ratings conditions for extended periods of time may affect reliability. Supply Voltage (VCC)...............................................+ 6V V+........................................................................... (Vcc-0.3V) to +11.0V V- .............................................................................-11.0V Input Voltages Tin.....................................................-0.3V to (Vcc + 0.3V) Rin............................................................................+/-15V Output Voltages Tout...............................................(V+, +0.3V) to (V-, -0.3V Rout...................................................-0.3V to (Vcc + 0.3V) ABSOLUTE MAXIMUM RATINGS Short Circuit duration Tout.....................................................Continuous Package Power Dissipation: Plastic DIP...............................................375mW (derate 7mW/°C above +70°C) Small Outline...........................................375mW (derate 7mW/°C above +70°C) Storage Temperature..................-65°C to +150°C Lead Temperature (soldering, 10s).......... +300°C ELECTRICAL CHARACTERISTICS Vcc=5V ±10%, 0.1μF charge pump capacitors, Tmin to Tmax, unless otherwise noted, Typical values are Vcc=5V and Ta=25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 0.8 Volts TTL INPUT Logic Threshold LOW TIN Logic Threshold HIGH TIN Logic Pull-Up Current TIN = 0V 2.0 Volts 15 200 μA TTL OUTPUT Output Voltge LOW Iout = 3.2 mA: Vcc = +5V Output Voltage HIGH Iout = -1.0 mA 3.5 0.4 Output Voltage Swing All Transmitter outputs loaded with 3k ohms to GND +/-5.0 Output Resistance Vcc = 0V, Vout = +/-2V 300 Output Short Circuit Current Infinite Duration Maximum Data Rate CL = 2500pF, RL = 3kΩ Volts Volts RS-232 OUTPUT 120 +/-6.5V Volts Ohms +/-18 mA 240 kbps RS-232 INPUT Voltage Range -15 Voltage Threshold LOW Vcc = 5V, Ta=25°C Voltage Threshold HIGH Vcc = 5V, Ta=25°C Hysteresis Vcc = 5V, Ta=25°C Resistance Ta=25°C, -15V ≤ Vin ≤ +15V 0.8 +15 1.2 Volts Volts 1.7 2.4 Volts 0.2 0.5 1.0 Volts 3 5 7 kΩ SP232A_101_032420 2 ELECTRICAL CHARACTERISTICS Vcc=5V ±10%, 0.1μF charge pump capacitors, Tmin to Tmax, unless otherwise noted, Typical values are Vcc=5V and Ta=25°C DYNAMIC CHARACTERISTICS Driver Propagation Delay TTL to RS_232; CL = 50pF 1.5 3.0 μs Receiver Propagation Delay RS-232 to TTL, 0.1 1.0 μs Instantaneous Slew Rate CL = 10pF, RL = 3-7kΩ 30 V/ μs Transition Region Slew Rate CL = 2500pF, RL = 3kΩ; Measured from +3V to -3V or -3V to +3V 10 Vcc Power Supply Current No Load, Vcc = 5V, Ta=25°C 1.5 Vcc Power Supply Current, Loaded All Transmitters RL = 3kΩ, Ta=25°C 11 V/ μs POWER REQUIREMENTS 5 mA mA PIN ASSIGNMENTS Pin Number Pin Name Pin Function 1 C1+ Positive terminal of the voltage doubler charge pump capacitor 2 V+ +6.5V generated by the charge pump 3 C1- Negative terminal of the voltage doubler charge pump capacitor 4 C2+ Positive terminal of the inverting charge pump capacitor 5 C2- Negative terminal of the inverting charge pump capacitor 6 7 VT2OUT 8 R2IN 9 10 11 12 13 14 15 16 R2OUT -6.7V generated by the charge pump RS-232 driver output RS-232 receiver input TTL/CMOS receiver output T2IN TTL/CMOS driver input T1IN TTL/CMOS driver input R1OUT TTL/CMOS receiver output R1IN RS-232 receiver input T1OUT RS-232 driver output GND Ground Vcc 5V supply voltage SP232A_101_032420 3 DESCRIPTION DETAILED DESCRIPTION The SP232A transceiver is a two driver and two receiver device that meets the EIA/TIA- 232 and V.28 serial communication protocol. The device is pin-to-pin compatible with popular industry standard pinouts. The SP232A offers 120kbps data rate, 10V/μs slew rate and a regulated charge pump that operates from a single 5V supply. The proprietary on-board charge pump generates a regulated output of +/-6.5V for RS232 compliant voltage levels. Charge pump The charge pump is a patented design and uses a unique approach compared to older less efficient designs. The charge pump requires 4 external capacitors and uses a four phase voltage shifting technique. The internal power supply consists of a regulated dual charge pump that provides output voltages of +/-6.5V. This is important to maintain compliant RS-232 levels regardless of power supply fluctuations. The charge pump operates in a discontinous mode using an internal oscillator. If the voltages are less than a magnitude of 6.5V, the charge pump is enabled. If the output voltage exceed a magnitude of 6.5V then the charge pump is disabled. The internal oscillator controls the four phases of the voltage shifting. A description of each phase follows: Theory Of Operation The SP232A is made up of three basic circuit blocks: 1. Driver, 2. Receiver, and 3. charge pump. Drivers The drivers are inverting level transmitters that convert TTL or CMOS logic levels to EIA/TIA232 levels with an inverted sense relative to the input logic levels. Typically, the RS-232 output voltage swing is +/-6.5V with no load and +/5.0V minimum when fully loaded. The driver outputs are protected against infinite short-circuits to ground without degradation in reliability. Phase 1 Vss charge store and double: The positive terminals of capacitors C1 and C2 are charged from Vcc with their negative terminals initially connected to ground. C1+ is then connected to ground and the stored charge from C1- is superimposed onto C2-. Since C2+ is still connected to Vcc the voltage potential across C2 is now 2 x Vcc. The drivers can guarantee output data rates of 120Kbps under worst case loading of 3k ohms and 2500pF. Phase 2 Vss transfer and invert: Phase two connects the negative terminal of C2 to the Vss storage capacitor and the positive terminal of C2 to ground. This transfers the doubled and inverted (V-) voltage onto C4. Meanwhile, capacitor C1 is charged from Vcc in order to prepare it for its next phase. The driver output Slew Rate is internally limited to 30V/μs in order to meet the EIA standards (EIA-232F). Additionally, the driver output LOW to HIGH transition meet the monotonicity output requirements of the standard. Receivers The receivers convert EIA/TIA-232 signal levels to TTL or CMOS logic output levels. Since the input is usually from a transmission line, where long cable length and system interference can degrade the signal, the receiver inputs have a typical hysteresis margin of 500mV. This ensures that the receiver is virtually immune to noisy transmission lines. Should a input be left unconnected, an internal 5Kohm pull-down resistor to ground will commit the output of the receiver to a logic HIGH state. The input voltage range for the SP232A Receiver is +/-15V. Phase 3 Vdd charge store and double: Phase three is identical to the first phase. The positive terminals of C1 and C2 are charged from Vcc with their negative terminals initially connected to ground. C1+ is then connected to ground and the stored charge from C1- is superimposed onto C2-. Since C2+ is still connected to Vcc the voltage potential across capacitor C2 is now 2 x Vcc. SP232A_101_032420 4 DESCRIPTION Phase 4 Vdd transfer. The fourth phase connects the negative terminal of C2 to ground and the positive terminal of C2 to the Vdd storage capacitor . This transfers the doubled (V+) voltage onto C3. Meanwhile, capacitor C1 is charged from Vcc to prepare it for its next phase. The clock rate of the charge pump typically operates greater than 70kHz allowing the pump to operate efficiently with small 0.1uF capacitors. Efficient operation depends on rapid charging and discharging of C1 and C2. Therefore, the capacitors should be mounted as close as possible to the IC and have a low ESR (equivalent series resistance). Inexpensive, surface mount ceramic capacitors are ideal for use on charge pump. If polarized capacitors are used the positive and negative terminals should be connected as shown on the typical operating circuit. A diagram of the 4 individual phases is shown in Figure 1. Under lightly loaded conditions, the intelligent pump oscillator maximizes efficiency by running only as needed to maintain V+ and V- voltage levels. Since interface transceivers spend most of their time at idle, this power-efficient innovation can greatly reduce total power consumption. This improvement is made possible by the independent phase sequences of the Exar charge pump design. + V CC - Phase 2 – Vss transfer from C2 to C4. Meanwhile C1 is charged to Vcc + + V CC - C Phases 1 and 3: Store/Double. Double charge from C1 onto C2. C2 is now charged to -2xVcc + 1 C e- + 2 V+ e- e- C 3 + C Vss 4 + C + 1 C + 2 ee- V+ C V- + Patented 5,306,954 3 C + V CC - 4 Phase 4 VDD transfer from C2 to C3. Meanwhile C1 is charged to Vcc V e+ C + 1 e- C DD + 2 e+ + V+ V- C 3 + C 4 Figure 1. Charge pump phases SP232A_101_032420 5 TYPICAL PERFORMANCE CHARACTERISTICS Figure 5, Charge pump outputs at start up (1 = Vcc, 2 = V+, 3 = V-). Figure 2, Charge pump waveforms with no load (1 = C1+, 2 = C2+, 3 = V+, 4 = V-). Figure 3, Charge pump waveforms when fully loaded with 3k ohms (1 = C1+, 2 = C2+, 3 = V+, 4 = V-). Figure 6, Typical Application circuit Figure 4, Loopback results at 60kHZ and 2500pF load (1 = TXin, 2 = TXout/RXin, 3 = RXout). SP232A_101_032420 6 SP232A_101_032420 7 16 pin PDIP versions are obsolete. SP232A_101_032420 8 SP232A_101_032420 9 ORDERING INFORMATION(1) Part Number Temperature Range Package Packaging Method Lead-Free(2) SP232ACN-L 00C to +700C SP232ACN-L/TR 00C to +700C 16 pin nSOIC Tube Yes 16 pin nSOIC Tape and Reel Yes SP232ACT-L/TR 0 C to +70 C 16 pin WSOIC Tape and Reel Yes SP232AEN-L -40 C to +85 C 16 pin nSOIC Tube Yes SP232AEN-L/TR -40 C to +85 C 16 pin nSOIC Tape and Reel Yes 0 0 0 0 0 0 NOTES: 1. Refer to www.maxlinear.com/SP232A for most up-to-date Ordering Information. 2. Visit www.maxlinear.com for additional information on Environmental Rating. 3. 16 pin PDIP versions are obsolete. REVISION HISTORY Date Revision Description 1-31-07 Jan 31-07 5-13-08 100 Generate individual SP232A datasheet using Exar format, update elect. spec. (TXout) and theory of operation to reflect new Charge Pump design as a result of 5 um to 2um conversion, remove EOL devices from ordering info and update new performance figures. 3-24-20 101 Update to MaxLinear logo. Update Ordering Information. Add revision history. Original SP232A/233A/310A/312A data sheet MaxLinear, Inc. 5966 La Place Court, Suite 100 Carlsbad, CA 92008 760.692.0711 p. 760.444.8598 f. www.maxlinear.com The content of this document is furnished for informational use only, is subject to change without notice, and should not be construed as a commitment by MaxLinear, Inc. MaxLinear, Inc. assumes no responsibility or liability for any errors or inaccuracies that may appear in the informational content contained in this guide. Complying with all applicable copyright laws is the responsibility of the user. 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