SP233ACT-L

SP233A Enhanced RS-232 Line Drivers/Receivers FEATURES • Operates from a Single +5V Power Supply • Meets all RS-232F and ITU V.28 Specifications • Operates with 0.1μF Ceramic Capacitors • No External Capacitors required (SP233A) • Low Power Shutdown (SP310A, SP312A) • High Data Rate - 120kbps under load • Low power CMOS Operation • +/-2kV Human Body Model ESD Protection • Lead Free packaging available DESCRIPTION The SP233A / SP310A / SP312A devices are a family of line driver and receiver pairs that meets the specifications of RS-232 and V.28 serial protocols. The devices are pin-to-pin compatible with popular industry standard pinouts. The SP233A / SP310A / SP312A offer 120kbps data rate under load, small ceramic type 0.1μF charge pump capacitors and overall ruggedness for comercial applications. Features include Exar's BiCMOS design allowing for low power operation without sacrificing performance. These devices are available in plastic DIP and SOIC Wide packages operating over the commercial and industrial temperature ranges. SELECTION TABLE Model Number of RS-232 Drivers Receivers No. of RX active in Shutdown No. of External 0.1μF Capacitors Shutdown WakeUp TTL Tri-State SP233A 2 2 N/A 0 No No No SP310A 2 2 0 4 Yes No Yes SP312A 2 2 2 4 Yes Yes Yes SP310A and SP312A are obsolete SP233A 102_032020 1 These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below are not implied. Exposure to absolute maximum ratings conditions for extended periods of time may affect reliability. Supply Voltage (VCC)....................................................+ 6V V+........................................................................... (Vcc-0.3V) to +11.0V V- .............................................................................-11.0V Input Voltages Tin.....................................................-0.3V to (Vcc + 0.3V) Rin............................................................................+/-30V Output Voltages Tout...............................................(V+, +0.3V) to (V-, -0.3V Rout...................................................-0.3V to (Vcc + 0.3V) ABSOLUTE MAXIMUM RATINGS Short Circuit duration Tout.....................................................Continuous Package Power Dissipation: Plastic DIP...............................................375mW (derate 7mW/°C above +70°C) Small Outline...........................................375mW (derate 7mW/°C above +70°C) Storage Temperature..................-65°C to +150°C Lead Temperature (soldering, 10s).......... +300°C ELECTRICAL CHARACTERISTICS Vcc=5V ±10%, 0.1μF charge pump capacitors, Tmin to Tmax, unless otherwise noted, Typical values are Vcc=5V and Ta=25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 0.8 Volts TTL INPUT Logic Threshold LOW TIN, EN, SD, ON/OFF Logic Threshold HIGH TIN, EN, SD, ON/OFF Logic Pull-Up Current TIN = 0V 2.0 Volts 15 200 μA TTL OUTPUT Output Voltge LOW Iout = 3.2mA: Vcc = +5V Output Voltage HIGH Iout = -1.0mA Leakage Current; Ta=25°C EN = Vcc, 0V ≤ Vout ≤ Vcc SP310A and SP312A only 0.4 3.5 Volts Volts 0.05 +/-10 μA RS-232 OUTPUT Output Voltage Swing All Transmitter outputs loaded with 3k ohms to GND +/-5.0 Output Resistance Vcc = 0V, Vout = +/-2V 300 Output Short Circuit Current Infinite Duration Maximum Data Rate CL = 2500pF, RL = 3kΩ 120 +/-9V Volts Ohms +/-18 mA 240 kbps RS-232 INPUT Voltage Range -25 Voltage Threshold LOW Vcc = 5V, Ta=25°C Voltage Threshold HIGH Vcc = 5V, Ta=25°C Hysteresis Vcc = 5V, Ta=25°C Resistance Ta=25°C, -25V ≤ Vin ≤ +25V 0.8 +25 1.2 Volts Volts 1.7 2.4 Volts 0.2 0.5 1.0 Volts 3 5 7 kΩ SP233A_102_032020 2 ELECTRICAL CHARACTERISTICS Vcc=5V ±10%, 0.1μF charge pump capacitors, Tmin to Tmax, unless otherwise noted, Typical values are Vcc=5V and Ta=25°C Parameter TEST CONDITIONS MIN TYP MAX Unit μs DYNAMIC CHARACTERISTICS Driver Propagation Delay TTL to RS_232; CL = 50pF 1.5 3.0 Receiver Propagation Delay RS-232 to TTL, 0.1 1.0 μs Instantaneous Slew Rate CL = 10pF, RL = 3-7kΩ 30 V/ μs Transition Region Slew Rate CL = 2500pF, RL = 3kΩ; Measured from +3V to -3V or -3V to +3V 10 V/ μs Output Enable Time SP310A and SP312A only 400 ns Output Disable Time SP310A and SP312A only 250 ns Vcc Power Supply Current No Load, Vcc = 5V, Ta=25°C 10 Vcc Power Supply Current, Loaded All Transmitters RL = 3kΩ, Ta=25°C 25 Shutdown Supply Current SP310A and SP312A only Vcc = 5V, Ta=25°C 1 POWER REQUIREMENTS 15 mA mA 10 μA PIN ASSIGNMENTS 20 pin PDIP 20 pin PDIP version is obsolete 20 pin WSOIC 18 pin WSOIC 18 pin WSOIC SP310A and SP312A are obsolete 3 SP233A 102_032020 DESCRIPTION DETAILED DESCRIPTION The SP233A, SP310A and SP312A devices are a family of line driver and receiver pairs that meet the EIA/TIA-232 and V.28 serial communication protocols. These devices are pin-to-pin compatible with popular industry standards. The SP233A, SP310A and SP312A devices offer a 120kbps data rate, 10V/μs slew rate and an onboard charge pump that operates from a single 5V supply using 0.1μF ceramic capacitors. The ESD tolerance has been improved on these devices to +/-2kV Human Body Model. Receivers The receivers convert EIA/TIA-232 signal levels to TTL or CMOS logic output levels. Since the input is usually from a transmission line, where long cable length and system interference can degrade the signal, the inputs have a typical hysteresis margin of 500mV. This ensures that the receiver is virtually immune to noisy transmission lines. Should an input be left unconnected, an internal 5kohm pull-down resistor to ground will commit the output of the receiver to a HIGH state. The SP233A device provides internal charge pump capacitors. The SP310A provides an ON/ OFF input that simultaneously disables the internal charge pump circuit and puts all transmitter and receiver outputs into a high impedance state. The SP312A is identical to the SP310 but with seperate tri-state and shutdown inputs Charge pump The charge pump is a patented design and uses a unique approach compared to older less efficiant designs. The charge pump requires 4 external capacitors and uses a four phase voltage shifting technique. The internal power supply consists of a dual charge pump that provides a driver output voltage swing of +/-9V. The internal oscillator controls the four phases of the voltage shifting. A description of each phase follows: Theory Of Operation The SP233A, SP310A and SP312A devices are made up of three basic circuit blocks: 1. Drivers, 2. Receivers, and 3. charge pump. Phase 1 Vss charge store and double: The positive terminals of capacitors C1 and C2 are charged from Vcc with their negative terminals initially connected to ground. C1+ is then connected to ground and the stored charge from C1- is superimposed onto C2-. Since C2+ is still connected to Vcc the voltage potential across C2 is now 2 x Vcc. Drivers The drivers are inverting level transmitters that convert TTL or CMOS logic levels to EIA/TIA232 levels with an inverted sense relative to the input logic levels. Typically, the driver output voltage swing is +/-9V. Even under worst case loading conditions of 3k ohms and 2500pF, the driver output is guaranteed to be +/-5.0V minimum, thus satisfying the RS-232 specification. The driver outputs are protected against infinite short-circuits to ground without degradation in reliability. Phase 2 Vss transfer and invert: Phase two connects the negative terminal of C2 to the Vss storage capacitor and the positive terminal of C2 to ground. This transfers the doubled and inverted (V-) voltage onto C4. Meanwhile, capacitor C1 is charged from Vcc to prepare it for its next phase. The drivers can guarantee output data rates of 120kbps under worst case loading of 3k ohms and 2500pF. The Slew rate of the driver output is internally limited to 30V/ μs in order to meet the EIA standards (EIA-232F). Additionally, the driver outputs LOW to HIGH transition meets the montonic output requirements of the standard. Phase 3 Vdd charge store and double: Phase three is identical to the first phase. The positive terminals of C1 and C2 are charged from Vcc with their negative terminals initially connected to ground. C1+ is then connected to ground and the stored charge from C1- is superimposed onto C2-. Since C2+ is still connected to Vcc the voltage potential across capacitor C2 is now 2 x Vcc. SP233A_102_032020 4 DESCRIPTION Phase 4 Vdd transfer: The fourth phase connects the negative terminal of C2 to ground and the positive terminal of C2 to the Vdd storage capacitor. This transfers the doubled (V+) voltage onto C3. Meanwhile, capacitor C1 is charged from Vcc to prepare it for its next phase. After the ring indicator has propagated through the SP312A receiver, it can be used to trigger the power management circuitry of the computer to power up the microprocessor, and bring the SD pin of the SP312A to a logic high, taking it out of the shutdown mode. The receiver propagation delay is typically 1us. The enable time for V+ and V- is typically 2ms. After V+ and V- have settled to their final values, a signal can be sent back to the modem on the data terminal ready (DTR) pin signifying that the computer is ready to accept the transmit data. The clock rate for the charge pump typically operates at greater than 15kHz allowing the pump to run efficiently with small 0.1uF capacitors. Efficient operation depends on rapid charging and discharging of C1 and C2, therefore capacitors should be mounted as close as possible to the IC and have low ESR (equivalent series resistance). Inexpensive surface mount, ceramic capacitors are ideal for using on charge pump. If polarized capacitors are used the positive and negative terminals should be connected as shown in the typical operating circuit. A diagram of the individual phases are shown in Figure 1. Shutdown (SD) and Enable (EN) features for the SP310A and SP312A Both the SP310A and SP312A have a shutdown / standby mode to conserve power in batterypowered applications. To activate the shutdown mode, which stops the operation of the charge pump, a logic "0" is applied to the appropriate control line. For the SP310A, this control line is the ON/OFF (pin 18) input. Activating the shutdown mode puts the SP310A transmitter and receiver ouptuts into a high impedance condition. For the SP312A, this control line is the SHUTDOWN (pin18) input; this also puts the transmitter outputs in a tri-state mode. The receiver outputs can be tri-stated seperately during normal operation or shutdown by applying a logic "1" on the EN line (pin 1). Power Receiver Up/Down outputs SD EN 0 0 Down Enabled 0 1 Down Tri-state 1 0 Up Enabled 1 1 Up Tri-state Table 1. Wake-up Function truth table Pin Strapping for the SP233ACT/ACP The SP233A packaged in a 20 pin SOICW package (SP233ACT) has a slightly different pinout than the SP233A in PDIP packaging (SP233ACP). To operate properly, the following pairs of pins must be externally wired together as noted in table 2: Pins Wired Together Two V- pins Wake-Up Feature for the SP312A The SP312A has a wake-up feature that keeps the receivers active when the device is placed into shutdown. Table 1 defines the truth table for the Wake-Up function. When only the receivers are activated, the SP312A typically draws less than 5uA supply current. In the case of when a modem is interfaced to a computer in power down mode, the Ring Indicator (RI) signal from the modem would be used to "wake-up" the computer, allowing it to accept data transmission. SOICW PDIP 10 & 17 12 & 17 Two C2+ pins 12 & 15 11 & 15 Two C- pins 10 & 16 11 & 16 No Connections for Pins 8, 13 and 14 Connect Pins 6 and 9 to GND Table 2. Pin Strapping table for SP233A SP233A 102_032020 5 + V CC - Phase 2 – Vss transfer from C2 to C4. Meanwhile C1 is charged to Vcc + + V CC - C Phases 1 and 3: Store/Double. Double charge from C1 onto C2. C2 is now charged to -2xVcc + 1 C e- + 2 V+ e- e- C 3 + C Vss 4 + C + 1 C + 2 ee- V+ C V- + Patented 5,306,954 3 C + V CC - 4 Phase 4 VDD transfer from C2 to C3. Meanwhile C1 is charged to Vcc V e+ C + 1 e- C DD + 2 e+ + V+ V- C 3 + C 4 Figure 1. Charge pump phases SP233A_102_032020 6 TYPICAL PERFORMANCE CHARACTERISTICS Figure 5, Charge pump outputs at start up (1 = Vcc, 2 = V+, 3 = V-). Figure 2, SP233A Charge pump waveformsno load (1 = C1+, 2 = C2+, 3 = V+, 4 = V-). Figure 3, SP233A Charge pump waveforms when fully loaded with 3Kohms (1 = C1+, 2 = C2+, 3 = V+, 4 = V-). Figure 4, Loopback results at 60KHZ and 2500pF load (1 = TXin, 2 = TXout/RXin, 3 = RXout). SP233A 102_032020 7 Figure 6, SP233ACP Typical Application circuit Figure 8, SP233ACT Typical Application circuit Figure 7, SP310A Typical Application circuit Figure 9, SP312A Typical Application circuit SP233A_102_032020 8 20 pin PDIP version is obsolete SP233A 102_032020 9 SP233A_102_032020 10 SP310A and SP312A WSOIC18 are obsolete SP233A 102_032020 11 ORDERING INFORMATION(1) Part number Temperature range Package Packaging Method Lead-Free(2) SP233ACT-L 0 to +700C SP233ACT-L/TR 0 to +700C 20 pin SOICW Tube Yes 20 pin SOICW Tape and Reel Yes SP233AET-L -40 to +85 C 20 pin SOICW Tube Yes SP233AET-L/TR -40 to +85 C 20 pin SOICW Tape and Reel Yes 0 0 NOTES: 1. Refer to www.maxlinear.com/SP233A for the most up-to-date Ordering Information. 2. Visit www.maxlinear.com for additional information on Environmental Rating. 3. SP310A, SP312A and 20 pin PDIP versions of SP233A are obsolete. REVISION HISTORY Date Revision Description 1-31-07 Rev B 5-13-08 100 Generate new SP233A/310A/312A Data sheet using Exar format. 6-03-11 101 Add Revision History table. Remove SP310ACP-L option per PDN 110510-01. 3-20-20 102 Update to MaxLinear logo. Update Ordering Information. Original SP232A/233A/310A/312A Sipex Data sheet MaxLinear, Inc. 5966 La Place Court, Suite 100 Carlsbad, CA 92008 760.692.0711 p. 760.444.8598 f. www.maxlinear.com The content of this document is furnished for informational use only, is subject to change without notice, and should not be construed as a commitment by MaxLinear, Inc. MaxLinear, Inc. assumes no responsibility or liability for any errors or inaccuracies that may appear in the informational content contained in this guide. Complying with all applicable copyright laws is the responsibility of the user. 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