SP3220EUEY-L/TR

SP3220E / SP3220EB / SP3220EU +3.0V to +5.5V RS-232 Driver/Receiver Pair FEATURES ■ Meets all EIA/TIA-232-F Standards from a +3.0V to +5.5V power supply • Interoperable with RS-232 and V.28 at +2.7V ■ Supports High Serial Data Rates: • 120kbps SP3220E • 250kbps SP3220EB • 1Mbps SP3220EU ■ 1µA Low Power Shutdown Mode ■ Footprint Compatible with MAX3221E, ISL3221 ■ 4 x 1.0µF External Charge Pump Capacitors ■ Improved ESD Specifications: +15kV Human Body Model +15kV IEC61000-4-2 Air Discharge +8kV IEC61000-4-2 Contact Discharge EN 1 16 SHDN C1+ 2 15 VCC V+ 3 14 GND C1- 4 C2+ 5 SP3220 E/EB/EU 13 T1OUT 12 No Connect 11 T1IN C2- 6 V- 7 10 No Connect R1IN 8 9 R1OUT Now Available in Lead Free Packaging DESCRIPTION The SP3220E devices are RS-232 driver/receiver solutions intended for portable or hand-held applications such as palmtop computers, instrumentation and consumer products. These devices incorporate a high-efficiency, charge-pump power supply that allows the SP3220E devices to deliver true RS-232 performance from a single power supply ranging from +3.0V to +5.0V. This charge pump requires only 0.1µF capacitors in 3.3V operation. The ESD tolerance of the these devices are over +/-15kV for both Human Body Model and IEC61000-4-2 Air discharge test methods. All devices have a low-power shutdown mode where the driver outputs and charge pumps are disabled. During shutdown, the supply current falls to less than 1µA. SELECTION TABLE MODEL Power Supplies RS-232 Drivers RS-232 Receivers External Components Shutdown Data Rate SP3220E +3.0V to +5.5V 1 1 4 Capacitors Yes 120kbps SP3220EB +3.0V to +5.5V 1 1 4 Capacitors Yes 250kbps SP3220EU +3.0V to +5.5V 1 1 4 Capacitors Yes 1Mbps SP3220E_EB_EU_103_031920 1 ABSOLUTE MAXIMUM RATINGS These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability and cause permanent damage to the device. Power Dissipation per package VCC.......................................................-0.3V to +6.0V V+ (NOTE 1).......................................-0.3V to +7.0V V- (NOTE 1)........................................+0.3V to -7.0V V+ + |V-| (NOTE 1)...........................................+13V ICC (DC VCC or GND current).........................+100mA 16-pin SSOP (derate 9.69mW/oC above +70oC)...............775mW 16-pin TSSOP (derate 10.5mW/oC above +70oC)..............840mW Input Voltages TxIN, EN, SHDN...........................-0.3V to Vcc + 0.3V RxIN...................................................................+25V Output Voltages TxOUT.............................................................+13.2V RxOUT, .......................................-0.3V to (VCC +0.3V) Short-Circuit Duration TxOUT....................................................Continuous Storage Temperature......................-65°C to +150°C NOTE 1: V+ and V- can have maximum magnitudes of 7V, but their absolute difference cannot exceed 13V. ELECTRICAL CHARACTERISTICS Unless otherwise noted, the following specifications apply for VCC = +3.0V to +5.5V with TAMB = TMIN to TMAX. Typical values apply at Vcc = +3.3V or +5.0V and TAMB = 25oC, C1 - C4 = 0.1µF. PARAMETER MIN. TYP. MAX. UNITS CONDITIONS Supply Current 0.3 1.0 mA no load, VCC = 3.3V, TAMB = 25oC, TxIN = GND or VCC Shutdown Supply Current 1.0 10 µA SHDN = GND, VCC = 3.3V, TAMB = 25oC, TxIN = Vcc or GND 0.8 V TxIN, EN, SHDN, Note 2 V Vcc = 3.3V, Note 2 DC CHARACTERISTICS LOGIC INPUTS AND RECEIVER OUTPUTS Input Logic Threshold LOW GND Input Logic Threshold HIGH 2.0 Input Logic Threshold HIGH 2.4 V Vcc = 5.0V, Note 2 Input Leakage Current +0.01 +1.0 µA TxIN, EN, SHDN, TAMB = +25oC, VIN = 0V to VCC Output Leakage Current +0.05 +10 µA Receivers disabled, VOUT = 0V to VCC 0.4 Output Voltage LOW Output Voltage HIGH V IOUT = 1.6mA VCC -0.6 VCC -0.1 V IOUT = -1.0mA +5.0 +5.4 V Driver output loaded with 3KΩ to GND, TAMB = +25oC DRIVER OUTPUTS Output Voltage Swing NOTE 2: Driver input hysteresis is typically 250mV. SP3220E_EB_EU_103_031920 2 ELECTRICAL CHARACTERISTICS Unless otherwise noted, the following specifications apply for VCC = +3.0V to +5.5V with TAMB = TMIN to TMAX, Typical values apply at VCC = +3.3V or +5.0V and TAMB = 25°C. PARAMETER MIN. TYP. MAX. UNITS +35 +60 mA +25 µA +15 V CONDITIONS DRIVER OUTPUTS (continued) Output Resistance 300 Output Short-Circuit Current Ω Output Leakage Current VCC = V+ = V- = 0V, TOUT=+2V VOUT = 0V VOUT = +12V, VCC = GND to 5.5V, Drivers disabled RECEIVER INPUTS Input Voltage Range -15 Input Threshold LOW 0.6 1.2 Input Threshold LOW 0.8 1.5 V Vcc = 3.3V V Vcc = 5.0V Input Threshold HIGH 1.5 2.4 V Vcc = 3.3V Input Threshold HIGH 1.8 2.4 V Vcc = 5.0V Input Hysteresis 0.3 Input Resistance 3 5 Data Rate SP3220E 120 235 Data Rate SP3220EB Data Rate SP3220EU V 7 kΩ TIMING CHARACTERISTICS kbps RL = 3KΩ, CL = 1000pF 250 kbps RL = 3KΩ, CL = 1000pF 1000 kbps RL = 3KΩ, CL = 250pF Receiver Propagation Delay, tPHL 0.15 µs Receiver input to Receiver output, CL = 150pF Receiver Propagation Delay, tPLH 0.15 µs Receiver input to Receiver output, CL = 150pF Receiver Output Enable Time 200 ns Receiver Output Disable Time 200 ns Driver Skew 100 ns | tPHL - tPLH |, TAMB = 25°C Receiver Skew 50 ns | tPHL - tPLH | Transition-Region Slew Rate Transition-Region Slew Rate 30 90 V/µs Vcc = 3.3V, RL = 3kΩ, TAMB = 25°C, measurements taken from -3.0V to +3.0V or +3.0V to -3.0V (SP3220E and SP3220EB) V/µs Vcc = 3.3V, RL = 3kΩ, TAMB = 25°C, measurements taken from -3.0V to +3.0V or +3.0V to -3.0V (SP3220EU) SP3220E_EB_EU_103_031920 3 TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise noted, the following performance characteristics apply for VCC = +3.3V, 250kbps data rate, all drivers loaded with 3kΩ, 0.1µF charge pump capacitors, and TAMB = +25°C. 6 30 T1 at Full Data Rate T2 at 1/16 Full Data Rate T1+T2 Loaded with 3k/CLoad 4 125Kbps 20 Transmitter Output Voltage (V) Icc (mA) 25 60Kbps 15 20Kbps 10 5 0 0 1000 2000 3000 4000 TxOUT+ 2 T1 at 250Kbps 0 -2 TxOUT- -4 -6 5000 0 1000 4 5000 10 Supply Current (mA) Transmitter Output Voltage (V) TxOUT+ 2 0 -2 -4 TxOUT- 2.7 3 3.5 4 Supply V oltage (V) 4.5 8 6 4 2 0 5 T1 Loaded with 3K // 1000pf @ 250Kbps 2.7 3 3.5 - Slew + Slew 20 Icc (mA) 10 5 500 1000 2000 3000 4000 5 1Mbps 30 15 0 4.5 Figure 4. Supply Current vs Supply Voltage for the SP3220EB. 40 25 4 Supply Voltage (V) Figure 3. Transmitter Output Voltage vs Supply Voltage for the SP3220EB. Slew rate (V/s) 4000 12 6 0 3000 Figure 2. Transmitter Output Voltage vs Load Capacitance for the SP3220EB. Figure 1. Icc vs Load Capacitance for the SP3220EB. -6 2000 Load Capacitance (pF) Load Capacitance (pF) Load Capacitance (pF) 500Kbps 20 10 0 5000 2Mbps 0 250 500 1000 2000 3000 4000 Load Capacitance (pF) Figure 6. Supply Current vs Supply Voltage for the SP3220EU. Figure 5. Slew Rate vs Load Capacitance for the SP3220EB. SP3220E_EB_EU_103_031920 4 TYPICAL PERFORMANCE CHARACTERISTICS: Continued Unless otherwise noted, the following performance characteristics apply for VCC = +3.3V, 250kbps data rate, all drivers loaded with 3kΩ, 0.1µF charge pump capacitors, and TAMB = +25°C. 6 6 2Mbps 1.5Mbps 1Mbps 2 0 -2 -4 -6 1.5Mbps 2Mbps 0 250 500 1000 2 0 -2 -4 1Mbps 1500 TxOUT+ 4 Transmitter Output Voltage (V) Transmitter Output V oltage (V) 4 -6 2000 Load Capacitance (pF) TxOUT- 2.5 2.7 3 3.5 4 Supply V oltage (V) 4.5 5 Figure 8. Transmitter Output Voltage vs Supply Voltage for the SP3220EU. Figure 7. Transmitter Output Voltage vs Load Capacitance for the SP3220EU. 16 Supply Current (mA) 14 12 10 8 6 4 2 0 T1 Loaded with 3K // 1000pf @1Mbps 2.7 3 3.5 4 4.5 5 Supply Voltage (V) Figure 9. Supply Current vs Supply Voltage for the SP3220EU. SP3220E_EB_EU_103_031920 5 PIN FUNCTION NAME FUNCTION PIN NUMBER EN Receiver Enable. Apply Logic LOW for normal operation. Apply logic HIGH to disable the receiver outputs (high-Z state) 1 C1+ Positive terminal of the voltage doubler charge-pump capacitor 2 V+ +5.5V output generated by the charge pump 3 C1- Negative terminal of the voltage doubler charge-pump capacitor 4 C2+ Positive terminal of the inverting charge-pump capacitor 5 C2- Negative terminal of the inverting charge-pump capacitor 6 -5.5V output generated by the charge pump 7 RS-232 receiver input 8 VR1IN R1OUT T1IN T1OUT GND VCC SHDN N.C. TTL/CMOS receiver output 9 TTL/CMOS driver input 11 RS-232 driver output. 13 Ground 14 +3.0V to +5.5V supply voltage 15 Shutdown Control Input. Drive HIGH for normal device operation. Drive LOW to shutdown the drivers (high-Z output) and the onboard power supply 16 No Connect 10, 12 Table 1. Device Pin Description SP3220E_EB_EU_103_031920 6 PINOUT EN 1 16 SHDN C1+ 2 15 VCC V+ 3 14 GND C1- 4 C2+ 5 C2- 6 V- 7 SP3220 E/EB/EU 13 T1OUT 12 No Connect 11 T1IN 10 No Connect R1IN 8 9 R1OUT Figure 10. Pinout Configurations for the SP3220E/EB/EU SP3220E_EB_EU_103_031920 7 TYPICAL OPERATING CIRCUITS VCC C5 C1 C2 + 0.1µF 2 C1+ + + 0.1µF LOGIC INPUTS LOGIC OUTPUTS V+ 3 *C3 4 C15 C2+ 0.1µF 15 VCC SP3220 E/EB/EU V- C4 + 0.1µF T1OUT 13 RS-232 OUTPUTS R1IN 8 RS-232 INPUTS 9 R1OUT 5kΩ SHDN 1 EN 0.1µF 7 6 C211 T1IN + 16 GND 14 *can be returned to either VCC or GND Figure 11. SP3220E/EB/EU Typical Operating Circuit SP3220E_EB_EU_103_031920 8 DESCRIPTION The SP3220E/EB/EU devices meet the EIA/TIA-232 and ITU-T V.28/V.24 communication protocols and can be implemented in battery-powered, portable, or hand-held applications such as notebook or palmtop computers. The SP3220E/EB/EU devices feature Exar's proprietary on-board charge pump circuitry that generates ±5.5V for RS232 voltage levels from a single +3.0V to +5.5V power supply. This series is ideal for +3.3V-only systems, mixed +3.3V to +5.5V systems, or +5.0V-only systems that require true RS-232 performance. The SP3220EB device has a driver that can operate at a data rate of 250kbps fully loaded. The SP3220EU can operate at 1000kbps; the SP3220E device can operate at a typical data rate of 235kbps when fully loaded. will meet EIA/TIA-562 levels of +/-3.7V with supply voltages as low as 2.7V. The SP3220EB driver can guarantee a data rate of 250kbps fully loaded with 3kΩ in parallel with 1000pF, ensuring compatibility with PC-to-PC communication software. The SP3220EU driver can guarantee a data rate of 1000kbps fully loaded with 3kΩ in parallel with 250pF. The slew rate of the SP3220E and SP3220EB outputs are internally limited to a maximum of 30V/µs in order to meet the EIA standards (EIA RS-232D 2.1.7, Paragraph 5). The transition of the loaded output from HIGH to LOW also meet the monotonicity requirements of the standard. The slew rate of the SP3220EU is not limited. This allows it to transmit at much faster data rates. The SP3220E/EB/EU is a 1-driver/1- receiver device ideal for portable or hand-held applications. The SP3220E/EB/EU features a 1µA shutdown mode that reduces power consumption and extends battery life in portable systems. Its receivers remain active in shutdown mode, allowing external devices such as modems to be monitored using only 1µA supply current. Figure 12 shows a loopback test circuit used to test the RS-232 Driver. Figure 13 shows the test results of the loopback circuit with the SP3220EB driver active at 250kbps with RS-232 load in parallel with a 1000pF capacitor. Figure 14 shows the test results where the SP3220EU driver was active at 1000kbps and loaded with an RS-232 receiver in parallel with 250pF capacitors. A solid RS-232 data transmission rate of 250kbps provides compatibility with many designs in personal computer peripherals and LAN applications. THEORY OF OPERATION The SP3220E/EB/EU series is made up of three basic circuit blocks: 1. Driver 2. Receiver 3. The Exar proprietary charge pump The SP3220E/EB/EU driver's output stage is turned off (tri-state) when the device is in shutdown mode. When the power is off, the SP3220E/EB/EU device permits the outputs to be driven up to +/-12V. The driver's inputs do not have pull-up resistors. Designers should connect unused inputs to Vcc or GND. Driver The driver is an inverting level transmitter that converts TTL or CMOS logic levels to +5.0V EIA/TIA-232 levels with an inverted sense relative to the input logic levels. Typically, the RS-232 output voltage swing is +5.5V with no load and at least +5V minimum fully loaded. The driver outputs are protected against infinite short-circuits to ground without degradation in reliability. Driver outputs In the shutdown mode, the supply current falls to less than 1µA, where SHDN = LOW. When the SP3220E/EB/EU device is shut down, the device's driver output is disabled SP3220E_EB_EU_103_031920 9 DESCRIPTION (tri-stated) and the charge pump is turned off with V+ pulled down to Vcc and V- pulled to GND. The time required to exit shutdown is typically 100ms. Connect SHDN to Vcc if the shutdown mode is not used. SHDN has no effect on RxOUT. Note that the driver is enabled only when the magnitude of V- exceeds approximately 3V. VCC C5 C1 + + 0.1µF 0.1µF VCC C1+ V+ C3 + 0.1µF C1C2 + C2+ 0.1µF SP3220 E/EB/EU VC4 C2LOGIC INPUTS LOGIC OUTPUTS + 0.1µF TxOUT TxIN Receiver The receiver converts EIA/TIA-232 levels to TTL or CMOS logic output levels. The receiver has an inverting high-impedance output. This receiver output (RxOUT) is at high-impedance when the enable control EN = HIGH. In the shutdown mode, the receiver can be active or inactive. EN has no effect on TxOUT. The truth table logic of the SP3220E/EB/EU driver and receiver outputs can be found in Table 2. RxIN RxOUT 5kΩ EN *SHDN VCC GND (SP3220EU 250pF) (SP3220E/EB 1000pF) Figure 12. SP3220E/EB/EU Driver Loopback Test Circuit SHDN EN TxOUT RxOUT 0 0 Tri-state Active 0 1 Tri-state Tri-state 1 0 Active Active 1 1 Active Tri-state Table 2. SP3220E/EB/EU Truth Table Logic for Shutdown and Enable Control Figure 13. SP3220EB Loopback Test results at 250kbps Since receiver input is usually from a transmission line where long cable lengths and system interference can degrade the signal, the inputs have a typical hysteresis margin of 300mV. This ensures that the receiver is virtually immune to noisy transmission lines. Should an input be left unconnected, an internal 5KΩ pull-down resistor to ground will commit the output of the receiver to a HIGH state. Figure 14. SP3220EU Loopback Test results at 1Mbps SP3220E_EB_EU_103_031920 10 DESCRIPTION Charge Pump The charge pump is an Exar-patended design (U.S. 5,306,954) and uses a unique approach compared to older less-efficient designs. The charge pump still requires four external capacitors, but uses a four-phase voltage shifting technique to attain symmetrical 5.5V power supplies. The internal power supply consists of a regulated dual charge pump that provides output voltages of +/-5.5V regardless of the input voltage (Vcc) over the +3.0V to +5.5V range. Simultaneous with the transfer of the voltage to C3, the positive side of capacitor C1 is switched to VCC and the negative side is connected to GND. In most circumstances, decoupling the power supply can be achieved adequately using a 0.1µF bypass capacitor at C5 (refer to figures 6 and 7). In applications that are sensitive to power-supply noise, decouple Vcc to ground with a capacitor of the same value as charge-pump capacitor C1. Physically connect bypass capacitor as close to the IC as possible. Phase 4 — VDD transfer — The fourth phase of the clock connects the negative terminal of C2 to GND, and transfers this positive generated voltage across C2 to C4, the VDD storage capacitor. This voltage is regulated to +5.5V. At this voltage, the internal oscillator is disabled. Simultaneous with the transfer of the voltage to C4, the positive side of capacitor C1 is switched to VCC and the negative side is connected to GND, allowing the charge pump cycle to begin again. The charge pump cycle will continue as long as the operational conditions for the internal oscillator are present. Phase 3 — VDD charge storage — The third phase of the clock is identical to the first phase — the charge transferred in C1 produces –VCC in the negative terminal of C1, which is applied to the negative side of capacitor C2. Since C2+ is at VCC, the voltage potential across C2 is 2 times VCC. The charge pump operates in a discontinuous mode using an internal oscillator. If the output voltages are less than a magnitude of 5.5V, the charge pump is enabled. If the output voltages exceed a magnitude of 5.5V, the charge pump is disabled. This oscillator controls the four phases of the voltage shifting. A description of each phase follows. Since both V+ and V– are separately generated from VCC, in a no–load condition V+ and V– will be symmetrical. Older charge pump approaches that generate V– from V+ will show a decrease in the magnitude of V– compared to V+ due to the inherent inefficiencies in the design. Phase 1 — VSS charge storage — During this phase of the clock cycle, the positive side of capacitors C1 and C2 are initially charged to VCC. Cl+ is then switched to GND and the charge in C1– is transferred to C2–. Since C2+ is connected to VCC, the voltage potential across capacitor C2 is now 2 times VCC. Phase 2 — VSS transfer — Phase two of the clock connects the negative terminal of C2 to the VSS storage capacitor and the positive terminal of C2 to GND. This transfers a negative generated voltage to C3. This generated voltage is regulated to a minimum voltage of -5.5V. SP3220E_EB_EU_103_031920 11 DESCRIPTION Voltage potential across any of the capacitors will never exceed 2 x VCC. Therefore capacitors with working voltages as low as 6.3V rating may be used with a 3.0V VCC supply. The reference terminal of the V+ capacitor may be connected either to VCC or ground, but if connected to ground a minimum 10V working voltage is required. Higher working voltages and/or capacitance values may be advised if operating at higher VCC or to provide greater stability as the capacitors age. Charge Pump Design Guidelines The charge pump operates with 0.1µF capacitors for 3.3V operation. For other supply voltages, see the table for required capacitor values. Do not use values smaller than those listed. Increasing the capacitor values (e.g., by doubling in value) reduces ripple on the transmitter outputs and may slightly reduce power consumption. C2, C3, and C4 may be increased without changing C1’s value. Minimum recommended charge pump capacitor value Input Voltage Vcc Charge pump capacitor value for SP3220E/EB/EU 3.0V to 3.6V C1 - C4 = 0.1µF 3.0V to 5.5V C1 - C4 = 0.22µF Under lightly loaded conditions the intelligent pump oscillator maximizes efficiency by running only as needed to maintain V+ and V-. Since interface transceivers often spend much of their time at idle this power-efficient innovation can greatly reduce total power consumption. This improvement is made possible by the independent phase sequence of the Exar charge-pump design. The charge pump oscillator typically operates at greater than 250kHz allowing the pump to run efficiently with small 0.1μF capacitors. Efficient operation depends on rapidly charging and discharging C1 and C2, therefore capacitors should be mounted close to the IC and have low ESR (equivalent series resistance). Low cost surface mount ceramic capacitors (such as are widely used for power-supply decoupling) are ideal for use on the charge pump. However the charge pumps are designed to be able to function properly with a wide range of capacitor styles and values. If polarized capacitors are used the positive and negative terminals should be connected as shown in the Typical Operating Circuit. SP3220E_EB_EU_103_031920 12 DESCRIPTION VCC = +5V C4 +5V C1 + + C2 – –5V – + – VDD Storage Capacitor – + VSS Storage Capacitor C3 –5V Figure 15. Charge Pump — Phase 1 VCC = +5V C4 + C1 C2 – + – + – – + VDD Storage Capacitor VSS Storage Capacitor C3 -5.5V Figure 16. Charge Pump — Phase 2 [ T ] +6V a) C2+ T GND 1 GND 2 b) C2-6V T Ch1 2.00V Ch2 2.00V M 1.00µs Ch1 5.48V Figure 17. Charge Pump Waveforms VCC = +5V C4 +5V C1 + – C2 –5V + + – – – VDD Storage Capacitor + VSS Storage Capacitor C3 –5V Figure 18. Charge Pump — Phase 3 VCC = +5V +5.5V C1 + – C2 C4 + + – – – + VDD Storage Capacitor VSS Storage Capacitor C3 Figure 19. Charge Pump — Phase 4 SP3220E_EB_EU_103_031920 13 DESCRIPTION ESD TOLERANCE The SP3220E/EB/EU device incorporates ruggedized ESD cells on all driver output and receiver input pins. The ESD structure is improved over our previous family for more rugged applications and environments sensitive to electro-static discharges and associated transients. The improved ESD tolerance is at least +15kV without damage nor latch-up. the system is required to withstand an amount of static electricity when ESD is applied to points and surfaces of the equipment that are accessible to personnel during normal usage. The transceiver IC receives most of the ESD current when the ESD source is applied to the connector pins. The test circuit for IEC61000-4-2 is shown on Figure 21. There are two methods within IEC61000-4-2, the Air Discharge method and the Contact Discharge method. There are different methods of ESD testing applied: With the Air Discharge Method, an ESD voltage is applied to the equipment under test (EUT) through air. This simulates an electrically charged person ready to connect a cable onto the rear of the system only to find an unpleasant zap just before the person touches the back panel. The high energy potential on the person discharges through an arcing path to the rear panel of the system before he or she even touches the system. This energy, whether discharged directly or through air, is predominantly a function of the discharge current rather than the discharge voltage. Variables with an air discharge such as approach speed of the object carrying the ESD potential to the system and humidity will tend to change the discharge current. For example, the rise time of the discharge current varies with the approach speed. a) MIL-STD-883, Method 3015.7 b) IEC61000-4-2 Air-Discharge c) IEC61000-4-2 Direct Contact The Human Body Model has been the generally accepted ESD testing method for semi-conductors. This method is also specified in MIL-STD-883, Method 3015.7 for ESD testing. The premise of this ESD test is to simulate the human body’s potential to store electro-static energy and discharge it to an integrated circuit. The simulation is performed by using a test model as shown in Figure 20. This method will test the IC’s capability to withstand an ESD transient during normal handling such as in manufacturing areas where the IC's tend to be handled frequently. The Contact Discharge Method applies the ESD current directly to the EUT. This method was devised to reduce the unpredictability of the ESD arc. The discharge current rise time is constant since the energy is directly transferred without the air-gap arc. In situations such as hand held systems, the ESD charge can be directly discharged to the The IEC-61000-4-2, formerly IEC801-2, is generally used for testing ESD on equipment and systems. For system manufacturers, they must guarantee a certain amount of ESD protection since the system itself is exposed to the outside environment and human presence. The premise with IEC61000-4-2 is that RS RC SW1 DC Power Source SW2 CS Figure 20. ESD Test Circuit for Human Body Model Device Under Test SP3220E_EB_EU_103_031920 14 DESCRIPTION Contact-Discharge Model RS RC RV SW1 SW2 Device Under Test CS DC Power Source R S and RV add up to 330Ω for IEC61000-4-2. Figure 21. ESD Test Circuit for IEC61000-4-2 equipment from a person already holding the equipment. The current is transferred on to the keypad or the serial port of the equipment directly and then travels through the PCB and finally to the IC. The higher CS value and lower RS value in the IEC61000-4-2 model are more stringent than the Human Body Model. The larger storage capacitor injects a higher voltage to the test point when SW2 is switched on. The lower current limiting resistor increases the current charge onto the test point. I→ The circuit models in Figures 20 and 21 represent the typical ESD testing circuit used for all three methods. The CS is initially charged with the DC power supply when the first switch (SW1) is on. Now that the capacitor is charged, the second switch (SW2) is on while SW1 switches off. The voltage stored in the capacitor is then applied through RS, the current limiting resistor, onto the device under test (DUT). In ESD tests, the SW2 switch is pulsed so that the device under test receives a duration of voltage. 30A 15A For the Human Body Model, the current limiting resistor (RS) and the source capacitor (CS) are 1.5kΩ an 100pF, respectively. For IEC-61000-4-2, the current limiting resistor (RS) and the source capacitor (CS) are 330Ω an 150pF, respectively. DEVICE PIN TESTED Driver Outputs Receiver Inputs 0A t = 0ns Figure 22. ESD Test Waveform for IEC61000-4-2 HUMAN BODY MODEL Air Discharge +15kV +15kV t = 30ns t→ +15kV +15kV IEC61000-4-2 Direct Contact Level +8kV +8kV 4 4 Table 3. Transceiver ESD Tolerance Levels SP3220E_EB_EU_103_031920 15 PACKAGE: 16 PIN SSOP SP3220E_EB_EU_103_031920 16 PACKAGE: 16 PIN TSSOP SP3220E_EB_EU_103_031920 17 ORDERING INFORMATION(1) Part Number Operating Temperature Range Package Package Method Lead-Free(2) SP3220EB SP3220EBCA-L/TR 0°C to 70°C SSOP16 Tape and Reel Yes SP3220EBCY-L 0°C to 70°C TSSOP16 Tube Yes SP3220EBCY-L/TR 0°C to 70°C TSSOP16 Tape and Reel Yes SP3220EBEA-L/TR -40°C to 85°C SSOP16 Tape and Reel Yes SP3220EBEY-L -40°C to 85°C TSSOP16 Tube Yes SP3220EBEY-L/TR -40°C to 85°C TSSOP16 Tape and Reel Yes SP3220ECA-L/TR 0°C to 70°C SSOP16 Tape and Reel Yes SP3220ECY-L 0°C to 70°C TSSOP16 Tube Yes SP3220ECY-L/TR 0°C to 70°C TSSOP16 Tape and Reel Yes SP3220EEA-L/TR -40°C to 85°C SSOP16 Tape and Reel Yes SP3220EEY-L/TR -40°C to 85°C TSSOP16 Tape and Reel Yes -40°C to 85°C TSSOP16 Tape and Reel Yes SP3220E SP3220EU SP3220EUEY-L/TR NOTES: 1. Refer to www.maxlinear.com/SP3220E, www.maxlinear.com/SP3220EB, www.maxlinear.com/SP3220EU for the most up-to-date Ordering Information. 2. Visit www.maxlinear.com for additional information on Environmental Rating. SP3220E_EB_EU_103_031920 18 REVISION HISTORY Date Revision Description 08/30/05 -- 02/02/11 1.0.0 Convert to Exar Format and update ordering information. 06/03/11 1.0.1 Remove SP3220EUCA-L(/TR) and SP3220EUEA-L(/TR) per PDN 110510-01. 10/20/16 1.0.2 Update input voltage range of receiver from +/-25V to +/-15V, update ordering information table, remove WSOIC package information. 03/19/20 1.0.3 Update to MaxLinear logo. Update Ordering Information. Legacy Sipex Datasheet. MaxLinear, Inc. 5966 La Place Court, Suite 100 Carlsbad, CA 92008 760.692.0711 p. 760.444.8598 f. www.maxlinear.com The content of this document is furnished for informational use only, is subject to change without notice, and should not be construed as a commitment by MaxLinear, Inc. MaxLinear, Inc. assumes no responsibility or liability for any errors or inaccuracies that may appear in the informational content contained in this guide. Complying with all applicable copyright laws is the responsibility of the user. Without limiting the rights under copyright, no part of this document may be reproduced into, stored in, or introduced into a retrieval system, or transmitted in any form or by any means (electronic, mechanical, photocopying, recording, or otherwise), or for any purpose, without the express written permission of MaxLinear, Inc. Maxlinear, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. 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