SP3221E
Intelligent +3.0V to +5.5V RS-232 Transceiver
FEATURES
• Meets true EIA/TIA-232-F Standards
from a +3.0V to +5.5V power supply
• Interoperable with EIA/TIA-232 and adheres
to EIA/TIA-562 down to a +2.7V power
source
• AUTO ON-LINE® circuitry automatically
wakes up from a 1µA typical shutdown
• Minimum 250kbps data rate under load
• Regulated charge pump yields stable
RS-232 outputs regardless of VCC variations
• ESD specifications:
+15KV Human Body Model
+15KV IEC61000-4-2 Air Discharge
+8KV IEC61000-4-2 Contact Discharge
EN
16 SHDN
1
C1+ 2
15 VCC
V+ 3
C1-
4
14 GND
SP3221E
C2+ 5
13 T1OUT
12 ONLINE
C2-
6
11 T1IN
V-
7
10
R1IN
8
9
STATUS
R1OUT
DESCRIPTION
The SP3221E is an RS-232 transceiver solution intended for portable applications such as
notebook and hand held computers. This device uses an internal high-efficiency, charge-pump
power supply that requires only 0.1µF capacitors in 3.3V operation. This charge pump and
Exar's driver architecture allow the SP3221E to deliver compliant RS-232 performance from
a single power supply ranging from +3.0V to +5.5V. The SP3221E is a 1-driver/1-receiver
device ideal for laptop/notebook computer and PDA applications. The SP3221E is offered
in 16 pin TSSOP and SSOP packages.
The AUTO ON-LINE® feature allows the device to automatically "wake-up" during a shutdown state when an RS-232 cable is connected and a connected peripheral is turned on.
Otherwise, the device automatically shuts itself down drawing less than 1µA.
SELECTION TABLE
Device
Power
Supplies
RS- 232
Drivers
RS-232
Receivers
AUTO ON-LINE ®
TTL
3-state
Data Rate
(kbps)
SP3221E
+3.0V to +5.5V
1
1
YES
YES
250
SP3221E_201_031920
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ABSOLUTE MAXIMUM RATINGS
Output Voltages
TxOUT.............................................................+13.2V
RxOUT, STATUS.......................-0.3V to (VCC + 0.3V)
Short-Circuit Duration
TxOUT.....................................................Continuous
Storage Temperature......................-65°C to +150°C
These are stress ratings only and functional operation
of the device at these ratings or any other above those
indicated in the operation sections of the specifications
below is not implied. Exposure to absolute maximum
rating conditions for extended periods of time may
affect reliability and cause permanent damage to the
device.
VCC.......................................................-0.3V to +6.0V
V+ (NOTE 1).......................................-0.3V to +7.0V
V- (NOTE 1)........................................+0.3V to -7.0V
V+ + |V-| (NOTE 1)...........................................+13V
ICC (DC VCC or GND current).........................+100mA
Input Voltages
TxIN, ONLINE,
SHUTDOWN, EN......................-0.3V to VCC + 0.3V
RxIN...................................................................+15V
Power Dissipation per package
16-pin TSSOP
Theta-JA.................................................100.4°C/W
Theta-JC.................................................19°C/W
16-pin SSOP
Theta-JA.................................................87°C/W
Theta-JC.................................................26°C/W
NOTE 1: V+ and V- can have maximum magnitudes of 7V, but their absolute difference cannot exceed 13V.
ELECTRICAL CHARACTERISTICS
Unless otherwise noted, the following specifications apply for VCC = +3.0V to +5.5V with TAMB = TMIN to TMAX.
Typical values apply at VCC = +3.3V or +5.0V and TAMB = 25°C (Note 2).
PARAMETER
MIN.
TYP.
MAX.
UNITS
CONDITIONS
Supply Current,
AUTO ON-LINE®
1.0
10
µA
RxIN open, ONLINE = GND,
SHUTDOWN = Vcc, TxIN = Vcc or
GND, Vcc = +3.3V, TAMB = +25ºC
Supply Current, Shutdown
1.0
10
µA
SHUTDOWN = GND,
TxIN = Vcc or GND, Vcc = +3.3V,
TAMB = +25ºC
Supply Current,
AUTO ON-LINE® Disabled
0.3
1.0
mA
ONLINE = SHUTDOWN = Vcc, No
Load, Vcc = +3.3V, TAMB = +25ºC
0.8
V
DC CHARACTERISTICS
LOGIC INPUTS AND RECEIVER OUTPUT
Input Logic Threshold
LOW
HIGH
2.0
Vcc = 3.3V or 5.0V,
TxIN, EN, SHUTDOWN, ONLINE
Input Leakage Current
+/-0.01
+/-1.0
µA
TxIN, EN, ONLINE, SHUTDOWN,
TAMB = +25ºC, Vin = 0V to Vcc
Output Leakage Current
+/-0.05
+/-10
µA
Receiver disabled,
Vout = 0V to Vcc
0.4
V
IOUT = 1.6mA
V
IOUT = -1.0mA
Output Voltage LOW
Output Voltage HIGH
Vcc - 0.6
Vcc - 0.1
NOTE 2: C1 - C4 = 0.1µF, tested at 3.3V ±10%.
C1 = 0.047µF, C2-C4 = 0.33µF, tested at 5V±10%.
SP3221E_201_031920
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ELECTRICAL CHARACTERISTICS
Unless otherwise noted, the following specifications apply for VCC = +3.0V to +5.5V with TAMB = TMIN to TMAX.
Typical values apply at VCC = +3.3V or +5.0V and TAMB = 25°C (Note 2).
PARAMETER
MIN.
TYP.
+/-5.0
+/-5.4
MAX.
UNITS
CONDITIONS
DRIVER OUTPUT
Output Voltage Swing
Output Resistance
300
V
Driver output loaded with 3kΩ to
GND, TAMB = +25ºC
Ω
Vcc = V+ = V- = 0V, Vout = +/-2V
Output Short-Circuit Current
+/-60
mA
Vout = 0V
Output Leakage Current
+/-25
µA
Vcc = 0V or 3.0V to 5.5V,
Vout = +/-12V, Driver disabled
+15
V
RECEIVER INPUT
Input Voltage Range
-15
Input Threshold LOW
0.6
Input Threshold LOW
0.8
1.2
Vcc = 3.3V
V
Vcc = 5.0V
Input Threshold HIGH
1.5
2.4
V
Vcc = 3.3V
Input Threshold HIGH
1.8
2.4
V
Vcc = 5.0V
Input Hysteresis
0.3
Input Resistance
3
1.5
V
V
5
7
kΩ
AUTO ON-LINE® CIRCUITRY CHARACTERISTICS (ONLINE = GND, SHUTDOWN = Vcc)
STATUS Output Voltage LOW
STATUS Output Voltage HIGH
0.4
Vcc - 0.6
V
IOUT = 1.6mA
V
IOUT = -1.0mA
Receiver Threshold to Driver
Enabled (tONLINE)
100
µs
Figure 13
Receiver Positive or Negative
Threshold to STATUS HIGH
(tSTSH)
0.5
µs
Figure 13
Receiver Positive or Negative
Threshold to STATUS LOW
(tSTSL)
20
µs
Figure 13
NOTE 2: C1 - C4 = 0.1µF, tested at 3.3V ±10%.
C1 = 0.047µF, C2-C4 = 0.33µF, tested at 5V±10%.
SP3221E_201_031920
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TIMING CHARACTERISTICS
Unless otherwise noted, the following specifications apply for VCC = +3.0V to +5.5V with TAMB = TMIN to TMAX.
Typical values apply at VCC = +3.3V or +5.0V and TAMB = 25°C.
PARAMETER
MIN.
TYP.
MAX.
UNITS
CONDITIONS
AC CHARACTERISTICS
Data Rate
250
kbps
RL = 3kΩ, CL = 1000pF,
Receiver Propagation Delay
tPHL and tPLH
0.15
µs
Receiver input to Receiver output,
CL = 150pF
Receiver Output Enable Time
200
ns
Normal Operation
Receiver Output Disable Time
200
ns
Normal Operation
Driver Skew
350
800
ns
│tPHL - tPLH│, RL = 3kΩ,
CL = 1000pF
Receiver Skew
50
800
ns
│tPHL - tPLH│, CL = 150pF
30
V/µs
Transition-Region Slew Rate
6
Vcc = 3.3V, RL = 3kΩ, CL = 150pF
to 1000pF, TAMB = 25°C, measurements taken from -3.0V to +3.0V
or +3.0V to -3.0V
SP3221E_201_031920
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TYPICAL OPERATING CIRCUIT
Figure 1. SP3221E Typical Operating Circuit
SP3221E_201_031920
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TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise noted, the following performance characteristics apply for VCC = +3.3V, 250Kbps data rate,
driver loaded with 3kΩ, 0.1µF charge pump capacitors, and TAMB = +25°C.
14
6
12
4
10
2
Ic c (m A )
8
V out
6
4
0
-2
2
0
Txout+
2.7
3.2
3.7
4.2
4.7
-4
5.2
-6
V c c (V )
2.7
3.2
3.7
4.2
4.7
5.2
TxoutVcc
Figure 3. Transmitter Output Voltage VS. Supply
Voltage
Figure 2. Supply Current VS. Supply Voltage
12
10
mA
8
6
4
2
0
0
100
200
300
kb p s
Figure 4. Supply Current VS.Data Rate
SP3221E_201_031920
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PIN DESCRIPTION
Name
Function
Pin #
EN
Receiver Enable, apply logic LOW for normal operation. Apply logic HIGH to
disable receiver output (high-Z state).
1
C1+
Positive terminal of the voltage doubler charge-pump capacitor
2
V+
Regulated +5.5V output generated by charge pump
3
C1-
Negative terminal of the voltage doubler charge-pump capacitor
4
C2+
Positive terminal of the inverting charge-pump capacitor
5
C2-
Negative terminal of the inverting charge-pump capacitor
6
Regulated -5.5V output generated by charge pump
7
RS-232 receiver input
8
VR1IN
R1OUT
TTL/CMOS receiver output
9
TTL/CMOS output indicating receiver signal activity
10
TTL/CMOS driver input
11
Apply logic HIGH to override AUTO ON-LINE ® circuitry keeping driver active
(SHUTDOWN must also be logic HIGH, refer to table 2)
12
RS-232 driver output
13
GND
Ground
14
Vcc
+3.0V to +5.5V supply voltage
15
Apply logic LOW to shut down drivers and charge pump. This overrides all
AUTO ON-LINE ® circuitry and ONLINE (refer to table 2).
16
STATUS
T1IN
ONLINE
T1OUT
SHUTDOWN
SP3221E_201_031920
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DESCRIPTION
THEORY OF OPERATION
The SP3221E is a 1-driver/1-receiver device
ideal for portable or handheld applications.
The SP3221E transceiver meets the EIA/
TIA-232 and ITU-T V.28/V.24 communication
protocols and can be implemented in batterypowered, portable, or handheld applications
such as notebook or handheld computers.
The SP3221E device features the Exar
proprietary and patented (U.S.‑‑ 5,306,954)
on-board charge pump circuitry that generates ±5.5V RS-232 voltage levels from a
single +3.0V to +5.5V power supply.
The SP3221E is made up of four basic
circuit blocks:
1. Driver, 2. Receiver, 3. The Exar proprietary charge pump, and 4. AUTO ON-LINE®
circuitry.
Driver
The driver is an inverting level transmitter that
converts TTL or CMOS logic levels to 5.0V
EIA/TIA-232 levels with an inverted sense
relative to the input logic levels. Typically,
the RS-232 output voltage swing is +5.4V
with no load and +5V minimum fully loaded.
The driver output is protected against infinite
short-circuits to ground without degradation
in reliability. This driver will comply with
the EIA-TIA-232F and all previous RS-232
versions. Unused driver inputs should be
connected to GND or VCC.
This device is an ideal choice for power sensitive designs. Featuring AUTO ON-LINE®
circuitry, the SP3221E reduces the power
supply drain to a 1µA supply current. In
many portable or handheld applications,
an RS-232 cable can be disconnected or
a connected peripheral can be turned off.
Under these conditions, the internal charge
pump and the drivers will be shut down.
Otherwise, the system automatically comes
online. This feature allows design engineers
to address power saving concerns without
major design changes.
The driver can guarantee an output data rate
of 250kbps while being fully loaded with 3kΩ
in parallel with 1000pF, ensuring compatibility
with PC-to-PC communication software.
The slew rate of the driver output is internally
limited to a maximum of 30V/µs in order
to meet the EIA standards (EIA RS-232D
2.1.7, Paragraph 5). The transition of the
loaded output from HIGH to LOW also
meets the monotonicity requirements of
the standard.
VCC
C5
C1
C2
+
+
+
2 C1+
0.1µF
0.1µF
TTL/CMOS OUTPUT
V+
SP3221E
C3
C4
T1OUT 13
11 T1IN
R1IN
9 R1OUT
1
16
12
+
0.1µF
V- 7
6 C2-
5KΩ
VCC
3
4 C15 C2+
TTL/CMOS INPUT
UART
or
Serial µC
15
VCC
0.1µF
8
+
0.1µF
Figure 6 shows a loopback test circuit used
to test the RS-232 Driver. Figure 8 shows
the test results where the driver was active at
250kbps and loaded with an RS-232 receiver
in parallel with a 1000pF capacitor. RS-232
data transmission rate of 250kbps provides
compatibility with designs in personal computer peripherals and LAN applications.
RS-232
OUTPUT
RS-232
INPUT
EN
SHUTDOWN
ONLINE
10 STATUS
GND
14
RESET
µP
Supervisor
IC
VIN
Figure 5. Interface Circuitry Controlled by Microprocessor Supervisory Circuit
SP3221E_201_031920
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Receiver
The receiver converts ±5.0V EIA/TIA-232
levels to TTL or CMOS logic output levels.
The receiver has an inverting output that can
be disabled by using the EN pin.
The receiver is active when the AUTO ONLINE® circuitry is enabled or when in shutdown. During the shutdown, the receiver will
continue to be active. If there is no activity
present at the receiver for a period longer
than 20µs or when SHUTDOWN is enabled,
the device goes into a standby mode where
the circuit draws 1µA. Driving EN to a logic
HIGH forces the output of the receiver into
high-impedance. The truth table logic of the
SP3221E driver and receiver outputs can be
found in Table 2.
Since receiver input is usually from a transmission line where long cable lengths and
system interference can degrade the signal,
the inputs have a typical hysteresis margin
of 300mV. This ensures that the receiver
is virtually immune to noisy transmission
lines. Should an input be left unconnected,
an internal 5kΩ pull-down resistor to ground
will commit the output of the receiver to a
HIGH state.
Figure 6. Loopback Test Circuit for RS-232 Driver
Data Transmission Rates
Figure 7. Loopback Test Circuit result at 250Kbps
(Driver Fully Loaded)
Device: SP3221E
SHUTDOWN
EN
TXOUT
RXOUT
0
0
High Z
Active
0
1
High Z
High Z
1
0
Active
Active
1
1
Active
High Z
Table 2. SHUTDOWN and EN Truth Tables
Note: In AUTO ON-LINE® Mode where ONLINE = GND
and SHUTDOWN = VCC, the device will shut down if
there is no activity present at the Receiver inputs.
SP3221E_201_031920
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Charge Pump
Phase 3
— VDD charge storage — The third phase of
the clock is identical to the first phase — the
charge transferred in C1 produces –VCC in
the negative terminal of C1, which is applied
to the negative side of capacitor C2. Since
C2+ is at VCC, the voltage potential across C2
is 2 times VCC.
The charge pump uses a unique approach
compared to older less–efficient designs.
The charge pump still requires four external
capacitors, but uses a four–phase voltage
shifting technique to attain symmetrical
5.5V power supplies. The internal power
supply consists of a regulated dual charge
pump that provides output voltages of
+/-5.5V regardless of input voltage (VCC)
over the +3.0V to +5.5V range. This
is important to maintain compliant RS232 levels regardless of power supply
fluctuations.
Phase 4
— VDD transfer — The fourth phase of
the clock connects the negative terminal
of C2 to GND, and transfers this positive
generated voltage across C2 to C4, the
VDD storage capacitor. This voltage is
regulated to +5.5V. At this voltage, the internal oscillator is disabled. Simultaneous
with the transfer of the voltage to C4, the
positive side of capacitor C1 is switched to VCC
and the negative side is switched to GND, allowing the charge pump cycle to begin again.
The charge pump cycle will continue as long
as the operational conditions for the internal
oscillator are present.
The charge pump operates in a discontinuous mode using an internal oscillator. If the
output voltages are less than a magnitude
of 5.5V, the charge pump is enabled. If the
output voltages exceed a magnitude of 5.5V,
the charge pump is disabled. This oscillator
controls the four phases of the voltage shifting. A description of each phase follows.
Since both V+ and V– are separately generated from VCC, in a no–load condition V+
and V– will be symmetrical. Older charge
pump approaches that generate V– from
V+ will show a decrease in the magnitude
of V– compared to V+ due to the inherent
inefficiencies in the design.
Phase 1
— VSS charge storage — During this phase
of the clock cycle, the positive side of capacitors C1 and C2 are initially charged to VCC.
Cl+ is then switched to GND and the charge
in C1– is transferred to C2–. Since C2+ is connected to VCC, the voltage potential across
capacitor C2 is now 2 times VCC.
Phase 2
— VSS transfer — Phase two of the clock
connects the negative terminal of C2 to the VSS
storage capacitor and the positive terminal of
C2 to GND. This transfers a negative generated voltage to C3. This generated voltage is
regulated to a minimum voltage of -5.5V.
Simultaneous with the transfer of the voltage to C3, the positive side of capacitor C1
is switched to VCC and the negative side is
connected to GND.
SP3221E_201_031920
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VCC = +5V
C4
+5V
+
C1
C2
–
–5V
+
–
+
–
–
+
VDD Storage Capacitor
VSS Storage Capacitor
C3
–5V
Figure 8. Charge Pump - Phase 1
VCC = +5V
C4
C1
+
C2
–
+
–
+
–
–
+
VDD Storage Capacitor
VSS Storage Capacitor
C3
–10V
Figure 9. Charge Pump - Phase 2
[
T
]
+6V
a) C2+
T
1
2
0V
2
0V
b) C2-
T
Ch1 2.00V Ch2 2.00V M 1.00ms Ch1 1.96V
-6V
Figure 10. Charge Pump Waveforms
VCC = +5V
C4
+5V
C1
+
–
C2
–5V
+
+
–
–
+
–
VDD Storage Capacitor
VSS Storage Capacitor
C3
–5V
Figure 11. Charge Pump - Phase 3
VCC = +5V
+10V
C1
+
–
C2
C4
+
+
–
–
–
+
VDD Storage Capacitor
VSS Storage Capacitor
C3
Figure 12. Charge Pump - Phase 4
SP3221E_201_031920
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Charge Pump Capacitor selection
The Exar charge pump is designed to
operate reliably with a range of low cost
capacitors.Either polarized or non polarized capacitors may be used. If polarized
capacitors are used they should be oriented
as shown in the Typical Operating Circuit.
The V+ capacitor may be connected to either
ground or Vcc (polarity reversed.)
on the transmitter outputs and may slightly
reduce power consumption. C2, C3, and
C4 can be increased without changing
C1’s value
For best charge pump efficiency locate the
charge pump and bypass capacitors as
close as possible to the IC. Surface mount
capacitors are best for this purpose. Using
capacitors with lower equivalent series resistance (ESR) and self-inductance, along
with minimizing parasitic PCB trace inductance will optimize charge pump operation.
Designers are also advised to consider that
capacitor values may shift over time and
operating temperature.
The charge pump operates with 0.1µF capacitors for 3.3V operation. For other supply
voltages, see the table for required capacitor
values. Do not use values smaller than those
listed. Increasing the capacitor values (e.g.,
by doubling in value) reduces ripple
Minimum recommended charge pump capacitor value
Input Voltage VCC
Charge pump capacitor value
3.0V to 3.6V
C1 - C4 = 0.1µF
4.5V to 5.5V
C1 = 0.047µF, C2-C4 = 0.33µF
3.0V to 5.5V
C1 - C4 = 0.22µF
Table 4. Capacitor selection table
SP3221E_201_031920
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The second stage of the AUTO ON-LINE®
circuitry, shown in Figure 15, processes the
receiver's RXINACT signal with an accumulated delay that disables the device to
a 1µA typical supply current. The STATUS
pin goes to a logic LOW when the cable
is disconnected. The typical accumulated
delay is around 20µs. When the SP3221E
driver and internal charge pump are disabled,
the supply current is reduced to 1µA typical.
This can commonly occur in handheld or
portable applications where the RS-232
cable is disconnected or the RS-232 driver
of the connected peripheral are truned off.
AUTO ON-LINE Circuitry
®
The SP3221E device has AUTO ON-LINE®
circuitry on board that saves power in applications such as laptop computers, PDA's,
and other portable systems.
The SP3221E device incorporates an AUTO
ON-LINE® circuit that automatically enables
itself when the external transmitter is enabled
and the cable is connected. Conversely,
the AUTO ON-LINE® circuit also disables
most of the internal circuitry when the device
is not being used and goes into a standby
mode where the device typically draws 1µA.
This function is externally controlled by the
ONLINE pin. When this pin is tied to a logic
LOW, the AUTO ON-LINE® function is active. Once active, the device is enabled until
there is no activity on the receiver input. The
receiver input typically sees at least ±3V,
which are generated from the transmitter
at the other end of the cable with a ±5V
minimum. When the external transmitter
is disabled or the cable is disconnected,
the receiver input will be pulled down by its
internal 5kΩ resistor to ground. When this
occurs over a period of time, the internal
transmitter will be disabled and the device
goes into a shutdown or standby mode.
When the ONLINE pin is HIGH, the AUTO
ON-LINE® mode is disabled.
The AUTO ON-LINE® mode can be disabled
by the SHUTDOWN pin. If this pin is a logic
LOW, the AUTO ON-LINE® function will not
operate regardless of the logic state of the
ONLINE pin. Table 3 summarizes the logic
of the AUTO ON-LINE® operating modes.
The truth table logic of the SP3221E driver
and receiver outputs can be found in Table 2.
When the SP3221E device is shutdown,
the charge pumps are turned off. V+ charge
pump output decays to VCC,the V- output
decays to GND. The decay time will depend
on the size of capacitors used for the charge
pump. Once in shutdown, the time required
to exit the shut down state and have valid
V+ and V- levels is typically 200µs.
For easy programming, the STATUS can
be used to indicate DTR or a Ring Indicator
signal. Tying ONLINE and SHUTDOWN
together will bypass the AUTO ON-LINE®
circuitry so this connection acts like a shutdown input pin
The AUTO ON-LINE ® circuit has two
stages:
1) Inactive Detection
2) Accumulated Delay
The first stage, shown in Figure 14, detects
an inactive input. A logic HIGH is asserted
on RXINACT if the cable is disconnected or
the external transmitters are disabled. Otherwise, RXINACT will be at a logic LOW.
SP3221E_201_031920
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RS-232 SIGNAL
AT RECEIVER
INPUT
SHUTDOWN
ONLINE
STATUS
TRANSCEIVER STATUS
YES
HIGH
LOW
HIGH
Normal Operation
(AUTO ON-LINE©)
YES
HIGH
HIGH
HIGH
Normal Operation
NO
HIGH
HIGH
LOW
Normal Operation
NO
HIGH
LOW
LOW
Shutdown (AUTO ON-LINE©)
YES
LOW
HIGH/LOW
HIGH
Shutdown
NO
LOW
HIGH/LOW
LOW
Shutdown
Table 3. AUTO ON-LINE® Logic
S
H
U
T
RECEIVER +2.7V
0V
RS-232 INPUT
VOLTAGES -2.7V
D
O
W
N
VCC
STATUS
0V
tSTSL
tSTSH
tONLINE
DRIVER
RS-232 OUTPUT
VOLTAGES
+5V
0V
-5V
Figure 13. AUTO ON-LINE® Timing Waveforms
Inactive Detection Block
RXIN
RS-232
Receiver Block
RX INACT
RXOUT
Figure 14. Stage I of AUTO ON-LINE® Circuitry
SP3221E_201_031920
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ESD TOLERANCE
The SP3221E device incorporates
ruggedized ESD cells on the driver output
and receiver input pins. The ESD structure is
improved over our previous family for more
rugged applications and environments
sensitive to electro-static discharges and
associated transients. The improved ESD
tolerance is at least +15kV without damage
nor latch-up.
ESD is applied to points and surfaces of the
equipment that are accessible to personnel
during normal usage. The transceiver IC
receives most of the ESD current when the
ESD source is applied to the connector pins.
The test circuit for IEC61000-4-2 is shown
on Figure 16. There are two methods within
IEC61000-4-2, the Air Discharge method and
the Contact Discharge method. With the Air
Discharge Method, an ESD voltage is applied
to the equipment under test (EUT) through
air. This simulates an electrically charged
person ready to connect a cable onto the
rear of the system only to find an unpleasant
zap just before the person touches the back
panel. The high energy potential on the
person discharges through an arcing path
to the rear panel of the system before he or
she even touches the system. This energy,
whether discharged directly or through air,
is predominantly a function of the discharge
current rather than the discharge voltage.
Variables with an air discharge such as
approach speed of the object carrying the
ESD potential to the system and humidity
will tend to change the discharge current.
For example, the rise time of the discharge
current varies with the approach speed.
The Contact Discharge Method applies the
ESD current directly to the EUT. This method
was devised to reduce the unpredictability
of the ESD arc. The discharge current rise
time is constant since the energy is directly
transferred without the air-gap arc. In situations such as hand held systems, the ESD
charge can be directly discharged to the
equipment from a person already holding
the equipment. The current is transferred
on to the keypad or the serial port of the
equipment directly and then travels through
the PCB and finally to the IC.
There are different methods of ESD testing
applied:
a) MIL-STD-883, Method 3015.7
b) IEC61000-4-2 Air-Discharge
c) IEC61000-4-2 Direct Contact
The Human Body Model has been the
generally accepted ESD testing method
for semiconductors. This method is also
specified in MIL-STD-883, Method 3015.7
for ESD testing. The premise of this ESD test
is to simulate the human body’s potential to
store electro-static energy and discharge it
to an integrated circuit. The simulation is
performed by using a test model as shown
in Figure 15. This method will test the IC’s
capability to withstand an ESD transient
during normal handling such as in manufacturing areas where the IC's tend to be
handled frequently.
The IEC-61000-4-2, formerly IEC801-2, is
generally used for testing ESD on equipment
and systems. For system manufacturers,
they must guarantee a certain amount of
ESD protection since the system itself is
exposed to the outside environment and
human presence. The premise with IEC61000-4-2 is that the system is required to
withstand an amount of static electricity when
Figure15. ESD Test Circuit for Human Body Model
SP3221E_201_031920
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Figure 16. ESD Test Circuit for IEC61000-4-2
i→
The circuit model in Figures 15 and 16 represent the typical ESD testing circuit used for
all three methods. The CS is initially charged
with the DC power supply when the first
switch (SW1) is on. Now that the capacitor
is charged, the second switch (SW2) is on
while SW1 switches off. The voltage stored
in the capacitor is then applied through RS,
the current limiting resistor, onto the device
under test (DUT). In ESD tests, the SW2
switch is pulsed so that the device under
test receives a duration of voltage.
30A
15A
0A
For the Human Body Model, the current
limiting resistor (RS) and the source capacitor
(CS) are 1.5kΩ an 100pF, respectively. For
IEC-61000-4-2, the current limiting resistor
(RS) and the source capacitor (CS) are 330Ω
an 150pF, respectively.
t=0ns
t→
t=30ns
Figure 17. ESD Test Waveform for IEC61000-4-2
The higher CS value and lower RS value in
the IEC-61000-4-2 model are more stringent
than the Human Body Model. The larger
storage capacitor injects a higher voltage
to the test point when SW2 is switched on.
The lower current limiting resistor increases
the current charge onto the test point.
DEVICE PIN
TESTED
Driver Output
Receiver Input
HUMAN BODY
MODEL
Air Discharge
±15kV
±15kV
±15kV
±15kV
IEC61000-4-2
Direct Contact
±8kV
±8kV
Level
4
4
Table 5. Transceiver ESD Tolerance Levels
SP3221E_201_031920
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PACKAGE: 16 Pin TSSOP
SP3221E_201_031920
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PACKAGE: 16 Pin SSOP
SP3221E_201_031920
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ORDERING INFORMATION(1)
Part Number
Temperature
Range
Package
Packaging
Method
Lead-Free(2)
SP3221EEA-L/TR
-40°C to +85°C
16-pin SSOP
Tape and Reel
Yes
SP3221EEY-L/TR
-40°C to +85°C
16-pin TSSOP
Tape and Reel
Yes
NOTES:
1. Refer to www.maxlinear.com/SP3221E for most up-to-date Ordering Information.
2. Visit www.maxlinear.com for additional information on Environmental Rating.
SP3221E_201_031920
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REVISION HISTORY
DATE
REVISION
DESCRIPTION
Nov 2012
1.0.0
Production release
Dec 2012
1.0.1
Remove reference to SSOP package
Sept 2014
1.0.2
Add SSOP package option, update package thermal information
ECN 1414-04 Oct 2014
Aug 2016
2.0.0
Update Auto On-Line Circuitry section and Logic table
Mar 2020
2.0.1
Update to MaxLinear logo. Update Ordering Information.
MaxLinear, Inc.
5966 La Place Court, Suite 100
Carlsbad, CA 92008
760.692.0711 p.
760.444.8598 f.
www.maxlinear.com
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