SP3223EBEA-L/TR

SP3223E / SP3223EB / SP3223EU Intelligent +3.0V to +5.5V RS-232 Transceivers FEATURES • Meets true EIA/TIA-232-F Standards from a +3.0V to +5.5V power supply • Interoperable with EIA/TIA-232 and adheres to EIA/TIA-562 down to a +2.7V power source • AUTO ON-LINE® circuitry automatically wakes up from a 1µA shutdown • Minimum 250Kbps data rate under load (EB) • 1 Mbps data rate for high speed RS-232 (EU) • Regulated Charge Pump Yields Stable RS-232 Outputs Regardless of VCC Variations • ESD Specifications: +15KV Human Body Model +15KV IEC61000-4-2 Air Discharge +8KV IEC61000-4-2 Contact Discharge EN 20 SHUTDOWN 1 C1+ 2 19 Vcc V+ 3 18 GND C1- 4 17 T1OUT C2+ 5 16 R1IN C2- 6 15 R1OUT V- 7 14 ONLINE SP3223E T2OUT 8 13 T1IN R1IN 9 12 T2IN R2OUT 10 11 STATUS Now Available in Lead Free Packaging DESCRIPTION The SP3223 products are RS-232 transceiver solutions intended for portable applications such as notebook and hand held computers. These products use an internal high-efficiency, charge-pump power supply that requires only 0.1µF capacitors in 3.3V operation. This charge pump and Exar's driver architecture allow the SP3223 series to deliver compliant RS-232 performance from a single power supply ranging from +3.3V to +5.0V. The SP3223 is a 2driver/2-receiver device ideal for laptop/notebook computer and PDA applications. The AUTO ON-LINE® feature allows the device to automatically "wake-up" during a shutdown state when an RS-232 cable is connected and a connected peripheral is turned on. Otherwise, the device automatically shuts itself down drawing less than 1µA. SELECTION TABLE Device Power Supplies RS- 232 Drivers RS-232 Receivers AUTO ON-LINE ® TTL 3-state Data Rate (kbps) SP3223E +3.0V to +5.5V 2 2 YES YES 120 SP3223EB +3.0V to +5.5V 2 2 YES YES 250 SP3223EU +3.0V to +5.5V 2 2 YES YES 1000 SP3223E/EB/EU_102_031920 1 ABSOLUTE MAXIMUM RATINGS These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability and cause permanent damage to the device. VCC.......................................................-0.3V to +6.0V V+ (NOTE 1).......................................-0.3V to +7.0V V- (NOTE 1)........................................+0.3V to -7.0V V+ + |V-| (NOTE 1)...........................................+13V ICC (DC VCC or GND current).........................+100mA Input Voltages TxIN, ONLINE, SHUTDOWN, EN......................-0.3V to VCC + 0.3V RxIN...................................................................+15V Output Voltages TxOUT.............................................................+13.2V RxOUT, STATUS.......................-0.3V to (VCC + 0.3V) Short-Circuit Duration TxOUT.....................................................Continuous Storage Temperature......................-65°C to +150°C Power Dissipation per package 20-pin SSOP (derate 9.25mW/oC above +70oC)..750mW 20-pin TSSOP (derate 11.1mW/oC above +70oC..900mW NOTE 1: V+ and V- can have maximum magnitudes of 7V, but their absolute difference cannot exceed 13V. ELECTRICAL CHARACTERISTICS Unless otherwise noted, the following specifications apply for VCC = +3.0V to +5.5V with TAMB = TMIN to TMAX. Typical values apply at VCC = +3.3V or +5.0V and TAMB = 25°C (Note 2). PARAMETER MIN. TYP. MAX. UNITS DC CHARACTERISTICS Supply Current, AUTO ON-LINE® 1.0 10 µA Supply Current, Shutdown 1.0 10 µA Supply Current, AUTO ON-LINE® Disabled 0.3 1.0 mA 0.8 Vcc V CONDITIONS All RxIN open, ONLINE = GND, SHUTDOWN = Vcc, TxIN = Vcc or GND, Vcc = +3.3V, TAMB = +25ºC SHUTDOWN = GND, TxIN = Vcc or GND, Vcc = +3.3V, TAMB = +25ºC ONLINE = SHUTDOWN = Vcc, No Load, Vcc = +3.3V, TAMB = +25ºC LOGIC INPUTS AND RECEIVER OUTPUTS Input Logic Threshold LOW HIGH GND 2.0 Vcc = 3.3V or 5.0V, TxIN, EN, SHUTDOWN, ONLINE Input Leakage Current +/-0.01 +/-1.0 µA TxIN, EN, ONLINE, SHUTDOWN, TAMB = +25ºC, Vin = 0V to Vcc Output Leakage Current +/-0.05 +/-10 µA Receivers disabled, Vout = 0V to Vcc 0.4 V IOUT = 1.6mA V IOUT = -1.0mA Output Voltage LOW Output Voltage HIGH Vcc - 0.6 Vcc - 0.1 NOTE 2: C1 - C4 = 0.1µF, tested at 3.3V ±10%. C1 = 0.047µF, C2-C4 = 0.33µF, tested at 5V±10%. SP3223E/EB/EU_102_031920 2 ELECTRICAL CHARACTERISTICS Unless otherwise noted, the following specifications apply for VCC = +3.0V to +5.5V with TAMB = TMIN to TMAX. Typical values apply at VCC = +3.3V or +5.0V and TAMB = 25°C (Note 2). PARAMETER Driver Outputs Output Voltage Swing Output Resistance MIN. +/-5.0 TYP. MAX. +/-5.4 300 Output Short-Circuit Current +/-35 Output Leakage Current RECEIVER INPUTS Input Voltage Range -15 UNITS CONDITIONS V All Driver outputs loaded with 3kΩ to GND, TAMB = +25ºC Ω Vcc = V+ = V- = 0V, Vout = +/-2V +/-60 mA Vout = 0V +/-25 µA Vcc = 0V or 3.0V to 5.5V, Vout = +/-12V, Driver disabled +15 V Input Threshold LOW 0.6 1.2 V Vcc = 3.3V Input Threshold LOW 0.8 1.5 V Vcc = 5.0V Input Threshold HIGH 1.5 2.4 V Vcc = 3.3V Input Threshold HIGH 1.8 2.4 V Vcc = 5.0V 7 kΩ Input Hysteresis Input Resistance 0.3 3 V 5 AUTO ON-LINE® CIRCUITRY CHARACTERISTICS (ONLINE = GND, SHUTDOWN = Vcc) STATUS Output Voltage LOW STATUS Output Voltage HIGH 0.4 Vcc - 0.6 V IOUT = 1.6mA V IOUT = -1.0mA Receiver Threshold to Drivers Enabled (tONLINE) 200 µs Figure 15 Receiver Positive or Negative Threshold to STATUS HIGH (tSTSH) 0.5 µs Figure 15 Receiver Positive or Negative Threshold to STATUS LOW (tSTSL) 20 µs Figure 15 NOTE 2: C1 - C4 = 0.1µF, tested at 3.3V ±10%. C1 = 0.047µF, C2-C4 = 0.33µF, tested at 5V±10%. SP3223E/EB/EU_102_031920 3 TIMING CHARACTERISTICS Unless otherwise noted, the following specifications apply for VCC = +3.0V to +5.5V with TAMB = TMIN to TMAX. Typical values apply at VCC = +3.3V or +5.0V and TAMB = 25°C. PARAMETER MIN. TYP. 120 235 MAX. UNITS CONDITIONS Maximum Data Rate SP3223E SP3223EB 250 SP3223EU 1000 kbps RL = 3kΩ, CL = 1000pF, One Driver active RL = 3kΩ, CL = 250pF, One Driver active Receiver Propagation Delay tPHL and tPLH 0.15 µA Receiver input to Receiver output, CL = 150pF Receiver Output Enable Time 200 ns Normal Operation Receiver Output Disable Time 200 ns Normal Operation │tPHL - tPLH│, TAMB = 25°C Driver Skew E, EB 100 500 ns EU 50 100 ns 200 1000 ns Receiver Skew E, EB, EU │tPHL - tPLH│ Transition-Region Slew Rate E, EB EU 30 90 V/µs Vcc = 3.3V, RL = 3kΩ, TAMB = 25°C, measurements taken from -3.0V to +3.0V or +3.0V to -3.0V SP3223E/EB/EU_102_031920 4 TYPICAL OPERATING CIRCUIT Figure 1. SP3223E Typical Operating Circuit SP3223E/EB/EU_102_031920 5 TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise noted, the following performance characteristics apply for VCC = +3.3V, 250Kbps data rate, all drivers loaded with 3kΩ, 0.1µF charge pump capacitors, and TAMB = +25°C. 30 6 4 25 TxOUT + 2 20 0 15 + Slew 10 -2 TxOUT - -4 -6 - Slew 0 1000 1 T ransmitter at 250Kbps 1 T ransmitter at 15.6Kbps All drivers loaded 3K + Load Cap 5 2000 3000 4000 0 5000 0 500 1000 2000 3000 4000 5000 Load Capacitance (pF) Load Capacitance (pF) Figure 2. Transmitter Output Voltage VS. Load Capacitance for the SP3223EB Figure 3. Slew Rate VS. Load Capacitance for the SP3223EB 35 20 30 25 15 250K bps 20 125K bps 10 15 20K bps 10 5 0 0 1000 2000 3000 4000 1 T ransmitter at 250Kbps 2 T ransmitters at 15.6Kbps All drivers loaded with 3K // 1000pF 5 1 T ransmitter at 250Kbps 1 T ransmitter at 15.6Kbps All drivers loaded 3K + Load Cap 0 5000 Load Capacitance (pF) 2.7 3 3.5 4 4.5 5 Supply VVoltage Supply oltage(Vdc) (V DC ) Figure 5. Supply Current VS. Supply Voltage for the SP3223EB Figure 4. Supply Current VS. Load Capacitance when Transmitting Data for the SP3223EB 6 Tx OUT + 4 2 0 -2 -4 -6 Tx OUT - 2.7 3 3.5 4 4.5 5 Supply VVoltage Supply oltage(Vdc) (V DC ) Figure 6. Transmitter Output Voltage VS. Supply Voltage for the SP3223EB SP3223E/EB/EU_102_031920 6 TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise noted, the following performance characteristics apply for VCC = +3.3V, 1000Kbps data rate, all drivers loaded with 3kΩ, 0.1µF charge pump capacitors, and TAMB = +25°C. 6 200 4 150 2 -2 T1 at 500K bps T2 at 31. 2K bps All TX loaded 3K // CLoad 50 0 0 250 -4 500 1000 1500 Load Capacitance (pF) -6 2000 2.7 3 3.5 4 Supply V oltage (V) Supply Voltage (V) 4.5 5 Figure 8. Transmitter Output Voltage VS. Supply Voltage for the SP3223EU Figure 7. Transmitter Skew VS. Load Capacitance for the SP3223EU 35 6 30 4 T1 at 1Mbps T2 at 62. 5K bps 2 25 20 0 15 -2 T1 at 1Mbps T2 at 62. 5K bps 10 -4 -6 1D river at 1Mbps Other D rivers at 62. 5K bps All Drive rs Loaded with 3K // 250pF 0 100 5 0 250 500 1000 Load Capacitance (pF) 0 1500 Figure 9. Transmitter Output Voltage VS. Load Capacitance for the SP3223EU 250 500 1000 Load Capacitance (pF) 1500 Figure 10. Supply Current VS. Load Capacitance for the SP3223EU 6 20 4 15 2 10 2.7 3 3.5 4 Supply V Voltage oltage (V) Supply (V) 4.5 T1 at 1Mbps T2 at 62. 5K bps All Drive rs loaded with 3K //250pF 0 T1 at 1Mbps T2 at 62. 5K bps All Drive rs loaded with 3K //250pF 5 0 0 -2 -4 -6 5 2.7 3 3.5 4 Supply oltage (V) SupplyV Voltage (V) 4.5 5 Figure 12. Transmitter Output Voltage VS. Supply Voltage for the SP3223EU Figure 11. Supply Current VS. Supply Voltage for the SP3223EU SP3223E/EB/EU_102_031920 7 PIN DESCRIPTION Name Function Pin # EN Receiver Enable, Apply logic LOW for normal operation. Apply logic HIGH to disable receiver outputs (high-Z state). 1 C1+ Positive terminal of the voltage doubler charge-pump capacitor 2 V+ Regulated +5.5V output generated by charge pump 3 C1- Negative terminal of the voltage doubler charge-pump capacitor 4 C2+ Positive terminal of the inverting charge-pump capacitor 5 C2- Negative terminal of the inverting charge-pump capacitor 6 Regulated -5.5V output generated by charge pump 7 T2OUT RS-232 Driver output 8 R2IN RS-232 receiver input 9 TTL/CMOS receiver output 10 V- R2OUT STATUS TTL/CMOS output indicating online and shutdown status 11 T2IN TTL/CMOS driver input 12 T1IN TTL/CMOS driver input 13 ONLINE Apply logic HIGH to override AUTO ON-LINE ® circuitry keeping drivers active (SHUTDOWN must also be logic HIGH, refer to table 2). 14 R1OUT TTL/CMOS receiver output 15 R1IN RS-232 receiver input 16 T1OUT RS-232 Driver output 17 GND Ground 18 Vcc +3.0V to +5.5V supply voltage 19 Apply logic LOW to shut down drivers and charge pump. This overrides all AUTO ON-LINE ® circuitry and ONLINE (refer to table 2). 20 SHUTDOWN Table 2. Pin Description SP3223E/EB/EU_102_031920 8 DESCRIPTION THEORY OF OPERATION The SP3223 is a 2-driver/2-receiver device ideal for portable or handheld applications. The SP3223 transceivers meet the EIA/TIA232 and ITU-T V.28/V.24 communication protocols and can be implemented in batterypowered, portable, or handheld applications such as notebook or handheld computers. The SP3223 devices feature Exar's proprietary on-board charge pump circuitry that generates ±5.5V RS-232 voltage levels from a single +3.0V to +5.5V power supply. The SP3223 series is made up of four basic circuit blocks: 1. Drivers, 2. Receivers, 3. The Exar proprietary charge pump, and 4. AUTO ONLINE® circuitry. Drivers The drivers are inverting level transmitters that convert TTL or CMOS logic levels to 5.0V EIA/TIA-232 levels with an inverted sense relative to the input logic levels. Typically, the RS-232 output voltage swing is +5.4V with no load and +5V minimum fully loaded. The driver outputs are protected against infinite short-circuits to ground without degradation in reliability. These drivers comply with the EIA-TIA-232F and all previous RS-232 versions. Unused driver inputs should be connected to GND or VCC. These devices are an ideal choice for power sensitive designs. Featuring AUTO ON-LINE® circuitry, the SP3223 reduces the power supply drain to a 1µA supply current. In many portable or handheld applications, an RS-232 cable can be disconnected or a connected peripheral can be turned off. Under these conditions, the internal charge pump and the drivers will be shut down. Otherwise, the system automatically comes online. This feature allows design engineers to address power saving concerns without major design changes. The drivers can guarantee output data rates fully loaded with 3kΩ in parallel with 1000pF, (SP3223EU, CL= 250pF) ensuring compatibility with PC-to-PC communication software. The slew rate of the driver output on the E and EB versions is internally limited to a maximum of 30V/µs in order to meet the EIA standards (EIA RS-232D 2.1.7, Paragraph 5). The Slew Rate of EU version is not limited to enable higher speed data transfers. The transition of the loaded output from HIGH to LOW also meets the monotonicity requirements of the standard. VCC C5 C1 C2 + + + 2 C1+ 0.1µF 0.1µF V+ SP3223E C3 C4 11 T1IN T1OUT 17 12 T2IN T2OUT 8 5KΩ 10 R2OUT + 0.1µF V- 7 6 C2- 15 R1OUT TTL/CMOS OUTPUTS 3 4 C15 C2+ TTL/CMOS INPUTS UART or Serial µC 19 VCC 0.1µF R1IN 16 R2IN 9 + 0.1µF RS-232 OUTPUTS RS-232 INPUTS 5KΩ Figure 14 shows a loopback test circuit used to test the RS-232 Drivers. Figure 15 shows the test results where one driver was active at 250kbps and all drivers are loaded with an RS-232 receiver in parallel with a 1000pF capacitor. RS-232 data transmission rate of 120kbps to 1Mbps provide compatibility with designs in personal computer peripherals and LAN applications. EN VCC 20 14 SHUTDOWN ONLINE 11 STATUS GND 18 RESET µP Supervisor IC VIN Figure 13. Interface Circuitry Controlled by Microprocessor Supervisory Circuit SP3223E/EB/EU_102_031920 9 Device: SP3223 SHUTDOWN EN TXOUT RXOUT 0 0 High Z Active 0 1 High Z High Z 1 0 Active Active 1 1 Active High Z Table 3. SHUTDOWN and EN Truth Tables Note: In AUTO ON-LINE® Mode where ONLINE = GND and SHUTDOWN = VCC, the device will shut down if there is no activity present at the Receiver inputs. Receivers The receivers convert ±5.0V EIA/TIA-232 levels to TTL or CMOS logic output levels. Receivers have an inverting output that can be disabled by using the EN pin. Figure 14. Loopback Test Circuit for RS-232 Driver Data Transmission Rates Receivers are active when the AUTO ONLINE® circuitry is enabled or when in shutdown. During the shutdown, the receivers will continue to be active. If there is no activity present at the receivers for a period longer than 100µs or when SHUTDOWN is enabled, the device goes into a standby mode where the circuit draws 1µA. Driving EN to a logic HIGH forces the outputs of the receivers into high-impedance. The truth table logic of the SP3223 driver and receiver outputs can be found in Table 2. Figure 15. Loopback Test Circuit result at 250Kbps (All Drivers Fully Loaded) Since receiver input is usually from a transmission line where long cable lengths and system interference can degrade the signal, the inputs have a typical hysteresis margin of 300mV. This ensures that the receiver is virtually immune to noisy transmission lines. Should an input be left unconnected, an internal 5kΩ pull-down resistor to ground will commit the output of the receiver to a HIGH state. Charge Pump The charge pump uses a unique approach compared to older less–efficient designs. The charge pump still requires four external capacitors, but uses a four–phase voltage shifting technique to attain symmetrical 5.5V power supplies. The internal power supply consists of a regulated dual charge pump that provides output voltages of +/-5.5V regardless of input voltage (VCC) over the +3.0V to +5.5V range. This is important to maintain compliant RS232 levels regardless of power supply fluctuations. SP3223E/EB/EU_102_031920 10 The charge pump operates in a discontinuous mode using an internal oscillator. If the output voltages are less than a magnitude of 5.5V, the charge pump is enabled. If the output voltages exceed a magnitude of 5.5V, the charge pump is disabled. This oscillator controls the four phases of the voltage shifting. A description of each phase follows. as the operational conditions for the internal oscillator are present. Since both V+ and V– are separately generated from VCC, in a no–load condition V+ and V– will be symmetrical. Older charge pump approaches that generate V– from V+ will show a decrease in the magnitude of V– compared to V+ due to the inherent inefficiencies in the design. Phase 1 — VSS charge storage — During this phase of the clock cycle, the positive side of capacitors C1 and C2 are initially charged to VCC. Cl+ is then switched to GND and the charge in C1– is transferred to C2–. Since C2+ is connected to VCC, the voltage potential across capacitor C2 is now 2 times VCC. The Exar charge pump is designed to operate reliably with a range of low cost capacitors. Either polarized or non polarized capacitors may be used. If polarized capacitors are used they should be oriented as shown in the Typical Operating Circuit. The V+ capacitor may be connected to either ground or Vcc (polarity reversed.) Phase 2 — VSS transfer — Phase two of the clock connects the negative terminal of C2 to the VSS storage capacitor and the positive terminal of C2 to GND. This transfers a negative generated voltage to C3. This generated voltage is regulated to a minimum voltage of -5.5V. Simultaneous with the transfer of the voltage to C3, the positive side of capacitor C1 is switched to VCC and the negative side is connected to GND. The charge pump operates with 0.1µF capacitors for 3.3V operation. For other supply voltages, see table 4 for required capacitor values. Do not use values smaller than those listed. Increasing the capacitor values (e.g., by doubling in value) reduces ripple on the transmitter outputs and may slightly reduce power consumption. C2, C3, and C4 can be increased without changing C1’s value. Phase 3 — VDD charge storage — The third phase of the clock is identical to the first phase — the charge transferred in C1 produces –VCC in the negative terminal of C1, which is applied to the negative side of capacitor C2. Since C2+ is at VCC, the voltage potential across C2 is 2 times VCC. For best charge pump efficiency locate the charge pump and bypass capacitors as close as possible to the IC. Surface mount capacitors are best for this purpose. Using capacitors with lower equivalent series resistance (ESR) and self-inductance, along with minimizing parasitic PCB trace inductance will optimize charge pump operation. Designers are also advised to consider that capacitor values may shift over time and operating temperature. Phase 4 — VDD transfer — The fourth phase of the clock connects the negative terminal of C2 to GND, and transfers this positive generated voltage across C2 to C4, the VDD storage capacitor. This voltage is regulated to +5.5V. At this voltage, the internal oscillator is disabled. Simultaneous with the transfer of the voltage to C4, the positive side of capacitor C1 is switched to VCC and the negative side is switched to GND, allowing the charge pump cycle to begin again. The charge pump cycle will continue as long SP3223E/EB/EU_102_031920 11 VCC = +5V C4 +5V + C1 + C2 – –5V – + – VDD Storage Capacitor – + VSS Storage Capacitor C3 –5V Figure 16. Charge Pump - Phase 1 VCC = +5V C4 C1 + + C2 – – + – VDD Storage Capacitor – + VSS Storage Capacitor C3 –10V Figure 17. Charge Pump - Phase 2 [ T ] +6V a) C2+ T 1 0V 2 2 0V b) C2- T Ch1 2.00V Ch2 2.00V M 1.00ms Ch1 1.96V -6V Figure 18. Charge Pump Waveforms VCC = +5V C4 +5V C1 + – + C2 –5V + – VDD Storage Capacitor – + VSS Storage Capacitor – C3 –5V Figure 19. Charge Pump - Phase 3 VCC = +5V C4 +10V C1 + – C2 + – + – VDD Storage Capacitor – + VSS Storage Capacitor C3 Figure 20. Charge Pump - Phase 4 Minimum recommended charge pump capacitor value Input Voltage VCC Charge pump capacitor value 3.0V to 3.6V C1 - C4 = 0.1µF 4.5V to 5.5V C1 = 0.047µF, C2-C4 = 0.33µF 3.0V to 5.5V C1 - C4 = 0.22µF Table 4. Minimum Charge Pump Capacitor values SP3223E/EB/EU_102_031920 12 The second stage of the AUTO ON-LINE® circuitry, shown in Figure 23, processes the receiver's RXINACT signal with an accumulated delay that disables the device to a 1µA typical supply current. The STATUS pin goes to a logic LOW when the cable is disconnected, the external transmitter is disabled, or the SHUTDOWN pin is invoked. The typical accumulated delay is around 20µs. When the SP3223 drivers and internal charge pump are disabled, the supply current is reduced to 1µA typical. This can commonly occur in handheld or portable applications where the RS-232 cable is disconnected or the RS-232 drivers of the connected peripheral are truned off. The AUTO ON-LINE® mode can be disabled by the SHUTDOWN pin. If this pin is a logic LOW, the AUTO ON-LINE® function will not operate regardless of the logic state of the ONLINE pin. Table 5 summarizes the logic of the AUTO ON-LINE® operating modes. The truth table logic of the SP3223 driver and receiver outputs can be found in Table 3. AUTO ON-LINE Circuitry ® The SP3223 device has AUTO ON-LINE® circuitry on board that saves power in applications such as laptop computers, PDA's, and other portable systems. The SP3223 device incorporates an AUTO ON-LINE® circuit that automatically enables itself when the external transmitter is enabled and the cable is connected. Conversely, the AUTO ON-LINE® circuit also disables most of the internal circuitry when the device is not being used and goes into a standby mode where the device typically draws 1µA. This function is externally controlled by the ONLINE pin. When this pin is tied to a logic LOW, the AUTO ON-LINE® function is active. Once active, the device is enabled until there is no activity on receiver inputs. The receiver input typically sees at least ±3V, which are generated from the transmitter at the other end of the cable with a ±5V minimum. When the external transmitter is disabled or the cable is disconnected, the receiver input will be pulled down by its internal 5kΩ resistor to ground. When this occurs over a period of time, the internal transmitters will be disabled and the device goes into a shutdown or standby mode. When the ONLINE pin is HIGH, the AUTO ON-LINE® mode is disabled. The STATUS pin outputs a logic LOW signal if the device is shutdown. This pin goes to a logic HIGH when the external transmitter is enabled and the cable is connected. When the SP3223 device is shutdown, the charge pumps are turned off. V+ charge pump output decays to VCC,the V- output decays to GND. The decay time will depend on the size of capacitors used for the charge pump. Once in shutdown, the time required to exit the shut down state and have valid V+ and V- levels is typically 200µs. The AUTO ON-LINE ® circuit has two stages: 1) Inactive Detection 2) Accumulated Delay For easy programming, the STATUS can be used to indicate DTR or a Ring Indicator signal. Tying ONLINE and SHUTDOWN together will bypass the AUTO ON-LINE® circuitry so this connection acts like a shutdown input pin The first stage, shown in Figure 22, detects an inactive input. A logic HIGH is asserted on RXINACT if the cable is disconnected or the external transmitters are disabled. Otherwise, RXINACT will be at a logic LOW. This circuit is duplicated for each of the other receivers. SP3223E/EB/EU_102_031920 13 S H U T R E C E IV E R +2.7V 0V R S -232 INP UT V OLTAG E S -2.7V D O W N VCC S TAT US 0V tS T S L tS T S H tONL INE DR IV E R R S -232 OUT P UT V OLTAG E S +5V 0V -5V Figure 21. AUTO ON-LINE® Timing Waveforms RS-232 SIGNAL AT RECEIVER INPUT SHUTDOWN ONLINE STATUS TRANSCEIVER STATUS YES HIGH LOW HIGH Normal Operation (AUTO ON-LINE©) NO HIGH HIGH LOW Normal Operation NO HIGH LOW LOW Shutdown (AUTO ON-LINE©) YES LOW HIGH/LOW HIGH Shutdown NO LOW HIGH/LOW LOW Shutdown Table 5. AUTO ON-LINE® Logic Inactive Detection Block RXIN RS-232 Receiver Block RX INACT RXOUT Figure 22. Stage I of AUTO ON-LINE® Circuitry Delay Buffer Delay Buffer INACTIVE R 1ON R 2 ON SHUTDOWN Figure 23. Stage II of AUTO ON-LINE® Circuitry SP3223E/EB/EU_102_031920 14 ESD TOLERANCE The SP3223 series incorporates ruggedized ESD cells on all driver output and receiver input pins. The ESD structure is improved over our previous family for more rugged applications and environments sensitive to electro-static discharges and associated transients. The improved ESD tolerance is at least +15kV without damage nor latch-up. is applied to points and surfaces of the equipment that are accessible to personnel during normal usage. The transceiver IC receives most of the ESD current when the ESD source is applied to the connector pins. The test circuit for IEC61000-4-2 is shown on Figure 25. There are two methods within IEC61000-4-2, the Air Discharge method and the Contact Discharge method. With the Air Discharge Method, an ESD voltage is applied to the equipment under test (EUT) through air. This simulates an electrically charged person ready to connect a cable onto the rear of the system only to find an unpleasant zap just before the person touches the back panel. The high energy potential on the person discharges through an arcing path to the rear panel of the system before he or she even touches the system. This energy, whether discharged directly or through air, is predominantly a function of the discharge current rather than the discharge voltage. Variables with an air discharge such as approach speed of the object carrying the ESD potential to the system and humidity will tend to change the discharge current. For example, the rise time of the discharge current varies with the approach speed. The Contact Discharge Method applies the ESD current directly to the EUT. This method was devised to reduce the unpredictability of the ESD arc. The discharge current rise time is constant since the energy is directly transferred without the air-gap arc. In situations such as hand held systems, the ESD charge can be directly discharged to the equipment from a person already holding the equipment. The current is transferred on to the keypad or the serial port of the equipment directly and then travels through the PCB and finally to the IC. There are different methods of ESD testing applied: a) MIL-STD-883, Method 3015.7 b) IEC61000-4-2 Air-Discharge c) IEC61000-4-2 Direct Contact The Human Body Model has been the generally accepted ESD testing method for semiconductors. This method is also specified in MIL-STD-883, Method 3015.7 for ESD testing. The premise of this ESD test is to simulate the human body’s potential to store electro-static energy and discharge it to an integrated circuit. The simulation is performed by using a test model as shown in Figure 24. This method will test the IC’s capability to withstand an ESD transient during normal handling such as in manufacturing areas where the IC's tend to be handled frequently. The IEC-61000-4-2, formerly IEC801-2, is generally used for testing ESD on equipment and systems. For system manufacturers, they must guarantee a certain amount of ESD protection since the system itself is exposed to the outside environment and human presence. The premise with IEC61000-4-2 is that the system is required to withstand an amount of static electricity when ESD Figure 24. ESD Test Circuit for Human Body Model SP3223E/EB/EU_102_031920 15 Figure 25. ESD Test Circuit for IEC61000-4-2 i→ The circuit model in Figures 24 and 25 represent the typical ESD testing circuit used for all three methods. The CS is initially charged with the DC power supply when the first switch (SW1) is on. Now that the capacitor is charged, the second switch (SW2) is on while SW1 switches off. The voltage stored in the capacitor is then applied through RS, the current limiting resistor, onto the device under test (DUT). In ESD tests, the SW2 switch is pulsed so that the device under test receives a duration of voltage. 30A 15A 0A For the Human Body Model, the current limiting resistor (RS) and the source capacitor (CS) are 1.5kΩ an 100pF, respectively. For IEC-61000-4-2, the current limiting resistor (RS) and the source capacitor (CS) are 330Ω an 150pF, respectively. t=0ns t=30ns t→ Figure 26. ESD Test Waveform for IEC61000-4-2 The higher CS value and lower RS value in the IEC61000-4-2 model are more stringent than the Human Body Model. The larger storage capacitor injects a higher voltage to the test point when SW2 is switched on. The lower current limiting resistor increases the current charge onto the test point. DEVICE PIN TESTED Driver Outputs Receiver Inputs HUMAN BODY MODEL Air Discharge ±15kV ±15kV ±15kV ±15kV IEC61000-4-2 Direct Contact ±8kV ±8kV Level 4 4 Table 6. Transceiver ESD Tolerance Levels SP3223E/EB/EU_102_031920 16 PACKAGE: 20 Pin TSSOP SP3223E/EB/EU_102_031920 17 PACKAGE: 20 Pin SSOP SP3223E/EB/EU_102_031920 18 ORDERING INFORMATION(1) Part Number Temperature Range Package Packaging Method Lead-Free(2) -40°C to +85°C 20-pin TSSOP Tape and Reel Yes SP3223ECA-L/TR 0°C to +70°C 20-pin SSOP Tape and Reel Yes SP3223ECY-L 0°C to +70°C 20-pin TSSOP Tube Yes SP3223ECY-L/TR 0°C to +70°C 20-pin TSSOP Tape and Reel Yes SP3223EEA-L -40°C to +85°C 20-pin SSOP Tube Yes SP3223EEA-L/TR -40°C to +85°C 20-pin SSOP Tape and Reel Yes SP3223EEY-L -40°C to +85°C 20-pin TSSOP Tube Yes SP3223EEY-L/TR -40°C to +85°C 20-pin TSSOP Tape and Reel Yes -40°C to +85°C 20-pin TSSOP Tape and Reel Yes SP3223EB SP3223EBEY-L/TR SP3223E SP3223EU SP3223EUEY-L/TR NOTES: 1. Refer to www.maxlinear.com/SP3223EB, www.maxlinear.com/SP3223E, and www.maxlinear.com/SP3223EU for most up-to-date Ordering Information. 2. Visit www.maxlinear.com for additional information on Environmental Rating. PRODUCT NOMENCLATURE SP3223 E U EY L /TR Tape and Reel options “L” suffix indicates Lead Free packaging Package Type Part Number A= SSOP Y=TSSOP Temperature Range C= Commercial Range 0ºc to 70ºC E= Extended Range -40ºc to 85ºC Speed Indicator ESD Rating Blank= 120Kbps B= 250Kbps U= 1Mbps E= 15kV HBM and IEC 1000-4 SP3223E/EB/EU_102_031920 19 REVISION HISTORY DATE REVISION DESCRIPTION 10-06-06 --- Legacy Sipex data sheet Nov 2010 1.0.0 Convert to Exar data sheet format and remove EOL parts. June 2012 1.0.1 Correct type error on page 1 pin diagram. Pin 9 should be R2IN not R1IN, Change ESD protection levels to IEC61000-4-2. Mar 2020 1.0.2 Update to MaxLinear logo. Update Ordering Information. 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