SP3222E / SP3232E
True 3.0V to 5.5V RS-232 Transceivers
Description
FEATURES
■ Meets true EIA/TIA-232-F standards from
a 3.0V to 5.5V power supply
■ Minimum 120kbps data rate under full load
■ 1μA low power shutdown with receivers
active (SP3222E)
■ Interoperable with RS-232 down to a 2.7V
power source
■ Enhanced ESD specifications:
■ ±15kV Human Body Model
■ ±15kV IEC61000-4-2 Air Discharge
■ ±8kV IEC61000-4-2 Contact
Discharge
The SP3222E and SP3232E series are RS-232 transceiver solutions
intended for portable or hand-held applications such as notebook
or palmtop computers. The SP3222E / SP3232E series has a highefficiency, charge-pump power supply that requires only 0.1µF
capacitors in 3.3V operation. This charge pump allows the SP3222E
/ SP3232E series to deliver true RS-232 performance from a single
power supply ranging from 3.0V to 5.5V. The SP3222E / SP3232E
are 2-driver / 2-receiver devices. This series is ideal for portable or
hand-held applications such as notebook or palmtop computers. The
ESD tolerance of the SP3222E / SP3232E devices are over ±15kV
for both Human Body Model and IEC61000-4-2 Air discharge test
methods. The SP3222E device has a low-power shutdown mode
where the devices’ driver outputs and charge pumps are disabled.
During shutdown, the supply current falls to less than 1µA.
Ordering Information - Page 21
Typical Applications
VCC
VCC
C5
C1
C2
LOGIC
INPUTS
+
+
+
0.1µF
2 C1+
0.1µ F
C5
V+
6 C2-
SP3222E
SSOP
TSSOP
V-
*C3
13 T1IN
T1OUT
17
12 T2IN
T2OUT
8
R1IN
R2IN
C1
0.1µF
+
0.1µF
C2
RS-232
OUTPUTS
LOGIC
INPUTS
RS-232
INPUTS
LOGIC
OUTPUTS
9
+
+
+
0.1µF
2 C1+
0.1µF
V+
6 C2-
SP3222E
SOIC
18
V-
0.1µF
7
C4
T1OUT
15
11 T2IN
T2OUT
8
R1IN
14
R2IN
9
5kΩ
10 R2OUT
+
+
0.1µF
RS-232
OUTPUTS
RS-232
INPUTS
5kΩ
SHDN
GND
*C3
12 T1IN
5kΩ
1 EN
3
4 C15 C2+
0.1µF
17
VCC
13 R1OUT
16
5kΩ
10 R2OUT
+
7
C4
15 R1OUT
LOGIC
OUTPUTS
3
4 C15 C2+
0.1µF
19
VCC
20
1 EN
VCC
*can be returned to
either VCC or GND
C5
C1
C2
LOGIC
INPUTS
+
+
+
0.1µF
1 C1+
0.1µF
GND
16
VCC
V+
SP3232E
V-
*C3
C4
11 T1IN
T1OUT
14
10 T2IN
T2OUT
7
R1IN
13
R2IN
8
5kΩ
9 R2OUT
+
18
*can be returned to
either VCC or GND
0.1µF
6
5 C2-
12 R1OUT
LOGIC
OUTPUTS
16
2
3 C14 C2+
0.1µF
SHDN
+
0.1µF
RS-232
OUTPUTS
RS-232
INPUTS
5kΩ
GND
15
REV 1.0.3
*can be returned to
either VCC or GND
1/21
SP3222E / SP3232E
Absolute Maximum Ratings
These are stress ratings only and functional operation
of the device at these ratings or any other above those
indicated in the operation sections of the specifications
below is not implied. Exposure to absolute maximum
rating conditions for extended periods of time may affect
reliability and cause permanent damage to the device.
VCC..................................................................-0.3V to 6.0V
V+(1).................................................................-0.3V to 7.0V
V-(1)..................................................................0.3V to -7.0V
V+ + |V-|(1).......................................................................13V
ICC (DC VCC or GND current).................................±100mA
Short-Circuit Duration
TxOUT................................................................Continuous
Storage Temperature..................................-65˚C to +150˚C
Power Dissipation per package
20-pin SSOP (derate 9.25mW/°C above 70°C).......750mW
18-pin SOIC (derate 15.7mW/°C above 70°C).......1260mW
20-pin TSSOP (derate 11.1mW/°C above 70°C).....890mW
16-pin SSOP (derate 9.69mW/°C above 70°C).......775mW
16-pin PDIP (derate 14.3mW/°C above 70°C).......1150mW
16-pin WSOIC (derate 11.2mW/°C above 70°C).....900mW
Input Voltages
TxIN, EN, SHDN.................................-0.3V to (VCC + 0.3V)
RxIN.............................................................................±25V
Output Voltages
TxOUT......................................................................±13.2V
16-pin TSSOP (derate 10.5mW/°C above 70°C).....850mW
16-pin NSOIC (derate 13.57mW/°C above 70°C)..1086mW
NOTE:
1. V+ and V- can have maximum magnitudes of 7V, but their absolute differ-
ence cannot exceed 13V.
RxOUT...............................................-0.3V to (VCC + 0.3V)
Electrical Characteristics
Unless otherwise noted, the following specifications apply for VCC = 3.0V to 5.5V with TAMB = TMIN to TMAX, typical values
apply at VCC = 3.3V or 5.0V and TAMB = 25°C.
PARAMETERS
MIN.
TYP.
MAX.
UNITS
CONDITIONS
Supply current
0.3
1.0
mA
no load, VCC = 3.3V,
TAMB = 25oC, TxIN = GND or VCC
Shutdown supply current
1.0
10
µA
SHDN = GND, VCC = 3.3V,
TAMB = 25oC, TxIN = Vcc or GND
0.8
V
TxIN, EN, SHDN(2)
DC Characteristics
Logic Inputs and Receiver Outputs
Input logic threshold LOW
Input logic threshold HIGH
2.0
VCC
V
VCC = 3.3V(2)
Input logic threshold HIGH
2.4
VCC
V
VCC = 5.0V(2)
Input leakage current
+0.01
+1.0
µA
TxIN, EN, SHDN,
TAMB = 25oC, VIN = 0V to VCC
Output leakage current
+0.05
+10
µA
Receivers disabled, VOUT = 0V to VCC
0.4
Output voltage LOW
V
IOUT = 1.6mA
VCC - 0.6
VCC - 0.1
V
IOUT = -1.0mA
Output voltage swing
+5.0
+5.4
V
All driver outputs loaded with 3kΩ to GND,
TAMB = 25oC
Output resistance
300
Ω
VCC = V+ = V- = 0V, TOUT = +2V
Output voltage HIGH
Driver Outputs
Output short-circuit current
Output leakage current
+35
+60
mA
+25
µA
REV 1.0.3
VOUT = 0V
VCC = 0V or 3.0V to 5.5V,
VOUT = +12V, drivers disabled
2/21
SP3222E / SP3232E
Electrical Characteristics (Continued)
Unless otherwise noted, the following specifications apply for VCC = 3.0V to 5.5V with TAMB = TMIN to TMAX, typical values
apply at VCC = 3.3V or 5.0V and TAMB = 25°C.
PARAMETERS
MIN.
TYP.
MAX.
UNITS
15
V
CONDITIONS
Receiver Inputs
Input voltage range
-15
Input threshold LOW
0.6
1.2
V
VCC = 3.3V
Input threshold LOW
0.8
1.5
V
VCC = 5.0V
Input threshold HIGH
1.5
2.4
V
VCC = 3.3V
Input threshold HIGH
1.8
2.4
V
VCC = 5.0V
Input hysteresis
0.3
Input resistance
V
3
5
7
kΩ
120
235
kbps
Driver propagation delay, tPHL
1.0
µs
RL = 3kΩ, CL = 1000pF
Driver propagation delay, tPLH
1.0
µs
RL = 3kΩ, CL = 1000pF
Receiver propagation delay, tPHL
0.3
µs
Receiver input to receiver output, CL = 150pF
Receiver propagation delay, tPLH
0.3
µs
Receiver input to receiver output, CL = 150pF
Receiver output enable time
200
ns
Receiver output disable time
200
ns
Driver skew
100
500
ns
| tPHL - tPLH |, TAMB = 25°C
Receiver skew
200
1000
ns
| tPHL - tPLH |
30
V/µs
Timing Characteristics
Maximum data rate
Transition-region slew rate
RL = 3kΩ, CL = 1000pF, one driver switching
VCC = 3.3V, RL = 3kΩ, CL = 1000pF,
TAMB = 25°C, measurements taken from
-3.0V to 3.0V or 3.0V to -3.0V
NOTE:
2. Driver input hysteresis is typically 250mV.
REV 1.0.3
3/21
SP3222E / SP3232E
Typical Performance Characteristics
Unless otherwise noted, the following performance characteristics apply for VCC = 3.3V, 120kbps data rate, all drivers
loaded with 3kΩ, 0.1µF charge pump capacitors, and TAMB = 25°C.
14
12
4
10
Vout+
Vout-
2
Slew Rate [V /µs ]
Transmitter Output Voltage [V]
6
0
0
500
1000
1500
2000
-2
6
4
+Slew
-Slew
2
-4
-6
8
0
Load Capacitance [pF]
Figure 1: Transmitter Output Voltage vs Load Capacitance
for the SP3222E and SP3232E
0
500
1000
1500
Load Capacitance [pF]
2000
2330
Figure 2: Slew Rate vs Load Capacitance
for the SP3222E and SP3232E
50
118KHz
60KHz
10KHz
45
40
Suppl y Current [mA]
35
30
25
20
15
10
5
0
0
500
1000
1500
2000
2330
Load Capacitance [pF]
Figure 3: Supply Current VS. Load Capacitance
when Transmitting Data
REV 1.0.3
4/21
SP3222E / SP3232E
Pin Functions
Pin Number
Pin Name
SP3222E
Pin Function / Description
SOIC
SSOP
TSSOP
SP3232E
EN
Receiver Enable. Apply logic LOW for normal operation.
Apply logic HIGH to disable the receiver outputs (high-Z state).
1
1
-
C1+
Positive terminal of the voltage doubler charge-pump capacitor
2
2
1
V+
5.5V output generated by the charge pump
3
3
2
C1-
Negative terminal of the voltage doubler charge-pump capacitor
4
4
3
C2+
Positive terminal of the inverting charge-pump capacitor
5
5
4
C2-
Negative terminal of the inverting charge-pump capacitor
6
6
5
-5.5V output generated by the charge pump
7
7
6
T1OUT
V-
RS-232 driver output
15
17
14
T2OUT
RS-232 driver output
8
8
7
R1IN
RS-232 receiver input
14
16
13
R2IN
RS-232 receiver input
9
9
8
R1OUT
TTL/CMOS receiver output
13
15
12
R2OUT
TTL/CMOS receiver output
10
10
9
T1IN
TTL/CMOS driver input
12
13
11
T2IN
TTL/CMOS driver input
11
12
10
GND
Ground
16
18
15
VCC
3.0V to 5.5V supply voltage
17
19
16
Shutdown Control Input. Drive HIGH for normal device operation.
Drive LOW to shutdown the drivers (high-Z output) and the on-board power supply.
18
20
-
-
11, 14
-
SHDN
N.C.
No connect
Table 1: Device Pin Description
REV 1.0.3
5/21
SP3222E / SP3232E
Pinouts
EN
EN
20 SHDN
1
C1+ 2
18 SHDN
1
C1+ 2
19 VCC
17 VCC
V+
3
16 GND
T1OUT
C1-
4
15
T1OUT
R1IN
C2+
5
14
R1IN
C2-
6
13 R1OUT
N.C.
V-
7
12 T1IN
8
13 T1IN
T2OUT
8
11 T2IN
9
12 T2IN
R2IN
9
10
V+
3
18 GND
C1-
4
17
C2+
5
16
C2-
6
15 R1OUT
V-
7
14
T2OUT
R2IN
R2OUT 10
SP3222E
11
SP3222E
R2OUT
N.C.
SOIC
SSOP/TSSOP
Figure 4: Pinout Configurations for the SP3222E
16 VCC
C1+ 1
V+ 2
15 GND
C1-
3
C2+
4
C2-
5
12 R1OUT
V-
6
11 T1IN
T2OUT
7
10
R2IN
8
9
14 T1OUT
SP3232E
13 R1IN
T2IN
R2OUT
Figure 5: Pinout Configurations for the SP3232E
REV 1.0.3
6/21
SP3222E / SP3232E
Typical Operating Circuits
VCC
VCC
C5
C1
C2
LOGIC
INPUTS
+
+
+
0.1µF
2 C1+
0.1µ F
6 C2-
V+
SP3222E
SSOP
TSSOP
3
*C3
C4
13 T1IN
T1OUT
17
12 T2IN
T2OUT
8
R1IN
+
C1
0.1µF
R2IN
+
0.1µF
+
C2
2 C1+
0.1µF
9
V+
0.1µF
SP3222E
SOIC
6 C2-
*C3
C4
T1OUT
15
11 T2IN
T2OUT
8
R1IN
10 R2OUT
R2IN
0.1µF
+
0.1µF
RS-232
OUTPUTS
14
5kΩ
LOGIC
OUTPUTS
+
7
12 T1IN
9
RS-232
INPUTS
5kΩ
5kΩ
1 EN
V-
13 R1OUT
RS-232
INPUTS
3
4 C15 C2+
LOGIC
INPUTS
RS-232
OUTPUTS
17
VCC
0.1µF
16
5kΩ
10 R2OUT
+
7
V-
15 R1OUT
LOGIC
OUTPUTS
+
C5
4 C15 C2+
0.1µF
19
VCC
SHDN
GND
1 EN
20
SHDN
GND
*can be returned to
either VCC or GND
18
16
18
*can be returned to
either VCC or GND
Figure 6: SP3222E Typical Operating Circuits
VCC
+
C5
+
C1
+
C2
LOGIC
INPUTS
0.1µF
1 C1+
0.1µF
V+
SP3232E
V-
*C3
C4
11 T1IN
T1OUT
14
10 T2IN
T2OUT
7
R1IN
R2IN
0.1µF
+
0.1µF
RS-232
OUTPUTS
13
5kΩ
9 R2OUT
+
6
5 C2-
12 R1OUT
LOGIC
OUTPUTS
2
3 C14 C2+
0.1µF
16
VCC
8
RS-232
INPUTS
5kΩ
GND
15
*can be returned to
either VCC or GND
Figure 7: SP3232E Typical Operating Circuit
REV 1.0.3
7/21
SP3222E / SP3232E
Applications Information
Figure 10 shows the test results where one driver
was active at 235kbps and all drivers loaded with an
RS-232 receiver in parallel with 1000pF capacitors. A
solid RS-232 data transmission rate of 120kbps provides
compatibility with many designs in personal computer
peripherals and LAN applications.
The
SP3222E / SP3232E transceivers meet the
EIA/TIA-232 and ITU-T V.28/V.24 communication protocols
and can be implemented in battery-powered, portable,
or hand-held applications such as notebook or palmtop
computers. The SP3222E / SP3232E devices feature
MaxLinear’s proprietary on-board charge pump circuitry
that generates 5.5V for RS-232 voltage levels from a single
3.0V to 5.5V power supply. This series is ideal for 3.3V-only
systems, mixed 3.3V to 5.5V systems, or 5.0V-only systems
that require true RS-232 performance. The SP3222E
/ SP3232E devices can operate at a typical data rate of
235kbps when fully loaded.
VCC
+
C5
The SP3222E and SP3232E are 2-driver / 2-receiver
devices ideal for portable or hand-held applications. The
SP3222E features a 1µA shutdown mode that reduces
power consumption and extends battery life in portable
systems. Its receivers remain active in shutdown mode,
allowing external devices such as modems to be monitored
using only 1µA supply current.
+
C1
0.1µF
VCC
C1+
+
C2
V+
C3
C1C2+
0.1µF
SP3222E
SP3232E
LOGIC
OUTPUTS
0.1µF
C4
+
0.1µF
TxOUT
TxIN
RxIN
RxOUT
5kΩ
EN*
1. Drivers
+
V-
C2LOGIC
INPUTS
Theory of Operation
The SP3222E/SP3232E series is made up of three basic
circuit blocks:
0.1µF
2. Receivers
VCC
*SHDN
GND
3. The MaxLinear proprietary charge pump
1000pF
* SP3222E only
Drivers
The drivers are inverting level transmitters that convert
TTL or CMOS logic levels to 5.0V EIA/TIA-232 levels
with an inverted sense relative to the input logic levels.
Typically, the RS-232 output voltage swing is 5.4V with
no load and 5V minimum fully loaded. The driver outputs
are protected against infinite short-circuits to ground
without degradation in reliability. Driver outputs will meet
EIA/TIA-562 levels of ±3.7V with supply voltages as low
as 2.7V.
The drivers can guarantee a data rate of 120kbps fully
loaded with 3kΩ in parallel with 1000pF, ensuring
compatability with PC-to-PC communication software.
The slew rate of the driver is internally limited to a maximum
of 30V/µs in order to meet the EIA standards (EIA
RS-232D 2.1.7, Paragraph 5). The transition of the loaded
output from HIGH to LOW also meet the monotonicity
requirements of the standard.
Figure 8: SP3222E/SP3232E Driver Loopback Test Circuit
[
T1 IN 1
T
]
T
T1 OUT 2
T
T
R1 OUT 3
Figure 8 shows a loopback test circuit used to test the
RS-232 Drivers. Figure 9 shows the test results of the
loopback circuit with all drivers active at 120kbps with
RS-232 loads in parallel with a 1000pF capacitor.
REV 1.0.3
Ch1 5.00V Ch2 5.00V M 5.00µs
Ch3 5.00V
Ch1
0V
Figure 9: Loopback Test results at 120kbps
8/21
SP3222E / SP3232E
Applications Information (Continued)
[
T
Since receiver input is usually from a transmission line
where long cable lengths and system interference can
degrade the signal, the inputs have a typical hysteresis
margin of 300mV. This ensures that the receiver is
virtually immune to noisy transmission lines. Should
an input be left unconnected, an internal 5kΩ pulldown
resistor to ground will commit the output of the receiver to
a HIGH state.
]
T
T1 IN 1
T1 OUT 2
T
T
Charge Pump
R1 OUT 3
Ch1 5.00V Ch2 5.00V M 2.50µs Ch1
Ch3 5.00V
0V
Figure 10: Loopback Test results at 235kbps
The SP3222E driver’s output stages are turned off (tristate) when the device is in shutdown mode. When the
power is off, the SP3222E device permits the outputs to
be driven up to ±12V. The driver’s inputs do not have pullup resistors. Designers should connect unused inputs to
VCC or GND.
In the shutdown mode, the supply current falls to less than
1µA, where SHDN = LOW. When the SP3222E device is
shut down, the device’s driver outputs are disabled (tristated) and the charge pumps are turned off with V+ pulled
down to VCC and V- pulled to GND. The time required to
exit shutdown is typically 100µs. Connect SHDN to VCC if
the shutdown mode is not used.
Receivers
The Receivers convert EIA/TIA-232 levels to TTL or
CMOS logic output levels. The SP3222E receivers have
an inverting tri-state output. These receiver outputs
(RxOUT) are tri-stated when the enable control EN =
HIGH. In the shutdown mode, the receivers can be active
or inactive. EN has no effect on TxOUT. The truth table
logic of the SP3222E driver and receiver outputs can be
found in Table 2.
SHDN
EN
TxOUT
RxOUT
0
0
Tri-state
Active
0
1
Tri-state
Tri-state
1
0
Active
Active
1
1
Active
Tri-state
The charge pump is an MaxLinear-patended design (U.S.
5,306,954) and uses a unique approach compared to older
less-efficient designs. The charge pump still requires four
external capacitors, but uses a four-phase voltage shifting
technique to attain symmetrical 5.5V power supplies. The
internal power supply consists of a regulated dual charge
pump that provides output voltages of ±5.5V regardless
of the input voltage (VCC) over the 3.0V to 5.5V range.
In most circumstances, decoupling the power supply can
be achieved adequately using a 0.1µF bypass capacitor
at C5 (refer to figures 6 and 7). In applications that are
sensitive to power-supply noise, decouple Vcc to ground
with a capacitor of the same value as charge-pump
capacitor C1. Physically connect bypass capcitors as
close to the IC as possible.
The charge pump operates in a discontinuous mode
using an internal oscillator. If the output voltages are less
than a magnitude of 5.5V, the charge pump is enabled.
If the output voltages exceed a magnitude of 5.5V, the
charge pump is disabled. This oscillator controls the
four phases of the voltage shifting. A description of each
phase follows.
Phase 1: VSS charge storage
During this phase of the clock cycle, the positive side of
capacitors C1 and C2 are initially charged to VCC. Cl+ is
then switched to GND and the charge in C1– is transferred
to C2–. Since C2+ is connected to VCC, the voltage
potential across capacitor C2 is now 2 times VCC.
Phase 2: VSS transfer
Phase two of the clock connects the negative terminal
of C2 to the VSS storage capacitor and the positive
terminal of C2 to GND. This transfers a negative
generated voltage to C3. This generated voltage is
regulated to a minimum voltage of -5.5V.
Simultaneous with the transfer of the voltage to C3, the
positive side of capacitor C1 is switched to VCC and the
negative side is connected to GND.
Table 2: SP3222E Truth Table Logic
for Shutdown and Enable Control
REV 1.0.3
9/21
SP3222E / SP3232E
Applications Information (Continued)
Phase 3: VDD charge storage
[
The third phase of the clock is identical to the first phase;
the charge transferred in C1 produces –VCC in the
negative terminal of C1, which is applied to the negative
side of capacitor C2. Since C2+ is at VCC, the voltage
potential across C2 is 2 times VCC.
+6V
a) C2+
T
GND 1
The fourth phase of the clock connects the negative
terminal of C2 to GND, and transfers this positive
generated voltage across C2 to C4, the VDD storage
capacitor.
This voltage is regulated to 5.5V.
At
this voltage, the internal oscillator is disabled.
Simultaneous with the transfer of the voltage to C4, the
positive side of capacitor C1 is switched to VCC and the
negative side is connected to GND, allowing the charge pump
cycle to begin again. The charge pump cycle will continue
as long as the operational conditions for the internal
oscillator are present.
Since both V+ and V– are separately generated from VCC,
in a no–load condition V+ and V– will be symmetrical.
Older charge pump approaches that generate V– from V+
will show a decrease in the magnitude of V– compared to
V+ due to the inherent inefficiencies in the design.
b) C2-6V
T
Ch1 2.00V Ch2 2.00V M 1.00µs Ch1 5.48V
Figure 13: Charge Pump Waveforms
VCC = +5V
+5V
C1
+
–5V
+
–
C4
+
–
VDD Storage Capacitor
–
+
VSS Storage Capacitor
C3
–5V
Figure 14: Charge Pump - Phase 3
VCC = +5V
VCC = +5V
+5V
C2
–
C2
–
The clock rate for the charge pump typically operates at
greater than 250kHz. The external capacitors can be as
low as 0.1µF with a 16V breakdown voltage rating.
+
]
GND 2
Phase 4: VDD transfer
C1
T
–5V
+
–
C4
+
+5.5V
–
+
–
VDD Storage Capacitor
VSS Storage Capacitor
C3
–5V
C1
+
–
C2
+
–
C4
+
–
–
+
VDD Storage Capacitor
VSS Storage Capacitor
C3
Figure 11: Charge Pump - Phase 1
Figure 15: Charge Pump - Phase 4
VCC = +5V
C4
C1
+
–
C2
+
–
-5.5V
+
–
–
+
VDD Storage Capacitor
VSS Storage Capacitor
C3
Figure 12: Charge Pump - Phase 2
REV 1.0.3
10/21
SP3222E / SP3232E
ESD Tolerance
The SP3222E / SP3232E Series incorporates ruggedized
ESD cells on all driver output and receiver input pins. The
ESD structure is improved over our previous family for more
rugged applications and environments sensitive to electrostatic discharges and associated transients. The improved
ESD tolerance is at least ±15kV without damage or latchup.
There are different methods of ESD testing applied:
a) MIL-STD-883, Method 3015.7
b) IEC61000-4-2 Air-Discharge
c) IEC61000-4-2 Direct Contact
The Human Body Model has been the generally accepted
ESD testing method for semiconductors. This method is
also specified in MIL-STD-883, Method 3015.7 for ESD
testing. The premise of this ESD test is to simulate the
human body’s potential to store electro-static energy and
discharge it to an integrated circuit. The simulation is
performed by using a test model as shown in Figure 16.
This method will test the IC’s capability to withstand an ESD
transient during normal handling such as in manufacturing
areas where the IC’s tend to be handled frequently.
The IEC61000-4-2, formerly IEC801-2, is generally used
for testing ESD on equipment and systems. For system
manufacturers, they must guarantee a certain amount of
ESD protection since the system itself is exposed to the
outside environment and human presence. The premise
with IEC61000-4-2 is that the system is required to withstand
an amount of static electricity when ESD is applied to
points and surfaces of the equipment that are accessible
to personnel during normal usage. The transceiver IC
receives most of the ESD current when the ESD source
is applied to the connector pins. The test circuit for
IEC61000-4-2 is shown on Figure 17. There are two
methods within IEC61000-4-2, the Air Discharge method
and the Contact Discharge method.
RS
RC
SW1
SW2
Device
Under
Test
CS
DC Power
Source
Figure 16: ESD Test Circuit for Human Body Model
Contact-Discharge Model
RS
RC
RV
SW1
DC Power
Source
SW2
Device
Under
Test
CS
R S and RV add up to 330Ω for IEC61000-4-2.
Figure 17: ESD Test Circuit for IEC61000-4-2
REV 1.0.3
11/21
SP3222E / SP3232E
I→
ESD Tolerance (Continued)
With the Air Discharge Method, an ESD voltage is applied to
the equipment under test (EUT) through air. This simulates
an electrically charged person ready to connect a cable onto
the rear of the system only to find an unpleasant zap just
before the person touches the back panel. The high energy
potential on the person discharges through an arcing path to
the rear panel of the system before he or she even touches
the system. This energy, whether discharged directly or
through air, is predominantly a function of the discharge
current rather than the discharge voltage. Variables with an
air discharge such as approach speed of the object carrying
the ESD potential to the system and humidity will tend to
change the discharge current. For example, the rise time of
the discharge current varies with the approach speed.
The Contact Discharge Method applies the ESD current
directly to the EUT. This method was devised to reduce
the unpredictability of the ESD arc. The discharge current
rise time is constant since the energy is directly transferred
without the air-gap arc. In situations such as hand held
systems, the ESD charge can be directly discharged to the
equipment from a person already holding the equipment.
The current is transferred on to the keypad or the serial port
of the equipment directly and then travels through the PCB
and finally to the IC.
The circuit model in Figures 16 and 17 represent the typical
ESD testing circuit used for all three methods. The CS is
initially charged with the DC power supply when the first
switch (SW1) is on. Now that the capacitor is charged,
the second switch (SW2) is on while SW1 switches off.
The voltage stored in the capacitor is then applied through
RS, the current limiting resistor, onto the device under test
(DUT). In ESD tests, the SW2 switch is pulsed so that the
device under test receives a duration of voltage.
DEVICE PIN TESTED
HUMAN BODY MODEL
Driver Outputs
Receiver Inputs
30A
15A
0A
t = 0ns
t→
t = 30ns
Figure 18: ESD Test Waveform for IEC61000-4-2
For the Human Body Model, the current limiting resistor
(RS) and the source capacitor (CS) are 1.5kΩ an 100pF,
respectively.
For IEC-61000-4-2, the current limiting
resistor (RS) and the source capacitor (CS) are 330Ω an
150pF, respectively.
The higher CS value and lower RS value in the IEC610004-2 model are more stringent than the Human Body Model.
The larger storage capacitor injects a higher voltage to the
test point when SW2 is switched on. The lower current
limiting resistor increases the current charge onto the test
point.
IEC61000-4-2
Air Discharge
Direct Contact
Level
±15kV
±15kV
±8kV
4
±15kV
±15kV
±8kV
4
Table 3: Transceiver ESD Tolerance Levels
REV 1.0.3
12/21
SP3222E / SP3232E
Mechanical Dimensions
SSOP20
Top View
Front View
Side View
REV 1.0.3
Drawing No:
POD-00000119
Revision:
A
13/21
SP3222E / SP3232E
Mechanical Dimensions
SSOP16
Top View
Side View
Front View
REV 1.0.3
Drawing No:
POD-00000116
Revision:
A
14/21
SP3222E / SP3232E
Mechanical Dimensions
WSOIC16
Top View
Side View
Front View
Drawing No: POD-00000115
Revision:
REV 1.0.3
B
15/21
SP3222E / SP3232E
Mechanical Dimensions
WSOIC18
Top View
Side View
Front View
Drawing No: POD-00000118
Revision:
REV 1.0.3
B
16/21
SP3222E / SP3232E
Mechanical Dimensions
NSOIC16
Top View
Front View
Side View
REV 1.0.3
Drawing No:
POD-00000114
Revision:
A
17/21
SP3222E / SP3232E
Mechanical Dimensions
TSSOP16
Top View
Front View
Side View
POD-00000117
Drawing No:
Revision:
REV 1.0.3
A
18/21
SP3222E / SP3232E
Mechanical Dimensions
TSSOP20
Top View
Side View
Front View
REV 1.0.3
Drawing No:
POD-00000120
Revision:
A
19/21
SP3222E / SP3232E
Ordering Information(1)
Part Number
Operating Temperature Range
Package
Packaging Method
Lead-Free(2)
SP3222ECA-L/TR
0°C to +70°C
20 Pin SSOP
Reel
Yes
SP3222ECT-L/TR
0°C to +70°C
18 Pin WSOIC
Reel
Yes
SP3222ECY-L/TR
0°C to +70°C
20 Pin TSSOP
Reel
Yes
SP3222EEA-L/TR
-40°C to +85°C
20 Pin SSOP
Reel
Yes
SP3222EEY-L/TR
-40°C to +85°C
20 Pin TSSOP
Reel
Yes
SP3232ECA-L
0°C to +70°C
16 Pin SSOP
Tube
Yes
SP3232ECA-L/TR
0°C to +70°C
16 Pin SSOP
Reel
Yes
SP3232ECN-L
0°C to +70°C
16 Pin NSOIC
Tube
Yes
SP3232ECN-L/TR
0°C to +70°C
16 Pin NSOIC
Reel
Yes
SP3232ECT-L/TR
0°C to +70°C
16 Pin WSOIC
Reel
Yes
SP3232ECY-L
0°C to +70°C
16 Pin TSSOP
Tube
Yes
SP3232ECY-L/TR
0°C to +70°C
16 Pin TSSOP
Reel
Yes
SP3232EEA-L
-40°C to +85°C
16 Pin SSOP
Tube
Yes
SP3232EEA-L/TR
-40°C to +85°C
16 Pin SSOP
Reel
Yes
SP3232EEN-L
-40°C to +85°C
16 Pin NSOIC
Tube
Yes
SP3232EEN-L/TR
-40°C to +85°C
16 Pin NSOIC
Reel
Yes
SP3232EET-L
-40°C to +85°C
16 Pin WSOIC
Tube
Yes
SP3232EET-L/TR
-40°C to +85°C
16 Pin WSOIC
Reel
Yes
SP3232EEY-L
-40°C to +85°C
16 Pin TSSOP
Tube
Yes
SP3232EEY-L/TR
-40°C to +85°C
16 Pin TSSOP
Reel
Yes
SP3222E
SP3232E
NOTE:
1. Refer to www.maxlinear.com/SP3222E and www.maxlinear.com/SP3232E for most up-to-date Ordering Information.
2. Visit www.maxlinear.com for additional information on Environmental Rating.
Selection Table
MODEL
Power Supplies
RS-232
Drivers
RS-232
Receivers
External
Components
Shutdown
TTL 3-State
# of Pins
SP3222E
+3.0V to +5.5V
2
2
4 Capacitors
Yes
Yes
18, 20
SP3232E
+3.0V to +5.5V
2
2
4 Capacitors
No
No
16
REV 1.0.3
20/21
SP3222E / SP3232E
Revision History
Revision
Date
Description
08/22/05
--
12/08/10
1.0.0
Convert to Exar Format and update ordering information.
03/14/13
1.0.1
Correct type error to driver Transition-Region Slew Rate
conditions.
10/16/17
1.0.2
Correct SP3222E nSOIC pinout to SOIC. Updated to MaxLinear logo. Updated format and ordering information table.
04/22/20
1.0.3
Change RxIN absolute maximum from ±15V to ±25V. Update Ordering
Information.
Legacy Sipex Datasheet
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Suite 100
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Tel.:+1 (760) 692-0711
Fax: +1 (760) 444-8598
www.maxlinear.com
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