SP508E
Rugged 20Mbps, 8 Channel Multi-Protocol Transceiver
with Programmable DCE/DTE and Termination Resistors
FEATURES
• 20Mbps Differential Transmission Rates
• 15kV ESD Tolerance for Analog I/Os
• Internal Transceiver Termination Resistors
for V.11/V.35
• Interface Modes:
– RS-232 (V.28)
– X.21 (V.11)
– RS-449/V.36
(V.10 & V.11)
Now Available in Lead Free Packaging
Refer to page 7 for pinout
• Easy Flow-Through Pinout
• +5V Only Operation
• Individual Driver/Receiver Enable/Disable Controls
• Operates in DTE or DCE Mode
– EIA-530 (V.10 & V.11)
– EIA-530A (V.10 & V.11)
– V.35
APPLICATIONS
• Router
• Software Selectable Protocols with 3-Bit Word
• Frame Relay
• Eight Drivers and Eight Receivers
• CSU
• V.35/V.11 Receiver Termination Network
• DSU
Disable Option
• PBX
• Internal Line or Digital Loopback Testing
• Adheres to NET1/NET2 and TBR-2 Requirements • Secure Communication Terminals
DESCRIPTION
The SP508E is a monolithic device that supports eight (8) popular serial interface standards
for Wide Area Network (WAN) connectivity. The SP508E is fabricated using a low power
BiCMOS process technology, and incorporates an Exar regulated charge pump allowing +5V
only operation. Exar's patented charge pump provides a regulated output of +5.8V, which
will provide enough voltage for compliant operation in all modes. Eight (8) drivers and eight
(8) receivers can be configured via software for any of the above interface modes at any
time. The SP508E requires no additional external components for compliant operation for
all of the eight (8) modes of operation other than four capacitors used for the internal charge
pump. All necessary termination is integrated within the SP508E and is switchable when
V.35 drivers and V.35 receivers, or when V.11 receivers are used. The SP508E provides the
controls and transceiver availability for operating as either a DTE or DCE.
Additional features with the SP508E include internal loopback that can be initiated in any
of the operating modes by use of the LOOPBACK pin. While in loopback mode, receiver
outputs are internally connected to driver inputs creating an internal signal path bypassing
the serial communications controller for diagnostic testing. The SP508E also includes a latch
enable pin with the driver and receiver address decoder. The internal V.11 or V.35 receiver
termination can be switched off using a control pin (TERM_OFF) for monitoring applications.
All eight (8) drivers and receivers in the SP508E include separate enable pins for added
convenience. The SP508E is ideal for WAN serial ports in networking equipment such as
routers, access concentrators, network muxes, DSU/CSU's, networking test equipment, and
other access devices.
Applicable U.S. Patents-5,306,954; and others patents pending
SP508E_101_013020
1
STORAGE CONSIDERATIONS
ABSOLUTE MAXIMUM RATINGS
Due to the relatively large package size, storage in a low
humidity environment is preferred. Large high density plastic
packages are moisture sensitive and should be stored in Dry
Vapor Barrier Bags. Prior to usage, the parts should remain
bagged and stored below 40°C and 60%RH. If the parts are
removed from the bag, they should be used within 48 hours
or stored in an environment at or below 20%RH. If the above
conditions cannot be followed, the parts should be baked
for four hours at 125°C in order to remove moisture prior to
soldering. Exar ships the 100-pin LQFP in Dry Vapor Barrier
Bags with a humidity indicator card and desiccant pack. The
humidity indicator should be below 30%RH.
These are stress ratings only and functional operation of the
device at these ratings or any other above those indicated in
the operation sections of the specifications below is not implied.
Exposure to absolute maximum rating conditions for extended
periods of time may affect reliability.
VCC ..................................................................................................+7V
Input Voltages:
Logic................................................. -0.3V to (VCC+0.5V)
Drivers............................................... -0.3V to (VCC+0.5V)
Receivers..............................................................±15.5V
Output Voltages:
Logic................................................. -0.3V to (VCC+0.5V)
Drivers ....................................................-7.5V to +12.5V
Receivers.......................................... -0.3V to (VCC+0.5V)
Storage Temperature...................................................-65°C to +150°C
Power Dissipation....................................................................1520mW
(derate 19.0mW/°C above +70°C)
Package Derating:
øJA....................................................................52.7 °C/W
øJC......................................................................6.5 °C/W
ELECTRICAL SPECIFICATIONS
TA = -40°C to +85°C and VCC = +4.75V to +5.25V unless otherwise noted. Typical values are for TA = 25C and Vcc = 5V.
PARAMETER
LOGIC INPUTS
MIN.
TYP.
MAX.
UNITS
VIL
0.8
VIH
2.0
Volts
Volts
VOL
0.4
VOH
2.4
Volts
Volts
LOGIC OUTPUTS
V.28 DRIVER
CONDITIONS
IOUT= –3.2mA
IOUT= 1.0mA
DC Parameters
Outputs
Open Circuit Voltage
±15
Volts per Figure 1
Loaded Voltage
±5.0
±15
Volts per Figure 2
Short-Circuit Current
±100
mA per Figure 4, VOUT=0V
Power-Off Impedance
300
Ω per Figure 5
AC Parameters
Outputs
Transition Time
1.5
µs per Figure 6; +3V to -3V
Instantaneous Slew Rate
30
V/µs per Figure 3
Propagation Delay
tPHL
0.5
1
5
µs
tPLH
0.5
1
5
µs
Max.Transmission Rate
120
230
kbps
V.28 RECEIVER
DC Parameters
Inputs
Input Impedance
3
7
kΩ per Figure 7
Open-Circuit Bias
+2.0
Volts per Figure 8
HIGH Threshold
1.7
3.0
Volts
LOW Threshold
0.8
1.2
Volts
AC Parameters
Propagation Delay
tPHL
50
100
500
ns
tPLH
50
100
500
ns
SP508E_101_013020
2
ELECTRICAL SPECIFICATIONS
TA = -40°C to +85°C and VCC = +4.75V to +5.25V unless otherwise noted. Typical values are for TA = 25C and Vcc = 5V
PARAMETER
V.28 RECEIVER (cont)
AC Parameters (cont.)
Max.Transmission Rate
MIN. TYP. MAX.
120
235
UNITS
CONDITIONS
kbps
V.10 DRIVER
DC Parameters
Outputs
Open Circuit Voltage
±4.0
±6.0
Volts
per Figure 9
Test-Terminated Voltage
0.9VOC
Volts
per Figure 10
Short-Circuit Current
±150
mA
per Figure 11
Power-Off Current
±100
µA
per Figure 12
AC Parameters
Outputs
Transition Time
500
ns
per Figure 13; 10% to 90%
Propagation Delay
tPHL
30
100
500
ns
tPLH
30
100
500
ns
Max.Transmission Rate
120
kbps
V.10 RECEIVER
DC Parameters
Inputs
Input Current
–3.25
+3.25
mA
per Figures 14 and 15
Input Impedance
4
kΩ
Sensitivity
±0.3
Volts
AC Parameters
Propagation Delay
tPHL
500
ns
tPLH
500
ns
Max.Transmission Rate
120
kbps
V.11 DRIVER
DC Parameters
Outputs
Open Circuit Voltage
±6.0
Volts
per Figure 16
Test Terminated Voltage
±2.0
Volts
per Figure 17
0.5VOC
0.67VOC
Volts
Balance
±0.4
Volts
per Figure 17
Offset
+3.0
Volts
per Figure 17
Short-Circuit Current
±150
mA
per Figure 18
Power-Off Current
±100
µA
per Figure 19
AC Parameters
Outputs
Transition Time
10
ns
per Fig. 21 and 36; 10% to 90%
Propagation Delay
Using CL = 50pF;
tPHL
30
85
ns
per Figures 33 and 36
tPLH
30
85
ns
per Figures 33 and 36
Differential Skew
5
10
ns
per Figures 33 and 36
(|tphl -tplh|)
Max.Transmission Rate
20
Mbps
Channel to Channel Skew
2
ns
V.11 RECEIVER
DC Parameters
Inputs
Common Mode Range
–7
+7
Volts
Sensitivity
±0.2
Volts
SP508E_101_013020
3
ELECTRICAL SPECIFICATIONS
TA = -40°C to +85°C and VCC = +4.75V to +5.25V unless otherwise noted. Typical values are for TA = 25C and Vcc = 5V
PARAMETER
MIN.
TYP.
MAX.
UNITS
CONDITIONS
V.11 RECEIVER (cont)
DC Parameters (cont.)
Input Current
–3.25
±3.25
mA per Figure 20 and 22;
power on or off
Current w/ 100Ω Termination
±60.75
mA per Figure 23 and 24
Input Impedance
4
kΩ
AC Parameters
Propagation Delay Using CL = 50pF;
tPHL
30
85
ns per Figures 33 and 38
tPLH
30
85
ns per Figures 33 and 38
Skew(|tphl-tplh|)
5
10
ns per Figure 33
Max.Transmission Rate
20
Mbps
Channel to Channel Skew
2
ns
V.35 DRIVER
DC Parameters
Outputs
Test Terminated Voltage
±0.44
±0.66
Volts per Figure 25
Offset
±0.6
Volts per Figure 25
Output Overshoot
-0.2VST
+0.2VST
Volts per Figure 25; VST = Steady state value
Source Impedance
50
150
Ω per Figure 27; ZS = V2/V1 x 50
Short-Circuit Impedance
135
165
Ω per Figure 28
AC Parameters
Outputs
Transition Time
7
20
ns per Figure 29; 10% to 90%
Propagation Delay
tPHL
30
85
ns per Figure 33 and 36; CL = 20pF
tPLH
30
85
ns per Figure 33 and 36; CL = 20pF
Differential Skew
5
10
ns per Figure 33 and 36; CL = 20pF
(|tphl-tplh|)
Max.Transmission Rate
20
Mbps
Channel to Channel Skew
2
ns
V.35 RECEIVER
DC Parameters
Inputs
Sensitivity
±50
+200
mV
Source Impedance
90
110
Ω per Figure 30; ZS = V2/V1 x 50Ω
Short-Circuit Impedance
135
165
Ω per Figure 31
AC Parameters
Propagation Delay
tPHL
30
85
ns per Figure 33 and 38; CL = 20pF
tPLH
30
85
ns per Figure 33 and 38; CL = 20pF
Skew(|tphl-tplh|)
5
10
ns per Figure 33; CL = 20pF
Max.Transmission Rate
20
Mbps
Channel to Channel Skew
2
ns
TRANSCEIVER LEAKAGE CURRENT
Driver Output 3-State Current
Rcvr Output 3-State Current
POWER REQUIREMENTS
VCC
4.75
ICC (Shutdown Mode)
(V.28/RS-232)
(V.11/RS-422)
(EIA-530 & RS-449)
(V.35)
(EIA-530A)
500
1
10
5.00
5.25
200
95
230
270
170
200
µA
µA
Volts
µA
mA
mA
mA
mA
mA
per Figure 32; Drivers disabled
TX & RX disabled, 0.4V - VO - 2.4V
All ICC values are with VCC = +5V
fIN = 120kbps; Drivers active & loaded
fIN = 10Mbps; Drivers active & loaded
fIN = 10Mbps; Drivers active & loade
V.35 @ fIN = 10Mbps, V.28 @ 20kbps
fIN = 10Mbps; Drivers active & loaded
SP508E_101_013020
4
OTHER AC CHARACTERISTICS
TA = -40°C to +85°C and VCC = +4.75V to +5.25V unless otherwise noted. Typical values are for TA = 25C and Vcc = 5V.
PARAMETER
MIN.
TYP.
MAX. UNITS
CONDITIONS
DRIVER DELAY TIME BETWEEN ACTIVE MODE AND TRI-STATE MODE
RS-232/V.28
tPZL; Tri-state to Output LOW
tPZH; Tri-state to Output HIGH
tPLZ; Output LOW to Tri-state
tPHZ; Output HIGH to Tri-state
RS-423/V.10
tPZL; Tri-state to Output LOW
tPZH; Tri-state to Output HIGH
tPLZ; Output LOW to Tri-state
tPHZ; Output HIGH to Tri-state
RS-422/V.11
tPZL; Tri-state to Output LOW
tPZH; Tri-state to Output HIGH
tPLZ; Output LOW to Tri-state
tPHZ; Output HIGH to Tri-state
V.35
tPZL; Tri-state to Output LOW
tPZH; Tri-state to Output HIGH
tPLZ; Output LOW to Tri-state
tPHZ; Output HIGH to Tri-state
0.11
0.11
0.05
0.05
5.0
2.0
2.0
2.0
µs
µs
µs
µs
CL = 100pF, Fig. 34 & 40; S2 closed
CL = 100pF, Fig. 34 & 40; S2 closed
CL = 100pF, Fig. 34 & 40; S2 closed
CL = 100pF, Fig. 34 & 40; S2 closed
0.07
0.05
0.55
0.12
2.0
2.0
2.0
2.0
µs
µs
µs
µs
CL = 100pF, Fig. 34 & 40; S2 closed
CL = 100pF, Fig. 34 & 40; S2 closed
CL = 100pF, Fig. 34 & 40; S2 closed
CL = 100pF, Fig. 34 & 40; S2 closed
0.04
0.05
0.03
0.11
10.0
2.0
2.0
2.0
µs
µs
µs
µs
CL = 100pF, Fig. 34 & 37; S1 closed
CL = 100pF, Fig. 34 & 37; S2 closed
CL = 15pF, Fig. 34 & 37; S1 closed
CL = 15pF, Fig. 34 & 37; S2 closed
0.85
0.36
0.06
0.05
10.0
2.0
2.0
2.0
µs
µs
µs
µs
CL = 100pF, Fig. 34 & 37; S1 closed
CL = 100pF, Fig. 34 & 37; S2 closed
CL = 15pF, Fig. 34 & 37; S1 closed
CL = 15pF, Fig. 34 & 37; S2 closed
0.05
0.05
0.65
0.65
2.0
2.0
2.0
2.0
µs
µs
µs
µs
CL = 100pF, Fig. 35 & 40; S1 closed
CL = 100pF, Fig. 35 & 40; S2 closed
CL = 100pF, Fig. 35 & 40; S1 closed
CL = 100pF, Fig. 35 & 40; S2 closed
0.04
0.03
0.03
0.03
2.0
2.0
2.0
2.0
µs
µs
µs
µs
CL = 100pF, Fig. 35 & 40; S1 closed
CL = 100pF, Fig. 35 & 40; S2 closed
CL = 100pF, Fig. 35 & 40; S1 closed
CL = 100pF, Fig. 35 & 40; S2 closed
RECEIVER DELAY TIME BETWEEN ACTIVE MODE AND TRI-STATE MODE
RS-232/V.28
tPZL; Tri-state to Output LOW
tPZH; Tri-state to Output HIGH
tPLZ; Output LOW to Tri-state
tPHZ; Output HIGH to Tri-state
RS-423/V.10
tPZL; Tri-state to Output LOW
tPZH; Tri-state to Output HIGH
tPLZ; Output LOW to Tri-state
tPHZ; Output HIGH to Tri-state
SP508E_101_013020
5
OTHER AC CHARACTERISTICS (Continued)
TA = -40°C to +85°C and VCC = +4.75V to +5.25V unless otherwise noted. Typical values are for TA = 25C and Vcc = 5V
PARAMETER
MIN. TYP. MAX. UNITS
RS-422/V.11
tPZL; Tri-state to Output LOW
tPZH; Tri-state to Output HIGH
tPLZ; Output LOW to Tri-state
tPHZ; Output HIGH to Tri-state
V.35
tPZL; Tri-state to Output LOW
tPZH; Tri-state to Output HIGH
tPLZ; Output LOW to Tri-state
tPHZ; Output HIGH to Tri-state
CONDITIONS
0.04
0.03
0.03
0.03
2.0
2.0
2.0
2.0
µs
µs
µs
µs
CL = 100pF, Fig. 35 & 39; S1 closed
CL = 100pF, Fig. 35 & 39; S2 closed
CL = 15pF, Fig. 35 & 39; S1 closed
CL = 15pF, Fig. 35 & 39; S2 close
0.04
0.03
0.03
0.03
2.0
2.0
2.0
2.0
µs
µs
µs
µs
CL = 100pF, Fig. 35 & 39; S1 closed
CL = 100pF, Fig. 35 & 39; S2 closed
CL = 15pF, Fig. 35 & 39; S1 closed
CL = 15pF, Fig. 35 & 39; S2 closed
TRANSCEIVER TO TRANSCEIVER SKEW
RS-232 Driver
100
ns
100
ns
RS-232 Receiver
20
ns
20
ns
RS-422 Driver
2
ns
2
ns
RS-422 Receiver
2
ns
2
ns
RS-423 Driver
2
ns
2
ns
RS-423 Receiver
2
ns
2
ns
V.35 Driver
2
ns
2
ns
V.35 Receiver
2
ns
2
ns
(per Figures 32, 33, 36, 38)
[ (tphl )Tx1 – (tphl )Txn ]
[ (tplh )Tx1 – (tplh )Txn]
[ (tphl )Rx1 – (tphl )Rxn ]
[ (tphl )Rx1 – (tphl )Rxn ]
[ (tphl )Tx1 – (tphl )Txn ]
[ (tplh )Tx1 – (tplh )Txn ]
[ (tphl )Rx1 – (tphl )Rxn ]
[ (tphl )Rx1 – (tphl )Rxn ]
[ (tphl )Tx2 – (tphl )Txn ]
[ (tplh )Tx2 – (tplh )Txn ]
[ (tphl )Rx2 – (tphl )Rxn ]
[ (tphl )Rx2 – (tphl )Rxn ]
[ (tphl )Tx1 – (tphl )Txn ]
[ (tplh )Tx1 – (tplh )Txn ]
[ (tphl )Rx1 – (tphl )Rxn ]
[ (tphl )Rx1 – (tphl )Rxn]
SP508E_101_013020
6
76 N/C
77 VCC
78 TR(b)
79 RRC(b)
80 VCC
81 RRC(a)
82 GND
83 RS(a)
84 VCC
85 RS(b)
86 GND
87 ST(a)
88 VCC
89 V35TGND3
90 ST(b)
91 GND
92 TT(a)
93 VCC
94 V35TGND2
95 TT(b)
96 GND
97 SD(a)
98 VCC
99 V35TGND1
100 SD(b)
PINOUT 100 PIN LQFP
VCC 1
75 TR(a)
GND 2
74 GND
SDEN 3
73 VDD
TTEN 4
72 C1+
STEN 5
71 VCC
RSEN 6
70 C2+
TREN 7
69 C1-
RRCEN 8
68 GND
RLEN 9
67 C2-
LLEN 10
66 VSS
SP508E
RDEN 11
RTEN 12
TXCEN 13
CSEN 14
DMEN 15
65 RL(a)
64 VCC
63 LL(a)
62 TM(a)
61 IC(a)
RRTEN 16
60 RRT(a)
ICEN 17
59 RRT(b)
TMEN 18
58 V10GND
D0 19
57 DM(a)
D1 20
56 DM(b)
D2 21
55 CS(a)
TERM_OFF 22
54 CS(b)
D_LATCH 23
53 TXC(a)
N/C 24
52 GND
GND 25
RT(a) 50
RT(b) 49
RD(a) 48
RD(b) 47
V35RGND 46
VCC 45
GND 44
TM 43
RI 42
DCD_DTE 41
DSR 40
CTS 39
TXC 38
RXC 37
RXD 36
LL 35
RL 34
DCD_DCE 33
DTR 32
ST 30
RTS 31
TXCE 29
TXD 28
VCC 26
LOOPBACK 27
51 TXC(b)
SP508E_101_013020
7
PIN DESCRIPTION
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Pin Name Description
VCC
5V Power Supply Input
GND
Signal Ground
SDEN
TxD Driver Enable Input
TTEN
TxCE Driver Enable Input
STEN
ST Driver Enable Input
RSEN
RTS Driver Enable Input
TREN
DTR Driver Enable Input
RRCEN DCD Driver Enable Input
RLEN
RL Driver Enable Input
LLEN#
LL Driver Enable Input
RDEN#
RxD Receiver Enable Input
RTEN#
RxC Receiver Enable Input
TxCEN# TxC Receiver Enable Input
CSEN#
CTS Receiver Enable Input
DMEN#
DSR Receiver Enable Input
RRTEN# DCDDTE Receiver Enable Input
ICEN#
RI Receiver Enable Input
TMEN
TM Receiver Enable Input
D0
Mode Select Input
D1
Mode Select Input
D2
Mode Select Input
TERM_OFF Termination Disable Input
D_LATCH# Decoder Latch Input
NC
No Connect
GND
Signal Ground
VCC
5V Power Supply Input
LOOPBACK# Loopback Mode Enable Input
TxD
TxD Driver TTL Input
TxCE
TxCE Driver TTL Input
ST
ST Driver TTL Input
RTS
RTS Driver TTL Input
DTR
DTR Driver TTL Input
DCD_DCE DCDDCE Driver TTL Input
RL
RL Driver TTL Input
LL
LL Driver TTL Input
RxD
RxD Receiver TTL Output
RxC
RxC Receiver TTLOutput
TxC
TxC Receiver TTL Output
CTS
CTS Receiver TTL Output
DSR
DSR Receiver TTL Output
DCD_DTE DCDDTE Receiver TTL Output
RI
RI Receiver TTL Output
TM
TM Receiver TTL Output
GND
Signal Ground
VCC
Power Supply Input
V35RGND Reciever Termination Refrence
RD(b)
RXD Non-Inverting Input
RD(a)
RXD Inverting Input
RT(b)
RxC Non-Inverting Input
RT(a)
RxC Inverting Input
Pin Number Pin Name Description
51
TxC(b)
TxC Non-Inverting Input
52
GND
Signal Ground
53
TxC(a)
TxC Inverting Input
54
CS(b)
CTS Non-Inverting Input
55
CS(a)
CTS Inverting Input
56
DM(b)
DSR Non-Inverting Input
57
DM(a)
DSR Inverting Input
58
GNDV10 V.10 Rx Reference Node
59
RRT(b)
DCDDTE Non-Inverting Input
60
RRT(a)
DCDDTE Inverting Input
61
IC
RI Receiver Input
62
TM(a)
TM Receiver Input
63
LL(a)
LL Driver Output
64
VCC
Power Supply Input
65
RL(a)
RL Driver Output
66
VSS1
-2xVCC Charge Pump Output
67
C2N
Charge Pump Capacitor
68
GND
Signal Ground
69
C1N
Charge Pump Capacitor
70
C2P
Charge Pump Capacitor
71
VCC
Power Supply Input
72
C1P
Charge Pump Capacitor
73
VDD
2xVCC Charge Pump Output
74
GND
Signal Ground
75
TR(a)
DTR Inverting Output
76
NC
No Connect
77
VCC
Power Supply Input
78
TR(b)
DTR Non-Inverting Output
79
RRC(b)
DCD Non-Inverting Output
80
VCC
Power Supply Input
81
RRC(a)
DCD Inverting Output
82
GND
Signal Ground
83
RS(a)
RTS Inverting Output
84
VCC
Power Supply Input
85
RS(b)
RTS Non-Inverting Output
86
GND
Signal Ground
87
ST(a)
ST Inverting Output
88
VCC
Power Supply Input
89
V35TGND3 ST Termination Referance
90
ST(b)
ST Non-Inverting Output
91
GND
Signal Ground
92
TT(a)
TxCE Inverting Output
93
VCC
5V Power Supply Input
94
V35TGND2 ST Termination Referance
95
TT(b)
TxCE Non-Inverting Output
96
GND
Signal Ground
97
SD(a)
TxD Inverting Output
98
VCC
5V Power Supply Input
99
V35TGND1 ST Termination Referance
100
SD(b)
TxD Non-Inverting Output
SP508E_101_013020
8
SP508E Driver Table
Dr i v er Ou t p u t
Pi n
V.35 Mo d e
EIA -530
Mo d e
RS-232
Mo d e
(V.28)
EIA -530A
Mo d e
RS-449
Mo d e
(V.36)
MODE (D0, D1, D2)
001
010
011
100
101
T1OUT(a)
V.35
V.11
V.28
V.11
V.11
V.11
High-Z
TxD(a)
T1OUT(b)
V.35
V.11
High-Z
V.11
V.11
V.11
High-Z
TxD(b)
X.21 Mo d e
Sh u t d o w n
(V.11)
110
Su g g es t ed
Si g n al
111
T2OUT(a)
V.35
V.11
V.28
V.11
V.11
V.11
High-Z
TxCE(a)
T2OUT(b)
V.35
V.11
High-Z
V.11
V.11
V.11
High-Z
TxCE(b)
T3OUT(a)
V.35
V.11
V.28
V.11
V.11
V.11
High-Z
TxC_DCE(a)
T3OUT(b)
V.35
V.11
High-Z
V.11
V.11
V.11
High-Z
TxC_DCE(b)
T4OUT(a)
V.28
V.11
V.28
V.11
V.11
V.11
High-Z
RTS(a)
T4OUT(b)
High-Z
V.11
High-Z
V.11
V.11
V.11
High-Z
RTS(b)
T5OUT(a)
V.28
V.11
V.28
V.10
V.11
V.11
High-Z
DTR(a)
T5OUT(b)
High-Z
V.11
High-Z
High-Z
V.11
V.11
High-Z
DTR(b)
T6OUT(a)
V.28
V.11
V.28
V.11
V.11
V.11
High-Z
DCD_DCE(a)
T6OUT(b)
High-Z
V.11
High-Z
V.11
V.11
V.11
High-Z
DCD_DCE(b)
T7OUT(a)
V.28
V.10
V.28
V.10
V.10
High-Z
High-Z
RL
T8OUT(a)
V.28
V.10
V.28
V.10
V.10
High-Z
High-Z
LL
Table 1. Driver Mode Selection
SP508E Receiver Table
Rec ei v er In p u t
Pi n
V.35 Mo d e
EIA -530
Mo d e
RS-232
Mo d e
(V.28)
EIA -530A
Mo d e
RS-449
Mo d e
(V.36)
X.21 Mo d e
Sh u t d o w n
(V.11)
Su g g es t ed
Si g n al
MODE (D0, D1, D2)
001
010
011
100
101
110
111
R1IN(a)
V.35
V.11
V.28
V.11
V.11
V.11
High-Z
RxD(a)
R1IN(b)
V.35
V.11
High-Z
V.11
V.11
V.11
High-Z
RxD(b)
R2IN(a)
V.35
V.11
V.28
V.11
V.11
V.11
High-Z
RxC(a)
R2IN(b)
V.35
V.11
High-Z
V.11
V.11
V.11
High-Z
RxC(b)
R3IN(a)
V.35
V.11
V.28
V.11
V.11
V.11
High-Z
TxC_DTE(a)
R3IN(b)
V.35
V.11
High-Z
V.11
V.11
V.11
High-Z
TxC_DTE(b)
R4IN(a)
V.28
V.11
V.28
V.11
V.11
V.11
High-Z
CTS(a)
R4IN(b)
High-Z
V.11
High-Z
V.11
V.11
V.11
High-Z
CTS(b)
R5IN(a)
V.28
V.11
V.28
V.10
V.11
V.11
High-Z
DSR(a)
R5IN(b)
High-Z
V.11
High-Z
High-Z
V.11
V.11
High-Z
DSR(b)
R6IN(a)
V.28
V.11
V.28
V.11
V.11
V.11
High-Z
DCD_DTE(a)
R6IN(b)
High-Z
V.11
High-Z
V.11
V.11
V.11
High-Z
DCD_DTE(b)
R7IN(a)
V.28
V.10
V.28
V.10
V.10
High-Z
High-Z
RI
R8IN(a)
V.28
V.10
V.28
V.10
V.10
High-Z
High-Z
TM
Table 2. Receiver Mode Selection
SP508E_101_013020
9
TEST CIRCUITS
A
A
VOC
VT
3kΩ
C
C
Figure 1. V.28 Driver Output Open Circuit Voltage
Figure 2. V.28 Driver Output Loaded Voltage
A
A
VT
7kΩ
O scilloscope
I sc
C
C
Scope used f or sle w rate
measurement.
Figure 4. V.28 Driver Output Short-Circuit Current
Figure 3. V.28 Driver Output Slew Rate
V C C = 0V
A
A
Ix
±2V
3kΩ
2500pF
O s cillos cope
C
C
Figure 6. V.28 Driver Output Rise/Fall Times
Figure 5. V.28 Driver Output Power-Off Impedance
SP508E_101_013020
10
A
A
I ia
±15V
voc
C
C
Figure 8. V.28 Receiver Input Open Circuit Bias
Figure 7. V.28 Receiver Input Impedance
A
A
3.9kΩ
Vt
450Ω
VOC
C
C
Figure 9. V.10 Driver Output Open-Circuit Voltage
Figure 10. V.10 Driver Output Test Terminated Volt-
V C C = 0V
A
A
Ix
±0.25V
I sc
C
C
Figure 11. V.10 Driver Output Short-Circuit Current
Figure 12. V.10 Driver Output Power-Off Current
SP508E_101_013020
11
A
A
I ia
±10V
O scilloscope
450Ω
C
C
Figure 13. V.10 Driver Output Transition Time
Figure 14. V.10 Receiver Input Current
V.10 RECEIVER
A
+3.25mA
V OCA
-10V
3.9kΩ
-3V
VOC
V OCB
+3V
+10V
Maximum Input Current
vesus Voltage
B
-3.25mA
C
Figure 15. V.10 Receiver Input IV Graph
Figure 16. V.11 Driver Output Open-Circuit Voltage
A
A
Isa
50Ω
VT
50Ω
B
B
V OS
I sb
C
C
Figure 17. V.11 Driver Output Test Terminated
Voltage
Figure 18. V.11 Driver Output Short-Circuit Current
SP508E_101_013020
12
V C C = 0V
A
A
Iia
Ixa
±10V
±0.25V
B
B
C
C
V C C = 0V
A
A
±0.25V
±10V
Ixb
B
B
C
Iib
C
Figure 19. V.11 Driver Output Power-Off Current
Figure 20. V.11 Receiver Input Current
V.11 RECEIVER
+3.25mA
A
50Ω
Oscilloscope
50Ω
B
-10V
50Ω
-3V
VE
+3V
C
+10V
Maximum Input Current
versus Voltage
-3.25mA
Figure 22. V.11 Receiver Input IV Graph
Figure 21. V.11 Driver Output Rise/Fall Time
SP508E_101_013020
13
A
V.11 R E CE IV E R
Iia
w/ O ptiona l C a ble Termina tion
i [mA] = V [V ] / 0.1
(100Ω to 150Ω)
±6V
100Ω to
150Ω
i [mA] = V [V ] - 3) / 4. 0
-6V
-3V
+3V
B
+6V
i [mA] = V [V ] - 3) / 4. 0
C
Ma ximum Input C urrent
i [mA] = V [V ] / 0.1
vers us Voltage
Figure 24. V.11 Receiver Input Graph w/ Termination
A
±6V
A
100Ω to
150Ω
50Ω
B
VT
Iib
50Ω
VOS
B
C
C
Figure 23. V.11 Receiver Input Current w/
Termination
Figure 25. V.35 Driver Output Test Terminated
Voltage
V1
A
A
50Ω
24kHz, 550mV p-p
S ine Wa ve
VCC
V2
B
B
C
Figure 26. V.35 Driver Output Offset Voltage
Figure 27. V.35 Driver Output Source Impedance
SP508E_101_013020
14
A
A
50Ω
O scilloscope
50Ω
IS C
B
B
50Ω
±2V
C
C
Figure 29. V.35 Driver Output Rise/Fall Time
Figure 28. V.35 Driver Output Short-Circuit
Impedance
A
V1
A
50Ω
24kHz, 550mV p-p
S ine Wa ve
V2
I sc
B
B
±2V
C
C
Figure 30. V.35 Receiver Input Source Impedance
Figure 31. V.35 Receiver Input Short-Circuit
Impedance
Any one of the three conditions for disabling the driver.
VCC = 0V
VCC
Logic “1”
1
1
1
D2
D1
D0
A
IZSC
C L1
±10V
T IN
B
B
A
A
fIN (50% Duty Cycle, 2.5V
C L2
P-P
R OU T
15pF
)
B
Figure 33. Driver/Receiver Timing Test Circuit
Figure 32. Driver Output Leakage Current Test
SP508E_101_013020
15
Output
Under
Test
VCC
S1
500Ω
VCC
S1
CR L
CL
1K Ω
Test P oint
R eceiver
Output
1K Ω
S2
S2
Figure 35. Receiver Timing Test Load Circuit
Figure 34. Driver Timing Test Load Circuit
f > 10MHz; tR < 10ns ; tF < 10ns
DR IV E R
INP UT
DR IV E R
O UT P UT
DIF F E R E NT IAL
O UT P UT
VB – VA
+3V
1.5V
0V
A
1.5V
tPHL
tPLH
V O 1/2V O
1/2V O
B
tDPLH
V O+
0V
VO–
tDPHL
tR
tF
tSKEW = | tDPLH - tDPHL |
Figure 36. Driver Propagation Delays
Mx or T x_ E nable
+3V
1.5V
0V
A, B
1.5V
tZL
5V
2.3V
V OL
V OH
A, B
2.3V
0V
tLZ
O utput normally L O W
0.5V
O utput normally H IG H
0.5V
tZH
tHZ
Figure 37. Driver Enable and Disable Times
A–B
R E C E IVE R O UT
f > 10MHz; tR < 10ns ; tF < 10ns
V 0D2 +
0V
V 0D2 –
O UT P UT
V OH
V OL
0V
INP UT
(V OH - V OL )/2
(V OH - V OL )/2
tPLH
tPHL
tSKEW = | tPHL - tPLH |
Figure 38. Receiver Propagation Delays
SP508E_101_013020
16
DE C x +3V
R C V R ENABLE
R E C E IVE R O UT
0V
f = 1MHz; tR < 10ns ; tF < 10ns
1.5V
1.5V
tZL
5V
1.5V
V IL
V IH
R E C E IVE R O UT
1.5V
0V
tLZ
O utput normally L O W
0.5V
O utput normally H IG H
0.5V
tZH
tHZ
Figure 39. Receiver Enable and Disable Times
T x_ E nable
+3V
0V
0V
T OUT
V OL
+3V
T x_ E nable
T OUT
0V
V OH
f = 60kH z; tR < 10ns ; tF < 10ns
1.5V
1.5V
tLZ
tZL
V OL - 0.5V
O utput LO W
V OL - 0.5V
f = 60kH z; tR < 10ns ; tF < 10ns
1.5V
1.5V
tZH
O utput HIG H
tHZ
V OH - 0.5V
0V
Figure 40. V.28 (RS-232) and V.10 (RS-423) Driver Enable and Disable Times
SP508E_101_013020
17
Figure 41. Typical V.28 Driver Output Waveform
Figure 42. Typical V.10 Driver Output Waveform
Figure 43. Typical V.11 Driver Output Waveform
Figure 44. Typical V.35 Driver Output Waveform
SP508E_101_013020
18
+5V (decoupling capacitor not shown)
VCC pins (1, 26, 45, 64, 71, 77, 80, 84, 88, 93, 98)
GND pins (2, 25, 44, 52, 68, 74, 82, 86, 91, 96)
N.C. pins (24 and 76)
1µF
1µF
72
1µF
VCC
73 VDD
V35RGND
RD(a)
RxD
RDEN
RD(b)
69
C1+
C1-
70
C2+
Regulated Charge Pump
67
C2-
VSS
1µF
46
48
28
97
99
100
3
36
11
47
29
92
94
95
4
50
RT(a)
RT(b)
37
12
49
TxC(a)
53
RxC
RTEN
TxC
TxCEN
TxC(b)
CS(a)
55
CS(b)
39
14
54
DM(a)
57
CTS
CSEN
DSR
DMEN
40
15
DM(b)
56
RRT(a)
60
DCD_DTE
RRTEN
RRT(b)
IC
RI
ICEN
30
87
89
90
5
38
13
51
41
16
59
TM
TMEN
23
D-LATCH
22
TERM-OFF
27
LOOPBACK
TTEN
ST
ST(a)
V35TGND3
ST(b)
STEN
DCD_DCE
10
V.10-GND
TT(b)
33
81
63
SP508E
V35TGND2
TR(b)
35
D2
TT(a)
78
7
9
D1
TxCE
DTR
65
21
SDEN
32
75
42
17
20
SD(b)
RS(b)
34
D0
V35TGND1
85
6
8
19
SD(a)
RTS
61
43
18
TxD
31
83
79
62
TM(a)
66
RS(a)
RSEN
TR(a)
TREN
RRC(a)
RRC(b)
RRCEN
RL
RL(a)
RLEN
LL
LL(a)
LLEN
58
GND
RECEIVER TERMINATION NETWORK
V.35 MODE
V.11 MODE
V.35 DRIVER TERMINATION NETWORK
51ohms
51ohms
V.35 MODE
124ohms
124ohms
TX ENABLE
RX ENABLE
51ohms
51ohms
Figure 45. Functional Diagram
SP508E_101_013020
19
FEATURES
There are four basic types of driver circuits –
ITU-T-V.28 (RS-232), ITU-T-V.10 (RS-423),
ITU-T-V.11 (RS-422), and CCITT-V.35.
The SP508E contains highly integrated serial
transceivers that offer programmability
between interface modes through software
control. The SP508E offers the hardware
interface modes for RS-232 (V.28), RS-449/
V.36 (V.11 and V.10), EIA-530 (V.11 and V.10),
EIA-530A (V.11 and V.10), V.35 (V.35 and V.28)
and X.21(V.11). The interface mode selection
is done via three control pins, which can be
latched via microprocessor control.
The V.28 (RS-232) drivers output singleended signals with a minimum of +5V (with
3kΩ & 2500pF loading), and can operate over
120kbps. Since the SP508E uses a charge
pump to generate the RS-232 output rails, the
driver outputs will never exceed +10V. The V.28
driver architecture is similar to Exar's standard
line of RS-232 transceivers.
The SP508E has eight drivers, eight receivers,
and Exar's patented on-board charge pump
(5,306,954) that is ideally suited for wide area
network connectivity and other multi-protocol
applications. Other features include digital and
line loopback modes, individual enable/disable
control lines for each driver and receiver, failsafe when inputs are either open or shorted,
individual termination resistor ground paths,
separate driver and receiver ground outputs,
enhanced ESD protection on driver outputs
and receiver inputs.
The RS-423 (V.10) drivers are also singleended signals which produce open circuit VOL
and VOH measurements of +4.0V to +6.0V.
When terminated with a 450Ω load to ground,
the driver output will not deviate more than 10%
of the open circuit value. This is in compliance
of the ITU V.10 specification. The V.10 (RS-423)
drivers are used in RS-449/V.36, EIA-530, and
EIA-530A modes as Category II signals from
each of their corresponding specifications.
The V.10 drivers are guaranteed to transmit
over 120kbps, but can operate at over 1Mbps
if necessary.
THEORY OF OPERATION
The SP508E device is made up of 1) the drivers,
2) the receivers, 3) a charge pump, 4) DTE/DCE
switching algorithm, and 5) control logic.
The third type of drivers are V.11 (RS-422)
differential drivers. Due to the nature of
differential signaling, the drivers are more
immune to noise as opposed to single-ended
transmission methods. The advantage is
evident over high speeds and long transmission
lines. The strength of the driver outputs can
produce differential signals that can maintain
+2V differential output levels with a load of
100Ω. The signal levels and drive capability of
these drivers allow the drivers to also support
RS-485 requirements of +1.5V differential
output levels with a 54Ω load. The strength
allows the SP508E differential driver to drive
over long cable lengths with minimal signal
degradation. The V.11 drivers are used in
RS-449, EIA-530, EIA-530A and V.36 modes
as Category I signals which are used for clock
and data. Exar's new driver design over its
predecessors allow the SP508E to operate
over 20Mbps for differential transmission.
Drivers
The SP508E has eight enhanced independent
drivers. Control for the mode selection is done
via a three-bit control word into D0, D1, and
D2. The drivers are prearranged such that for
each mode of operation, the relative position
and functionality of the drivers are set up to
accommodate the selected interface mode.
As the mode of the drivers is changed, the
electrical characteristics will change to support
the required signal levels. The mode of each
driver in the different interface modes that can
be selected is shown in Table 1.
SP508E_101_013020
20
The fourth type of drivers are V.35 differential
drivers. There are only three available on the
SP508E for data and clock (TxD, TxCE, and
TxC in DCE mode). These drivers are current
sources that drive loop current through
a differential pair resulting in a 550mV
differential voltage at the receiver. These
drivers also incorporate fixed termination
networks for each driver in order to set the
VOH and VOL depending on load conditions.
This termination network is basically a “Y”
configuration consisting of two 51Ω resistors
connected in series and a 124Ω resistor
connected between the two 50Ω resistors
and a V35TGND output. Each of the three
drivers and its associated termination will
have its own V35TGND output for grounding
convenience. Filtering can be done on
these pins to reduce common mode noise
transmitted over the transmission line by
connecting a capacitor to ground.
ranged for the specific requirements of
the synchronous serial interface. As the
operating mode of the receivers is changed,
the electrical characteristics will change
to support the required serial interface
protocols of the receivers. Table 2 shows
the mode of each receiver in the different
interface modes that can be selected.
There are two basic types of receiver circuits—ITU-T-V .28 (RS-232) and ITU-T-V.11,
(RS-422).
The RS-232 (V.28) receiver is single-ended
and accepts RS-232 signals from the RS232 driver. The RS-232 receiver has an
operating input voltage range of +15V and
can receive signals downs to +3V. The input
sensitivity complies with RS-232 and V .28
at +3V. The input impedance is 3kΩ to 7kΩ
in accordance to RS-232 and V .28. The
receiver output produces a TTL/CMOS signal
with a +2.4V minimum for a logic “1” and a
+0.4V maximum for a logic “0”. The RS-232
(V.28) protocol uses these receivers for all
data, clock and control signals. They are also
used in V.35 mode for control line signals:
CTS, DSR, LL, and RL. The RS-232 receivers can operate over 120kbps.
The drivers also have separate enable pins
which simplifies half-duplex configurations
for some applications, especially programmable DTE/DCE. The enable pins will either
enable or disable the output of the drivers
according to the appropriate active logic
illustrated on Figure 45. The enable pins
have internal pull-up and pull-down devices,
depending on the active polarity of the receiver, that enable the driver upon power-on
if the enable lines are left floating. During
disabled conditions, the driver outputs will
be at a high impedance 3-state.
The second type of receiver is a differential
type that can be configured internally to
support ITU-T-V.10 and CCITT-V.35
depending on its input conditions. This
receiver has a typical input impedance
of 10kΩ and a differential threshold of
less than +200mV, which complies with
the ITU-T-V.11 (RS-422) specifications.
V.11 receivers are used in RS-449/V.36,
EIA-530, EIA-530A and X.21 as Category I
signals for receiving clock, data, and some
control line signals not covered by Category
II V.10 circuits. The differential V.11 transceiver has improved architecture that allows
over 20Mbps transmission rates.
The driver inputs are both TTL and CMOS
compatible. All driver inputs have an internal
pull-up resistor so that the output will be at
a defined state at logic LOW (“0”). Unused
driver inputs can be left floating. The internal pull-up resistor value is approximately
500kΩ.
Receivers
The SP508E has eight enhanced independent receivers. Control for the mode
selection is done via a three-bit control word that is the same as the driver
control word. Therefore, the modes for
the drivers and receivers are identical in the
application.
Receivers dedicated for data and clock (RxD,
RxC, TxC) incorporate internal termination
for V.11. The termination resistor is typically
120Ω connected between the A and B inputs.
The termination is essential for minimizing
crosstalk and signal reflection over the
transmission line . The minimum value is
guaranteed to exceed 100Ω, thus complying
with the V.11 and RS-422 specifications.
Like the drivers, the receivers are prear
SP508E_101_013020
21
This resistor is invoked when the receiver is
operating as a V.11 receiver, in modes EIA530, EIA-530A, RS-449/V.36, and X.21. The
same receivers also incorporate a termination network internally for V.35 applications.
For V.35, the receiver input termination is a
“Y” termination consisting of two 51Ω resistors connected in series and a 124Ω resistor
connected between the two 50Ω resistors
and V35RGND output. The V35RGND is
usually grounded. The receiver itself is
identical to the V.11 receiver.
CHARGE PUMP
The charge pump is a Exar-patented design
(5,306,954) and uses a unique approach
compared to older less-efficient designs.
The charge pump still requires four external
capacitors, but uses four-phase voltage
shifting technique to attain symmetrical
power supplies. The charge pump VDD and
VSS outputs are regulated to +5.8V and
-5.8V, respectively. There is a free-running
oscillator that controls the four phases of
the voltage shifting. A description of each
phase follows.
The differential receivers can be configured
to be ITU-T-V.10 single-ended receivers
by internally connecting the non-inverting
input to ground. This is internally done
by default from the decoder. The non-inverting input is rerouted to V10GND and
can be grounded separately. The ITU-TV.10 receivers can operate over 1Mbps
and are used in RS-449/V.36, E1A-530,
E1A-530A and X.21 modes as Category II
signals as indicated by their corresponding
specifications. All receivers include an enable/disable line for disabling the receiver
output allowing convenient half-duplex
configurations. The enable pins will either
enable or disable the output of the receivers
according to the appropriate active logic illustrated on Figure 45. The receiver’s enable
lines include an internal pull-up or pull-down
device, depending on the active polarity of
the receiver, that enables the receiver upon
power up if the enable lines are left floating.
During disabled conditions, the receiver
outputs will be at a high impedance state.
If the receiver is disabled any associated
termination is also disconnected from the
inputs.
Phase 1
__VSS charge storage ——During this phase
of the clock cycle, the positive side of capacitors C1 and C2 are initially charged to VCC. C+
is then switched to ground and the charge
in C1- is transferred to C2-. Since C2+ is connected to VCC, the voltage potential across
capacitor C2 is now 2XVCC.
Phase 2
—VSS transfer —Phase two of the clock connects the negative terminal of C2 to the VSS
storage capacitor and the positive terminal
of C2 to ground, and transfers the negative
generated voltage to C3. This generated
voltage is regulated to –5.8V. Simultaneously, the positive side of the capacitor C1
is switched to VCC and the negative side is
connected to ground.
Phase 3
—VDD charge storage —The third phase of
the clock is identical to the first phase—the
charge transferred in C1 produces –VCC in
the negative terminal of C1 which is applied
to the negative side of the capacitor C2 .
Since C2+ is at VCC, the voltage potential
across C2 is 2XVCC.
All receivers include a fail-safe feature that
outputs a logic high when the receiver inputs
are open, terminated but open, or shorted
together. For single-ended V.28 and V.10
receivers, there are internal 5kΩ pull-down
resistors on the inputs which produces a
logic high (“1”) at the receiver outputs. The
differential receivers have a proprietary circuit that detect open or shorted inputs and
if so, will produce a logic HIGH (“1”) at the
receiver output.
Phase 4
—VDD transfer —The fourth phase of the
clock connects the negative terminal of C2
to ground, and transfers the generated 5.8V
across C2 to C4, the VDD storage capacitor.
This voltage is regulated to +5.8V. At the
regulated voltage, the internal oscillator is
disabled and simultaneously with this, the
positive side of capacitor C1 is switched to
VCC and the negative side is connected to
ground, and the cycle begins again.
SP508E_101_013020
22
The charge pump cycle will continue as long
as the operational conditions for the internal
oscillator are present.
There are internal pull-up devices on D0,
D1, and D2, which allow the device to be in
SHUTDOWN mode (“111”) upon power up.
However , if the device is powered -up with
the D_LATCH at a logic HIGH, the decoder
state of the SP508E will be undefined.
Since both V+ and V- are separately generated from VCC; in a no-load condition V+ and
V- will be symmetrical. Older charge pump
approaches that generate V- from V+ will show
a decrease in the magnitude of V- compared
to V+ due to the inherent inefficiencies in
the design.
ESD TOLERANCE
The SP508E device incorporates ruggedized
ESD cells on all driver output and receiver
input pins. The ESD structure is improved
over our previous family for more rugged
applications and environments sensitive
to electrostatic discharges and associated
transients.
The clock rate for the charge pump typically
operates at 250kHz. The external capacitors
can be as low as 1µF with a 16V breakdown
voltage rating.
CTR1/CTR2 EUROPEAN COMPLIANCY
As with all of Exar’s previous multiprotocol serial transceiver IC’s, the
drivers and receivers have been designed to meet all the requirements to
NET1/NET2 and TBR2 in order to meet
CTR1/CTR2 compliancy. The SP508E is
also tested in-house at Exar and adheres
to all the NET1/2 physical layer testing
and the ITU Series V specifications before
shipment. Please note that although the
SP508E , as with its predecessors, adhere to CTR1/CTR2 compliancy testing,
any complex or unusual configuration should
be double-checked to ensure CTR1/CTR2
compliance. Consult the factory for details.
TERM_OFF FUNCTION
The SP508E contains a TERM_OFF pin
that disables all three receiver input termination networks regardless of mode.
This allows the device to be used in
monitor mode applications that are typically found in networking test equipment.
The TERM_OFF pin internally contains a
pull-down device with an impedance of over
500kΩ, which will default in a “ON” condition
during power-up if V.35 receivers are used.
The individual receiver enable line and
the SHUTDOWN mode from the decoder
will disable the termination regardless of
TERM_OFF.
LOOPBACK FUNCTION
The SP508E contains a LOOPBACK pin that
invokes a loopback path. This loopback path
is illustrated in Figure 46. LOOPBACK has
an internal pull-up resistor that defaults to
normal mode during power up or if the pin is
left floating. During loopback, the driver output and receiver input characteristics will still
adhere to its appropriate specifications.
DECODER AND D_LATCH FUNCTION
The SP508E contains a D_LATCH pin
that latches the data into the D0, D1,
and D2 decoder inputs. If tied to a
logic LOW (“0”), the latch is transparent, allowing the data at the decoder
inputs to propagate through and program
the SP508E accordingly. If tied to a logic
HIGH(“1”), the latch locks out the data and
prevents the mode from changing until this
pin is brought to a logic LOW.
SP508E_101_013020
23
SD(a)
TxD
SD(b)
RD(a)
RxD
RD(b)
TT(a)
TxCE
TT(b)
RT(a)
RxC
RT(b)
ST(a)
ST
ST(b)
TxC(a)
TxC
TxC(b)
RS(a)
RTS
RS(b)
CS(a)
CTS
CS(b)
TR(a)
DTR
TR(b)
DM(a)
DSR
DM(b)
RRC(a)
DCD_DCE
RRC(b)
RR T(a)
DCD_DTE
RR T(b)
RL
RL(a)
RI
IC
LL
LL(a)
TM
TM(a)
Figure 46. SP508E Loopback Path
SP508E_101_013020
24
Figure 47. SP508E Typical Operating Configuration to Serial Port Connector with DCE/DTE
programmability
SP508E_101_013020
25
Input Line
Output Line
I/O Lines represented by double arrowhead signifies a bi-directional bus.
* - Driver applies f or DCE only on pins 15 and 12.
Receiver applies for DTE only on pins 15 and 12.
Driver applies f or DCE only on pins 8 and 10.
Receiver applies for DTE only on pins 8 and 10.
DCE/DTE
#142 (TM)
#125 (RI)
+5V
DTE
#109 (DCD)
#107 (DSR)
#106 (CTS)
#114 (TxC)
#115 (RXC)
#105 (RXD)
#141 (LL)
#140 (RL)
#109 (DCD)DCE
#108 (DTR)
#105 (RTS)
#113 (TXCE)
#103 (TxD)
+5V
10µ F
TM
RI
DCD_DTE
DSR
CTS
TxC
RxC
RxD
LL
RL
DCD_DCE
DTR
RTS
ST
TxCE
TxD
C1+
1µ F
C1- C2+ C2-
1µ F
RDEN
RTEN
TxCEN
DMEN
CSEN
RRTEN
ICEN
TMEN
GND
D2
D1
D0
VSS
V10_GND
V35RGND
V35TGND3
V35TGND2
V35TGND1
LOOPBACK
TERM_OFF
D_LATCH
SP508E
Logic Section
Transceiver Section
Charge Pump Section
VDD
SDEN
TTEN
STEN
TREN
RSEN
RRCEN
RLEN
LLEN
VCC
1µ F
1µ F
+5V
SIGNAL GND (10 Pins )
25 (V.10,V.28)
Date:
Title :
Customer:
Reference Design Schematic
Doc. #:
Typical SP508 DB-26 Serial Port Configuration
LL_TM
RI_RL
RXD_TXD_A
RXD_TXD_B
RXC_TXCE_A
RXC_TXCE_B
*TXC_RXC_A
*TXC_RXC_B
CTS_RTS_A
CTS_RTS_B
DSR_DTR_A
DSR_DTR_B
DCD_DCD_A
DCD_DCD_B
3 (V.11,V.35, V.28)
16 (V.11,V.35)
17 (V.11,V.35, V.28)
9 (V.11,V.35)
15 (V.11,V.35, V.28)
12 (V.11,V.35)
5 (V.11,V.28)
13 (V.11)
6 (V.11,V.28)
22 (V.11)
8 (V.11,V.28)
10 (V.11)
22 (V.10,V.28)
LL_TM
RL_RI
RTS_CTS_A
RTS_CTS_B
DTR_DSR_A
DTR_DSR_B
TXD_RXD_A
TXD_RXD_B
TXCE_TXC_A
TXCE_TXC_B
Signal (DTE_DCE)
18 (V.10,V.28)
21 (V.10,V.28)
4 (V.11,V.28)
19 (V.11)
20 (V.11,V.28)
23 (V.11)
2 (V.11,V.35, V.28)
14 (V.11,V.35)
24 (V.11,V.35, V.28)
11 (V.11,V.35)
µ DB-26 Serial Port Connector Pins
0
Rev.
PACKAGE: 100 Pin LQFP
SP508E_101_013020
26
DCE CONFIGURATION
SP508E_101_013020
27
DTE CONFIGURATION
SP508E_101_013020
28
ORDERING INFORMATION(1)
TEMPERATURE
RANGE
PACKAGE
PACKAGING
METHOD
LEAD-FREE(2)
SP508ECF-L
0°C to 70°C
100 Lead LQFP
Tray
Yes
SP508EEF-L
-40°C to 85°C
100 Lead LQFP
Tray
Yes
PART NUMBER
NOTES:
1. Refer to http://www.maxlinear.com/SP508E for most up-to-date Ordering Information.
2. Visit www.maxlinear.com for additional information on Environmental Rating.
REVISION HISTORY
DATE
REVISION DESCRIPTION
07/24/12
1.0.0
Production Release
01/30/20
1.0.1
Update to MaxLinear logo. Update ordering information.
MaxLinear, Inc.
5966 La Place Court, Suite 100
Carlsbad, CA 92008
760.692.0711 p.
760.444.8598 f.
www.maxlinear.com
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