SP509CF

® SP509 Rugged 40Mbps, 8 Channel Multi-Protocol Transceiver with Programmable DCE/DTE and Termination Resistors FEATURES ■ Ultra Fast 40Mbps Differential Transmission Rates Available ■ Improved ESD Tolerance for Analog I/Os with 15kV HBM. ■ Internal Transceiver Termination Resistors for V.11 and V.35 ■ Interface Modes: ✓ RS-232 (V.28) ✓ X.21 (V.11) ✓ RS-449/V.36 (V.10 & V.11) ✓ EIA-530 (V.10 & V.11) ✓ EIA-530A (V.10 & V.11) ✓ V.35 Now Available in Lead Free Packaging Refer to page 7 for pinout ■ Protocols are Software Selectable with 3-Bit Word ■ Eight (8) Drivers and Eight (8) Receivers ■ V.35 and V.11 Receiver Termination Network Disable Option ■ Internal Line or Digital Loopback for Diagnostic Testing ■ Adheres to NET1/NET2 and TBR-2 Compliancy Requirements ■ Easy Flow-Through Pinout ■ +5V Only Operation ■ Individual Driver and Receiver Enable/Disable Controls ■ Operates in either DTE or DCE Mode APPLICATIONS ■ Router ■ Frame Relay ■ CSU ■ DSU ■ PBX ■ Secure Communication Terminals DESCRIPTION The SP509 is a monolithic device that supports eight (8) popular serial interface standards for Wide Area Network (WAN) connectivity. The SP509 is fabricated using a low power BiCMOS process technology, and incorporates a Sipex regulated charge pump allowing +5V only operation. Sipex's patented charge pump provides a regulated output of +5.8V, which will provide enough voltage for compliant operation in all modes. Eight (8) drivers and eight (8) receivers can be configured via software for any of the above interface modes at any time. The SP509 requires no additional external components for compliant operation for all of the eight (8) modes of operation other than four capacitors used for the internal charge pump. All necessary termination is integrated within the SP509 and is switchable when V.35 drivers and V.35 receivers, or when V.11 receivers are used. The SP509 provides the controls and transceiver availability for operating as either a DTE or DCE. Additional features with the SP509 include internal loopback that can be initiated in any of the operating modes by use of the LOOPBACK pin. While in loopback mode, receiver outputs are internally connected to driver inputs creating an internal signal path bypassing the serial communications controller for diagnostic testing. The SP509 also includes a latch enable pin with the driver and receiver address decoder. The internal V.11 or V.35 receiver termination can be switched off using a control pin (TERM_OFF) for monitoring applications. All eight (8) drivers and receivers in the SP509 include separate enable pins for added convenience. The SP509 is ideal for WAN serial ports in networking equipment such as routers, concentrators, network muxes, DSU/CSU's, networking test equipment, and other access devices. Applicable U.S. Patents-5,306,954; and others patents pending Date: 1/19/05 SP509 Enhanced WAN Multi–Protocol Serial Transceiver © Copyright 2005 Sipex Corporation 1 ABSOLUTE MAXIMUM RATINGS These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. VCC ................................................................................................ +7V Input Voltages: Logic ................................................ -0.3V to (VCC+0.5V) Drivers ............................................. -0.3V to (VCC+0.5V) Receivers ........................................................... ±15.5V Output Voltages: Logic ................................................ -0.3V to (VCC+0.5V) Drivers ................................................................... ±12V Receivers ........................................ -0.3V to (VCC+0.5V) Storage Temperature ................................................ -65°C to +150°C Power Dissipation ................................................................. 1520mW (derate 19.0mW/°C above +70°C) STORAGE CONSIDERATIONS Due to the relatively large package size of the 100-pin quad flatpack, storage in a low humidity environment is preferred. Large high density plastic packages are moisture sensitive and should be stored in Dry Vapor Barrier Bags. Prior to usage, the parts should remain bagged and stored below 40°C and 60%RH. If the parts are removed from the bag, they should be used within 48 hours or stored in an environment at or below 20%RH. If the above conditions cannot be followed, the parts should be baked for four hours at 125°C in order to remove moisture prior to soldering. Sipex ships the 100-pin LQFP in Dry Vapor Barrier Bags with a humidity indicator card and desiccant pack. The humidity indicator should be below 30%RH. Package Derating: øJA ................................................................................................................. 52.7 °C/W øJC .................................................................................................................... 6.5 °C/W ELECTRICAL SPECIFICATIONS TA = +25°C and VCC = +4.75V to +5.25V unless otherwise noted. MIN. TYP. MAX. 0.8 UNITS Volts Volts Volts Volts CONDITIONS LOGIC INPUTS VIL VIH 2.0 0.4 2.4 LOGIC OUTPUTS VOL VOH IOUT= –3.2mA IOUT= 1.0mA V.28 DRIVER DC Parameters Outputs Open Circuit Voltage Loaded Voltage Short-Circuit Current Power-Off Impedance AC Parameters Outputs Transition Time Instantaneous Slew Rate Propagation Delay tPHL tPLH Max.Transmission Rate ±15 ±15 ±100 Volts Volts mA Ω µs V/µs µs µs kbps per Figure 1 per Figure 2 per Figure 4, VOUT=0V per Figure 5 VCC = +5V for AC parameters per Figure 6; +3V to -3V per Figure 3 ±5.0 300 1.5 30 0.5 0.5 120 1 1 230 5 5 V.28 RECEIVER DC Parameters Inputs Input Impedance Open-Circuit Bias HIGH Threshold LOW Threshold AC Parameters Propagation Delay tPHL tPLH 3 0.8 50 50 1.7 1.2 100 100 7 +2.0 3.0 kΩ Volts Volts Volts ns ns per Figure 7 per Figure 8 VCC = +5V for AC parameters 500 500 Date: 1/19/05 SP509 Enhanced WAN Multi–Protocol Serial Transceiver © Copyright 2005 Sipex Corporation 2 ELECTRICAL SPECIFICATIONS TA = +25°C and VCC = +4.75V to +5.25V unless otherwise noted. MIN. TYP. MAX. UNITS CONDITIONS V.28 RECEIVER (continued) AC Parameters (cont.) Max.Transmission Rate 120 235 kbps V.10 DRIVER DC Parameters Outputs Open Circuit Voltage Test-Terminated Voltage Short-Circuit Current Power-Off Current AC Parameters Outputs Transition Time Propagation Delay tPHL tPLH Max.Transmission Rate ±4.0 0.9VOC ±6.0 ±150 ±100 200 30 30 120 100 100 500 500 Volts Volts mA µA ns ns ns kbps per Figure 9 per Figure 10 per Figure 11 per Figure 12 VCC = +5V for AC parameters per Figure 13; 10% to 90% V.10 RECEIVER DC Parameters Inputs Input Current Input Impedance Sensitivity AC Parameters Propagation Delay tPHL tPLH Max.Transmission Rate –3.25 4 +3.25 ±0.3 50 50 120 mA kΩ Volts ns ns kbps per Figures 14 and 15 VCC = +5V for AC parameters V.11 DRIVER DC Parameters Outputs Open Circuit Voltage Test Terminated Voltage Balance Offset Short-Circuit Current Power-Off Current AC Parameters Outputs Transition Time Propagation Delay tPHL tPLH Differential Skew (|tPHL - tPLH|) Max.Transmission Rate Channel to Channel Skew ±6.0 ±2.0 0.5VOC 0.67VOC ±0.4 +3.0 ±150 ±100 10 30 30 2 40 2 50 50 5 Volts Volts Volts Volts Volts mA µA ns ns ns ns Mbps ns per Figure 16 per Figure 17 per Figure 17 per Figure 17 per Figure 18 per Figure 19 VCC = +5V for AC parameters per Figures 21 and 36; 10% to 90% Using CL = 50pF; per Figures 33 and 36 per Figures 33 and 36 per Figures 33 and 36 V.11 RECEIVER DC Parameters Inputs Common Mode Range Sensitivity –7 +7 ±0.2 Volts Volts Date: 1/19/05 SP509 Enhanced WAN Multi–Protocol Serial Transceiver © Copyright 2005 Sipex Corporation 3 ELECTRICAL SPECIFICATIONS TA = +25°C and VCC = +4.75V to +5.25V unless otherwise noted. MIN. TYP. MAX. UNITS CONDITIONS V.11 RECEIVER (continued) DC Parameters (cont.) Input Current Current w/100Ω Termination Input Impedance AC Parameters Propagation Delay tPHL tPLH Skew (|tPHL - tPLH|) Max.Transmission Rate Channel to Channel Skew –3.25 4 30 30 2 40 2 50 50 5 ±3.25 ±60.75 mA mA kΩ ns ns ns Mbps ns per Figure 20 and 22; power on or off per Figure 23 and 24 VCC = +5V for AC parameters Using CL = 50pF; per Figures 33 and 38 per Figures 33 and 38 per Figure 33 V.35 DRIVER DC Parameters Outputs Test Terminated Voltage ±0.44 Offset Output Overshoot -0.2VST Source Impedance 50 Short-Circuit Impedance 135 AC Parameters Outputs Transition Time Propagation Delay tPHL tPLH Differential Skew (|tPHL - tPLH|) Max.Transmission Rate 40 Channel to Channel Skew ±0.66 ±0.6 +0.2VST 150 165 7 30 30 2 2 20 50 50 5 Volts Volts Volts Ω Ω ns ns ns ns Mbps ns per Figure 25 per Figure 25 per Figure 25; VST = Steady state value per Figure 27; ZS = V2/V1 x 50 per Figure 28 VCC = +5V for AC parameters per Figure 29; 10% to 90% per Figures 33 and 36; CL = 20pF per Figures 33 and 36; CL = 20pF per Figures 33 and 36; CL = 20pF V.35 RECEIVER DC Parameters Inputs Sensitivity Source Impedance Short-Circuit Impedance AC Parameters Propagation Delay tPHL tPLH Skew (|tPHL - tPLH|) Max.Transmission Rate Channel to Channel Skew Driver Output 3-State Current Rcvr Output 3-State Current ±50 90 135 30 30 2 40 2 500 1 4.75 5.00 1 95 230 270 170 200 +100 110 165 50 50 5 mV Ω Ω ns ns ns Mbps ns µA µA Volts µA mA mA mA mA mA per Figure 30; ZS = V2/V1 x 50Ω per Figure 31 VCC = +5V for AC parameters per Figures 33 and 38; CL = 20pF per Figures 33 and 38; CL = 20pF per Figure 33; CL = 20pF TRANSCEIVER LEAKAGE CURRENT 10 5.25 per Figure 32; Drivers disabled TX & RX disabled, 0.4V - VO - 2.4V POWER REQUIREMENTS VCC ICC (Shutdown Mode) (V.28/RS-232) (V.11/RS-422) (EIA-530 & RS-449) (V.35) (EIA-530A) All ICC values are with VCC = +5V fIN = 120kbps; Drivers active & loaded fIN = 10Mbps; Drivers active & loaded fIN = 10Mbps; Drivers active & loaded V.35 @ fIN = 10Mbps, V.28 @ 20kbps fIN = 10Mbps; Drivers active & loaded Date: 1/19/05 SP509 Enhanced WAN Multi–Protocol Serial Transceiver © Copyright 2005 Sipex Corporation 4 OTHER AC CHARACTERISTICS TA = +25°C and VCC = +5.0V unless otherwise noted. PARAMETER MIN. TYP. MAX. UNITS DRIVER DELAY TIME BETWEEN ACTIVE MODE AND TRI-STATE MODE RS-232/V.28 tPZL; Tri-state to Output LOW 0.11 5.0 µs tPZH; Tri-state to Output HIGH tPLZ; Output LOW to Tri-state tPHZ; Output HIGH to Tri-state RS-423/V.10 tPZL; Tri-state to Output LOW tPZH; Tri-state to Output HIGH tPLZ; Output LOW to Tri-state tPHZ; Output HIGH to Tri-state RS-422/V.11 tPZL; Tri-state to Output LOW tPZH; Tri-state to Output HIGH tPLZ; Output LOW to Tri-state tPHZ; Output HIGH to Tri-state V.35 tPZL; Tri-state to Output LOW tPZH; Tri-state to Output HIGH tPLZ; Output LOW to Tri-state tPHZ; Output HIGH to Tri-state 0.11 0.05 0.05 2.0 2.0 2.0 µs µs µs CONDITIONS CL = 100pF, Fig. 34 & 40; S2 closed CL = 100pF, Fig. 34 & 40; S2 closed CL = 100pF, Fig. 34 & 40; S2 closed CL = 100pF, Fig. 34 & 40; S2 closed CL = 100pF, Fig. 34 & 40; S2 closed CL = 100pF, Fig. 34 & 40; S2 closed CL = 100pF, Fig. 34 & 40; S2 closed CL = 100pF, Fig. 34 & 40; S2 closed CL = 100pF, Fig. 34 & 37; S1 closed CL = 100pF, Fig. 34 & 37; S2 closed CL = 15pF, Fig. 34 & 37; S1 closed CL = 15pF, Fig. 34 & 37; S2 closed CL = 100pF, Fig. 34 & 37; S1 closed CL = 100pF, Fig. 34 & 37; S2 closed CL = 15pF, Fig. 34 & 37; S1 closed CL = 15pF, Fig. 34 & 37; S2 closed 0.07 0.05 0.55 0.12 2.0 2.0 2.0 2.0 µs µs µs µs 0.04 0.05 0.03 0.11 10.0 2.0 2.0 2.0 µs µs µs µs 0.85 0.36 0.06 0.05 10.0 2.0 2.0 2.0 µs µs µs µs RECEIVER DELAY TIME BETWEEN ACTIVE MODE AND TRI-STATE MODE RS-232/V.28 tPZL; Tri-state to Output LOW 0.05 2.0 µs CL = 100pF, Fig. 35 & 40; S1 closed tPZH; Tri-state to Output HIGH 0.05 2.0 µs CL = 100pF, Fig. 35 & 40; S2 closed tPLZ; Output LOW to Tri-state 0.65 2.0 µs CL = 100pF, Fig. 35 & 40; S1 closed tPHZ; Output HIGH to Tri-state 0.65 2.0 µs CL = 100pF, Fig. 35 & 40; S2 closed RS-423/V.10 tPZL; Tri-state to Output LOW 0.04 2.0 µs CL = 100pF, Fig. 35 & 40; S1 closed tPZH; Tri-state to Output HIGH 0.03 2.0 µs CL = 100pF, Fig. 35 & 40; S2 closed tPLZ; Output LOW to Tri-state 0.03 2.0 µs CL = 100pF, Fig. 35 & 40; S1 closed tPHZ; Output HIGH to Tri-state 0.03 2.0 µs CL = 100pF, Fig. 35 & 40; S2 closed Date: 1/19/05 SP509 Enhanced WAN Multi–Protocol Serial Transceiver © Copyright 2005 Sipex Corporation 5 OTHER AC CHARACTERISTICS (Continued) TA = +25°C and VCC = +5.0V unless otherwise noted. PARAMETER RS-422/V.11 tPZL; Tri-state to Output LOW tPZH; Tri-state to Output HIGH tPLZ; Output LOW to Tri-state tPHZ; Output HIGH to Tri-state V.35 tPZL; Tri-state to Output LOW tPZH; Tri-state to Output HIGH tPLZ; Output LOW to Tri-state tPHZ; Output HIGH to Tri-state MIN. TYP. 0.04 0.03 0.03 0.03 MAX. 2.0 2.0 2.0 2.0 UNITS µs µs µs µs CONDITIONS CL = 100pF, Fig. 35 & 39; S1 closed CL = 100pF, Fig. 35 & 39; S2 closed CL = 15pF, Fig. 35 & 39; S1 closed CL = 15pF, Fig. 35 & 39; S2 closed CL = 100pF, Fig. 35 & 39; S1 closed CL = 100pF, Fig. 35 & 39; S2 closed CL = 15pF, Fig. 35 & 39; S1 closed CL = 15pF, Fig. 35 & 39; S2 closed 0.04 0.03 0.03 0.03 2.0 2.0 2.0 2.0 µs µs µs µs TRANSCEIVER TO TRANSCEIVER SKEW RS-232 Driver 100 100 RS-232 Receiver 20 20 RS-422 Driver 2 2 RS-422 Receiver 2 3 RS-423 Driver 5 5 RS-423 Receiver 5 5 V.35 Driver V.35 Receiver 2 2 2 2 (per Figures 32, 33, 36, 38) ns [ (tphl )Tx1 – (tphl )Txn ] ns [ (tplh )Tx1 – (tplh )Txn] ns [ (tphl )Rx1 – (tphl )Rxn ] ns [ (tphl )Rx1 – (tphl )Rxn ] ns [ (tphl )Tx1 – (tphl )Txn ] ns [ (tplh )Tx1 – (tplh )Txn ] ns [ (tphl )Rx1 – (tphl )Rxn ] ns [ (tphl )Rx1 – (tphl )Rxn ] ns [ (tphl )Tx2 – (tphl )Txn ] ns [ (tplh )Tx2 – (tplh )Txn ] ns [ (tphl )Rx2 – (tphl )Rxn ] ns [ (tphl )Rx2 – (tphl )Rxn ] ns ns ns ns [ (tphl )Tx1 – (tphl )Txn ] [ (tplh )Tx1 – (tplh )Txn ] [ (tphl )Rx1 – (tphl )Rxn ] [ (tphl )Rx1 – (tphl )Rxn] Date: 1/19/05 SP509 Enhanced WAN Multi–Protocol Serial Transceiver © Copyright 2005 Sipex Corporation 6 PINOUT 100 PIN LQFP 99 V35TGND1 94 V35TGND2 89 V35TGND3 81 RRC(a) 79 RRC(b) 100 SD(b) 97 SD(a) 85 RS(b) 83 RS(a) 90 ST(b) 87 ST(a) 95 TT(b) 92 TT(a) 78 TR(b) 96 GND 91 GND 86 GND 82 GND 98 VCC 93 VCC 88 VCC 84 VCC 80 VCC 77 VCC 76 N/C VCC 1 GND 2 SDEN 3 TTEN 4 STEN 5 RSEN 6 TREN 7 RRCEN 8 RLEN 9 LLEN 10 RDEN 11 RTEN 12 TXCEN 13 CSEN 14 DMEN 15 RRTEN 16 ICEN 17 TMEN 18 D0 19 D1 20 D2 21 TERM_OFF 22 D_LATCH 23 N/C 24 GND 25 ® 75 TR(a) 74 GND 73 VDD 72 C1+ 71 VCC 70 C2+ 69 C168 GND 67 C266 VSS 65 RL(a) 64 VCC 63 LL(a) 62 TM(a) 61 IC(a) SP509 60 RRT(a) 59 RRT(b) 58 V10GND 57 DM(a) 56 DM(b) 55 CS(a) 54 CS(b) 53 TXC(a) 52 GND 51 TXC(b) ST 30 RTS 31 LOOPBACK 27 TXD 28 TXCE 29 TXC 38 CTS 39 TM 43 RI 42 RT(b) 49 RD(b) 47 DCD_DTE 41 Date: 1/19/05 SP509 Enhanced WAN Multi–Protocol Serial Transceiver DCD_DCE 33 V35RGND 46 RD(a) 48 RT(a) 50 DTR 32 LL 35 RL 34 RXD 36 RXC 37 DSR 40 VCC 26 GND 44 VCC 45 © Copyright 2005 Sipex Corporation 7 PIN DESCRIPTION Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Pin Name VCC GND SDEN TTEN STEN RSEN TREN RRCEN RLEN LLEN# RDEN# RTEN# TxCEN# CSEN# DMEN# RRTEN# ICEN# TMEN D0 D1 D2 D_LATCH# NC GND VCC TxD TxCE ST RTS DTR DCD_DCE RL LL RxD RxC TxC CTS DSR DCD_DTE RI TM GND VCC V35RGND RD(b) RD(a) RT(b) RT(a) Description 5V Power Supply Input Signal Ground TxD Driver Enable Input TxCE Driver Enable Input ST Driver Enable Input RTS Driver Enable Input DTR Driver Enable Input DCD Driver Enable Input RL Driver Enable Input LL Driver Enable Input RxD Receiver Enable Input RxC Receiver Enable Input TxC Receiver Enable Input CTS Receiver Enable Input DSR Receiver Enable Input DCDDTE Receiver Enable Input RI Receiver Enable Input TM Receiver Enable Input Mode Select Input Mode Select Input Mode Select Input Decoder Latch Input No Connect Signal Ground 5V Power Supply Input TxD Driver TTL Input TxCE Driver TTL Input ST Driver TTL Input RTS Driver TTL Input DTR Driver TTL Input DCDDCE Driver TTL Input RL Driver TTL Input LL Driver TTL Input RxD Receiver TTL Output RxC Receiver TTLOutput TxC Receiver TTL Output CTS Receiver TTL Output DSR Receiver TTL Output DCDDTE Receiver TTL Output RI Receiver TTL Output TM Receiver TTL Output Signal Ground Power Supply Input Reciever Termination Refrence RXD Non-Inverting Input RXD Inverting Input RxC Non-Inverting Input RxC Inverting Input Pin Number 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Pin Name TxC(b) GND TxC(a) CS(b) CS(a) DM(b) DM(a) GNDV10 RRT(b) RRT(a) IC TM(a) LL(a) VCC RL(a) VSS1 C2N GND C1N C2P VCC C1P VDD GND TR(a) NC VCC TR(b) RRC(b) VCC RRC(a) GND RS(a) VCC RS(b) GND ST(a) VCC ST(b) GND TT(a) VCC TT(b) GND SD(a) VCC SD(b) Description TxC Non-Inverting Input Signal Ground TxC Inverting Input CTS Non-Inverting Input CTS Inverting Input DSR Non-Inverting Input DSR Inverting Input V.10 Rx Reference Node DCDDTE Non-Inverting Input DCDDTE Inverting Input RI Receiver Input TM Receiver Input LL Driver Output Power Supply Input RL Driver Output -2xVCC Charge Pump Output Charge Pump Capacitor Signal Ground Charge Pump Capacitor Charge Pump Capacitor Power Supply Input Charge Pump Capacitor 2xVCC Charge Pump Output Signal Ground DTR Inverting Output No Connect Power Supply Input DTR Non-Inverting Output DCD Non-Inverting Output Power Supply Input DCD Inverting Output Signal Ground RTS Inverting Output Power Supply Input RTS Non-Inverting Output Signal Ground ST Inverting Output Power Supply Input ST Non-Inverting Output Signal Ground TxCE Inverting Output 5V Power Supply Input TxCE Non-Inverting Output Signal Ground TxD Inverting Output 5V Power Supply Input TxD Non-Inverting Output TERM_OFF Termination Disable Input LOOPBACK# Loopback Mode Enable Input V35TGND3 ST Termination Referance V35TGND2 ST Termination Referance V35TGND1 ST Termination Referance Date: 1/19/05 SP509 Enhanced WAN Multi–Protocol Serial Transceiver © Copyright 2005 Sipex Corporation 8 SP509 Driver Table Driver Output Pin MODE (D0, D1, D2) T1OUT(a) T1OUT(b) T2OUT(a) T2OUT(b) T3OUT(a) T3OUT(b) T4OUT(a) T4OUT(b) T5OUT(a) T5OUT(b) T6OUT(a) T6OUT(b) T7OUT(a) T8OUT(a) V.35 Mode 001 V.35 V.35 V.35 V.35 V.35 V.35 V.28 High-Z V.28 High-Z V.28 High-Z V.28 V.28 EIA-530 Mode 010 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.10 V.10 RS-232 Mode (V.28) 011 V.28 High-Z V.28 High-Z V.28 High-Z V.28 High-Z V.28 High-Z V.28 High-Z V.28 V.28 EIA-530A Mode 100 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.10 High-Z V.11 V.11 V.10 V.10 RS-449 Mode (V.36) 101 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.10 V.10 X.21 Mode (V.11) 110 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 High-Z High-Z Shutdown 111 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z TxD(a) TxD(b) TxCE(a) TxCE(b) TxC_DCE(a) TxC_DCE(b) RTS(a) RTS(b) DTR(a) DTR(b) DCD_DCE(a) DCD_DCE(b) RL LL Suggested Signal Table 1. Driver Mode Selection SP509 Receiver Table Receiver Input Pin MODE (D0, D1, D2) R1IN(a) R1IN(b) R2IN(a) R2IN(b) R3IN(a) R3IN(b) R4IN(a) R4IN(b) R5IN(a) R5IN(b) R6IN(a) R6IN(b) R7IN(a) R8IN(a) V.35 Mode 001 V.35 V.35 V.35 V.35 V.35 V.35 V.28 High-Z V.28 High-Z V.28 High-Z V.28 V.28 EIA-530 Mode 010 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.10 V.10 RS-232 Mode (V.28) 011 V.28 High-Z V.28 High-Z V.28 High-Z V.28 High-Z V.28 High-Z V.28 High-Z V.28 V.28 EIA-530A Mode 100 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.10 High-Z V.11 V.11 V.10 V.10 RS-449 Mode (V.36) 101 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.10 V.10 X.21 Mode (V.11) 110 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 High-Z High-Z Shutdown 111 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z RxD(a) RxD(b) RxC(a) RxC(b) TxC_DTE(a) TxC_DTE(b) CTS(a) CTS(b) DSR(a) DSR(b) DCD_DTE(a) DCD_DTE(b) RI TM Suggested Signal Table 2. Receiver Mode Selection Date: 1/19/05 SP509 Enhanced WAN Multi–Protocol Serial Transceiver © Copyright 2005 Sipex Corporation 9 TEST CIRCUITS A A VOC 3kΩ VT C C Figure 1. V.28 Driver Output Open Circuit Voltage Figure 2. V.28 Driver Output Loaded Voltage A A 7kΩ VT Oscilloscope Isc C Scope used for slew rate measurement. C Figure 3. V.28 Driver Output Slew Rate Figure 4. V.28 Driver Output Short-Circuit Current VCC = 0V A Ix A ±2V 3kΩ 2500pF Oscilloscope C C Figure 5. V.28 Driver Output Power-Off Impedance Figure 6. V.28 Driver Output Rise/Fall Times Date: 1/19/05 SP509 Enhanced WAN Multi–Protocol Serial Transceiver © Copyright 2005 Sipex Corporation 10 A Iia ±15V A voc C C Figure 7. V.28 Receiver Input Impedance Figure 8. V.28 Receiver Input Open Circuit Bias A A 3.9kΩ VOC 450Ω Vt C C Figure 9. V.10 Driver Output Open-Circuit Voltage Figure 10. V.10 Driver Output Test Terminated Voltage VCC = 0V A A Ix ±0.25V Isc C C Figure 11. V.10 Driver Output Short-Circuit Current Figure 12. V.10 Driver Output Power-Off Current Date: 1/19/05 SP509 Enhanced WAN Multi–Protocol Serial Transceiver © Copyright 2005 Sipex Corporation 11 A A Iia ±10V 450Ω Oscilloscope C C Figure 13. V.10 Driver Output Transition Time Figure 14. V.10 Receiver Input Current A V.10 RECEIVER +3.25mA 3.9kΩ VOC VOCA VOCB -10V -3V +3V +10V C B Maximum Input Current vesus Voltage -3.25mA Figure 15. V.10 Receiver Input IV Graph Figure 16. V.11 Driver Output Open-Circuit Voltage A A Isa 50Ω VT 50Ω Isb B VOS B C C Figure 17. V.11 Driver Output Test Terminated Voltage Figure 18. V.11 Driver Output Short-Circuit Current Date: 1/19/05 SP509 Enhanced WAN Multi–Protocol Serial Transceiver © Copyright 2005 Sipex Corporation 12 VCC = 0V A Iia A Ixa ±0.25V ±10V B B C C VCC = 0V A A ±10V ±0.25V Ixb B Iib B C C Figure 19. V.11 Driver Output Power-Off Current Figure 20. V.11 Receiver Input Current A V.11 RECEIVER 50Ω Oscilloscope +3.25mA 50Ω -10V B 50Ω VE -3V +3V +10V C Maximum Input Current vesus Voltage -3.25mA Figure 21. V.11 Driver Output Rise/Fall Time Figure 22. V.11 Receiver Input IV Graph Date: 1/19/05 SP509 Enhanced WAN Multi–Protocol Serial Transceiver © Copyright 2005 Sipex Corporation 13 V.11 RECEIVER A Iia ±6V w/ Optional Cable Termination (100Ω to 150Ω) i [mA] = V [V] / 0.1 100Ω to 150Ω i [mA] = V [V] - 3) / 4.0 -6V -3V +3V +6V B i [mA] = V [V] - 3) / 4.0 C i [mA] = V [V] / 0.1 Maximum Input Current versus Voltage Figure 24. V.11 Receiver Input Graph w/ Termination A A ±6V 50Ω VT 50Ω 100Ω to 150Ω Iib B B VOS C C Figure 23. V.11 Receiver Input Current w/ Termination Figure 25. V.35 Driver Output Test Terminated Voltage A V1 A 50Ω VT 50Ω VOS 50Ω 24kHz, 550mVp-p Sine Wave V2 B B C C Figure 26. V.35 Driver Output Offset Voltage Figure 27. V.35 Driver Output Source Impedance Date: 1/19/05 SP509 Enhanced WAN Multi–Protocol Serial Transceiver © Copyright 2005 Sipex Corporation 14 A A 50Ω Oscilloscope B ISC 50Ω B 50Ω ±2V C C Figure 28. V.35 Driver Output Short-Circuit Impedance Figure 29. V.35 Driver Output Rise/Fall Time V1 A 50Ω 24kHz, 550mVp-p Sine Wave A V2 B Isc B ±2V C C Figure 30. V.35 Receiver Input Source Impedance Figure 31. V.35 Receiver Input Short-Circuit Impedance Any one of the three conditions for disabling the driver. VCC = 0V 1 1 1 D2 D1 D0 A IZSC ±12V CL1 TIN B A CL2 VCC B ROUT A 15pF Logic “1” B fIN (50% Duty Cycle, 2.5VP-P) Figure 32. Driver Output Leakage Current Test Figure 33. Driver/Receiver Timing Test Circuit Date: 1/19/05 SP509 Enhanced WAN Multi–Protocol Serial Transceiver © Copyright 2005 Sipex Corporation 15 Output Under Test 500Ω CL S1 VCC Receiver Output CRL Test Point S1 1KΩ S2 1KΩ VCC S2 Figure 34. Driver Timing Test Load Circuit Figure 35. Receiver Timing Test Load Circuit f > 10MHz; tR < 10ns; tF < 10ns DRIVER INPUT +3V 1.5V 0V A B tDPLH DIFFERENTIAL OUTPUT VB – VA VO+ 0V VO– tDPHL VO 1/2VO tPLH tPHL 1/2VO 1.5V DRIVER OUTPUT tR tF tSKEW = | tDPLH - tDPHL | Figure 36. Driver Propagation Delays Mx or Tx_Enable +3V 1.5V 0V 5V tZL 2.3V VOL VOH Output normally LOW 1.5V tLZ 0.5V 0.5V tHZ A, B A, B 0V 2.3V tZH Output normally HIGH Figure 37. Driver Enable and Disable Times f > 10MHz; tR < 10ns; tF < 10ns V0D2+ A–B V0D2– VOH RECEIVER OUT VOL tSKEW = | tPHL - tPLH | Figure 38. Receiver Propagation Delays 0V INPUT OUTPUT (VOH - VOL)/2 0V (VOH - VOL)/2 tPHL tPLH Date: 1/19/05 SP509 Enhanced WAN Multi–Protocol Serial Transceiver © Copyright 2005 Sipex Corporation 16 f = 1MHz; tR < 10ns; tF < 10ns DECx +3V 1.5V RCVRENABLE RECEIVER OUT VIL VIH RECEIVER OUT 0V 1.5V tZH Output normally HIGH 0V 5V 1.5V Output normally LOW 0.5V 0.5V tHZ tZL 1.5V tLZ Figure 39. Receiver Enable and Disable Times +3V Tx_Enable 0V 0V TOUT VOL f = 60kHz; tR < 10ns; tF < 10ns 1.5V tZL VOL - 0.5V Output LOW 1.5V tLZ VOL - 0.5V +3V Tx_Enable 0V VOH TOUT 0V f = 60kHz; tR < 10ns; tF < 10ns 1.5V tZH Output HIGH 1.5V tHZ VOH - 0.5V Figure 40. V.28 (RS-232) and V.10 (RS-423) Driver Enable and Disable Times Date: 1/19/05 SP509 Enhanced WAN Multi–Protocol Serial Transceiver © Copyright 2005 Sipex Corporation 17 Figure 41. Typical V.28 Driver Output Waveform Figure 42. Typical V.10 Driver Output Waveform Figure 43. Typical V.11 Driver Output Waveform Figure 44. Typical V.35 Driver Output Waveform Figure 45. Typical V.11 Driver Output Waveform at 20MHz Figure 46. Typical V.35 Driver Output Waveform at 20 MHz Date: 1/19/05 SP509 Enhanced WAN Multi–Protocol Serial Transceiver © Copyright 2005 Sipex Corporation 18 +5V (decoupling capacitor not shown) 1µF 1µF 1µF VCC VDD C1+ C1- C2+ C2- VSS Regulated Charge Pump 1µF V35RGND RD(a) RxD RDEN RD(b) RT(a) RxC RTEN RT(b) TxC(a) TxC TxCEN TxC(b) CS(a) CTS CSEN CS(b) DM(a) DSR DMEN DM(b) RRT(a) DCD_DTE RRTEN RRT(b) IC RI ICEN TxD SD(a) V35TGND1 SD(b) SDEN TxCE TT(a) V35TGND2 TT(b) TTEN ST ST(a) V35TGND3 ST(b) STEN RTS RS(a) RS(b) RSEN DTR TR(a) TR(b) TREN DCD_DCE RRC(a) RRC(b) RRCEN RL RL(a) RLEN TM TM TMEN LL LL(a) LLEN D0 D1 D2 D-LATCH TERM-OFF LOOPBACK GND SP509 V.10-GND RECEIVER TERMINATION NETWORK V.35 MODE V.11 MODE RX ENABLE 51ohms 51ohms 124ohms V.35 DRIVER TERMINATION NETWORK 51ohms V.35 MODE TX ENABLE 51ohms 124ohms Figure 47. Functio nal Diagram Date: 1/19/05 SP509 Enhanced WAN Multi–Protocol Serial Transceiver © Copyright 2005 Sipex Corporation 19 The SP509 contains highly integrated serial transceivers that offer programmability between interface modes through software control. The SP509 offers the hardware interface modes for RS-232 (V.28), RS-449/V.36 (V.11 and V.10), EIA-530 (V.11 and V.10), EIA-530A (V.11 and V.10), V.35 (V.35 and V.28) and X.21(V.11). The interface mode selection is done via three control pins, which can be latched via microprocessor control. The SP509 has eight drivers, eight receivers, and Sipex's patented on-board charge pump (5,306,954) that is ideally suited for wide area network connectivity and other multi-protocol applications. Other features include digital and line loopback modes, individual enable/disable control lines for each driver and receiver, fail-safe when inputs are either open or shorted, individual termination resistor ground paths, separate driver and receiver ground outputs, enhanced ESD protection on driver outputs and receiver inputs. THEORY OF OPERATION The SP509 device is made up of 1) the drivers, 2) the receivers, 3) a charge pump, 4) DTE/DCE switching algorithm, and 5) control logic. Drivers The SP509 has eight enhanced independent drivers. Control for the mode selection is done via a threebit control word into D0, D1, and D2. The drivers are prearranged such that for each mode of operation, the relative position and functionality of the drivers are set up to accommodate the selected interface mode. As the mode of the drivers is changed, the electrical characteristics will change to support the required signal levels. The mode of each driver in the different interface modes that can be selected is shown in Table 1. FEATURES There are four basic types of driver circuits – ITU-T-V.28 (RS-232), ITU-T-V.10 (RS-423), ITU-T-V.11 (RS-422), and CCITT-V.35. The V.28 (RS-232) drivers output single-ended signals with a minimum of +5V (with 3kΩ & 2500pF loading), and can operate over 120kbps. Since the SP509 uses a charge pump to generate the RS-232 output rails, the driver outputs will never exceed +10V. The V.28 driver architecture is similar to Sipex's standard line of RS-232 transceivers. The RS-423 (V.10) drivers are also single-ended signals which produce open circuit VOL and VOH measurements of +4.0V to +6.0V. When terminated with a 450Ω load to ground, the driver output will not deviate more than 10% of the open circuit value. This is in compliance of the ITU V.10 specification. The V.10 (RS-423) drivers are used in RS-449/V.36, EIA-530, and EIA-530A modes as Category II signals from each of their corresponding specifications. The V.10 drivers are guaranteed to transmit over 120kbps, but can operate at over 1Mbps if necessary. The third type of drivers are V.11 (RS-422) differential drivers. Due to the nature of differential signaling, the drivers are more immune to noise as opposed to single-ended transmission methods. The advantage is evident over high speeds and long transmission lines. The strength of the driver outputs can produce differential signals that can maintain +2V differential output levels with a load of 100Ω. The signal levels and drive capability of these drivers allow the drivers to also support RS-485 requirements of +1.5V differential output levels with a 54Ω load. The strength allows the SP509 differential driver to drive over long cable lengths with minimal signal degradation. The V.11 drivers are used in RS-449, EIA-530, EIA-530A and V.36 modes as Category I signals which are used for clock and data. Sipex's new driver design over its predecessors allow the SP509 to operate over 40Mbps for differential transmission. Date: 1/19/05 SP509 Enhanced WAN Multi–Protocol Serial Transceiver © Copyright 2005 Sipex Corporation 20 The fourth type of drivers are V.35 differential drivers. There are only three available on the SP509 for data and clock (TxD, TxCE, and TxC in DCE mode). These drivers are current sources that drive loop current through a differential pair resulting in a 550mV differential voltage at the receiver. These drivers also incorporate fixed termination networks for each driver in order to set the VOH and VOL depending on load conditions. This termination network is basically a “Y” configuration consisting of two 51Ω resistors connected in series and a 124Ω resistor connected between the two 50Ω resistors and a V35TGND output. Each of the three drivers and its associated termination will have its own V35TGND output for grounding convenience. Filtering can be done on these pins to reduce common mode noise transmitted over the transmission line by connecting a capacitor to ground. The drivers also have separate enable pins which simplifies half-duplex configurations for some applications, especially programmable DTE/DCE. The enable pins will either enable or disable the output of the drivers according to the appropriate active logic illustrated on Figure 47. The enable pins have internal pull-up and pulldown devices, depending on the active polarity of the receiver, that enable the driver upon poweron if the enable lines are left floating. During disabled conditions, the driver outputs will be at a high impedance 3-state. The driver inputs are both TTL or CMOS compatible. All driver inputs have an internal pull-up resistor so that the output will be at a defined state at logic LOW (“0”). Unused driver inputs can be left floating. The internal pull-up resistor value is approximately 500kΩ. Receivers The SP509 has eight enhanced independent receivers. Control for the mode selection is done via a three-bit control word that is the same as the driver control word. Therefore, the modes for the drivers and receivers are identical in the application. Like the drivers, the receivers are prearranged for the specific requirements of the synchronous serial interface. As the operating mode of the receivers is changed, the electrical characteristics will change to support the required serial interface Date: 1/19/05 protocols of the receivers. Table 1 shows the mode of each receiver in the different interface modes that can be selected. There are two basic types of receiver circuits—ITU-T-V .28 (RS-232) and ITU-T-V.11, (RS-422). The RS-232 (V.28) receiver is single-ended and accepts RS-232 signals from the RS-232 driver. The RS-232 receiver has an operating input voltage range of +15V and can receive signals downs to +3V. The input sensitivity complies with RS-232 and V .28 at +3V. The input impedance is 3kΩ to 7kΩ in accordance to RS232 and V .28. The receiver output produces a TTL/CMOS signal with a +2.4V minimum for a logic “1” and a +0.4V maximum for a logic “0”. The RS-232 (V.28) protocol uses these receivers for all data, clock and control signals. They are also used in V.35 mode for control line signals: CTS, DSR, LL, and RL. The RS-232 receivers can operate over 120kbps. The second type of receiver is a differential type that can be configured internally to support ITU-T-V.10 and CCITT-V.35 depending on its input conditions. This receiver has a typical input impedance of 10kΩ and a differential threshold of less than +200mV, which complies with the ITU-T-V.11 (RS-422) specifications. V.11 receivers are used in RS-449/V.36, EIA-530, EIA-530A and X.21 as Category I signals for receiving clock, data, and some control line signals not covered by Category II V.10 circuits. The differential V.11 transceiver has improved architecture that allows over 40Mbps transmission rates. Receivers dedicated for data and clock (RxD, RxC, TxC) incorporate internal termination for V.11. The termination resistor is typically 120Ω connected between the A and B inputs. The termination is essential for minimizing crosstalk and signal reflection over the transmission line . The minimum value is guaranteed to exceed 100Ω, thus complying with the V.11 and RS-422 specifications. This resistor is invoked when the receiver is operating as a V.11 receiver, in modes EIA-530, EIA-530A, RS-449/V.36, and X.21. SP509 Enhanced WAN Multi–Protocol Serial Transceiver © Copyright 2005 Sipex Corporation 21 The same receivers also incorporate a termination network internally for V.35 applications. For V.35, the receiver input termination is a “Y” termination consisting of two 51Ω resistors connected in series and a 124Ω resistor connected between the two 50Ω resistors and V35RGND output. The V35RGND is usually grounded. The receiver itself is identical to the V.11 receiver. The differential receivers can be configured to be ITU-T-V.10 single-ended receivers by internally connecting the non-inverting input to ground. This is internally done by default from the decoder. The non-inverting input is rerouted to V10GND and can be grounded separately. The ITU-T-V.10 receivers can operate over 1Mbps and are used in RS-449/V.36, E1A-530, E1A-530A and X.21 modes as Category II signals as indicated by their corresponding specifications. All receivers include an enable/disable line for disabling the receiver output allowing convenient half-duplex configurations. The enable pins will either enable or disable the output of the receivers according to the appropriate active logic illustrated on Figure 47. The receiver’s enable lines include an internal pull-up or pull-down device, depending on the active polarity of the receiver, that enables the receiver upon power up if the enable lines are left floating. During disabled conditions, the receiver outputs will be at a high impedance state. If the receiver is disabled any associated termination is also disconnected from the inputs. All receivers include a fail-safe feature that outputs a logic high when the receiver inputs are open, terminated but open, or shorted together. For single-ended V.28 and V.10 receivers, there are internal 5kΩ pull-down resistors on the inputs which produces a logic high (“1”) at the receiver outputs. The differential receivers have a proprietary circuit that detect open or shorted inputs and if so, will produce a logic HIGH (“1”) at the receiver output. CHARGE PUMP The charge pump is a Sipex-patented design (5,306,954) and uses a unique approach compared to older less-efficient designs. The charge pump still requires four external capacitors, but uses four-phase voltage shifting technique to attain symmetrical power supplies. The charge pump VDD and VSS outputs are regulated to +5.8V and -5.8V, respectively. There is a free-running oscillator that controls the four phases of the voltage shifting. A description of each phase follows. Phase 1 __VSS charge storage ——During this phase of the clock cycle, the positive side of capacitors C1 and C2 are initially charged to VCC. C+ is then switched to ground and the charge in C1- is transferred to C2-. Since C2+ is connected to VCC, the voltage potential across capacitor C2 is now 2XVCC. Phase 2 —VSS transfer —Phase two of the clock connects the negative terminal of C2 to the VSS storage capacitor and the positive terminal of C2 to ground, and transfers the negative generated voltage to C3. This generated voltage is regulated to –5.8V. Simultaneously, the positive side of the capacitor C1 is switched to VCC and the negative side is connected to ground. Phase 3 —VDD charge storage —The third phase of the clock is identical to the first phase—the charge transferred in C1 produces –VCC in the negative terminal of C1 which is applied to the negative side of the capacitor C2 . Since C2+ is at VCC, the voltage potential across C2 is 2XVCC. Phase 4 —VDD transfer —The fourth phase of the clock connects the negative terminal of C2 to ground, and transfers the generated 5.8V across C2 to C4, the VDD storage capacitor. This voltage is regulated to +5.8V. At the regulated voltage, the internal oscillator is disabled and simultaneously with this, the positive side of capacitor C1 is switched to VCC and the negative side is connected to ground, and the cycle begins again. The charge pump cycle will continue as long as the operational conditions for the internal oscillator are present. © Copyright 2005 Sipex Corporation Date: 1/19/05 SP509 Enhanced WAN Multi–Protocol Serial Transceiver 22 Since both V+ and V- are separately generated from VCC; in a no-load condition V+ and V- will be symmetrical. Older charge pump approaches that generate V- from V+ will show a decrease in the magnitude of V- compared to V+ due to the inherent inefficiencies in the design. The clock rate for the charge pump typically operates at 250kHz. The external capacitors can be as low as 1µF with a 16V breakdown voltage rating. TERM_OFF FUNCTION The SP509 contains a TERM_OFF pin that disables all three receiver input termination networks regardless of mode. This allows the device to be used in monitor mode applications typically found in networking test equipment. The TERM_OFF pin internally contains a pull-down device with an impedance of over 500kΩ, which will default in a “ON” condition during power-up if V.35 receivers are used. The individual receiver enable line and the SHUTDOWN mode from the decoder will disable the termination regardless of TERM_OFF. LOOPBACK FUNCTION The SP509 contains a LOOPBACK pin that invokes a loopback path. This loopback path is illustrated in Figure 48. LOOPBACK has an internal pull-up resistor that defaults to normal mode during power up or if the pin is left floating. During loopback, the driver output and receiver input characteristics will still adhere to its appropriate specifications. DECODER AND D_LATCH FUNCTION The SP509 contains a D_LATCH pin that latches the data into the D0, D1, and D2 decoder inputs. If tied to a logic LOW (“0”), the latch is transparent, allowing the data at the decoder inputs to propagate through and program the SP509 accordingly. If tied to a logic HIGH(“1”), the latch locks out the data and prevents the mode from changing until this pin is brought to a logic LOW. There are internal pull-up devices on D0, D1, and D2, which allow the device to be in SHUTDOWN mode (“111”) upon power up. However , if the device is powered -up with the D_LATCH at a logic HIGH, the decoder state of the SP509 will be undefined. ESD TOLERANCE The SP509 device incorporates ruggedized ESD cells on all driver output and receiver input pins. The ESD structure is improved over our previous family for more rugged applications and environments sensitive to electrostatic discharges and associated transients. CTR1/CTR2 EUROPEAN COMPLIANCY As with all of Sipex’s previous multi-protocol serial transceiver IC’s the drivers and receivers have been designed to meet all the requirements to NET1/NET2 and TBR2 in order to meet CTR1/CTR2 compliancy. The SP509 is also tested in-house at Sipex and adheres to all the NET1/2 physical layer testing and the ITU Series V specifications before shipment. Please note that although the SP509 , as with its predecessors, adhere to CTR1/CTR2 compliancy testing, any complex or unusual configuration should be double-checked to ensure CTR1/CTR2 compliance. Consult the factory for details. Date: 1/19/05 SP509 Enhanced WAN Multi–Protocol Serial Transceiver © Copyright 2005 Sipex Corporation 23 SD(a) TxD SD(b) RD(a) RxD RD(b) TT(a) TxCE TT(b) RT(a) RxC RT(b) ST(a) ST ST(b) TxC(a) TxC TxC(b) RS(a) RTS RS(b) CS(a) CTS CS(b) TR(a) DTR TR(b) DM(a) DSR DM(b) RRC(a) DCD_DCE RRC(b) RRT(a) DCD_DTE RRT(b) RL RL(a) RI IC LL LL(a) TM TM(a) Figure 48. SP509 Loopback Path Date: 1/19/05 SP509 Enhanced WAN Multi–Protocol Serial Transceiver © Copyright 2005 Sipex Corporation 24 1µF 1µF 1µF Vcc + 10µF VCC 73 72 69 70 67 VDD C1+ C1- C2+ C2VSS 66 1µF CIRCUIT # #103 #113 #113 #105 #108 #109 #140 #141 28 97 SD(a) 100 S(b) 92 TT(a) 95 TT(b) 87 ST(a) 90 ST(b) 83 RS(a) 85 RS(b) 75 TR(a) 78 TR(b) 81 RRC(a) 79 RRC(b) Serial Port Connector Pins TxD 29 2 14 24 11 TxD_RXD_A TxD_RXD_B TxCE_TXC_A TXCE_TXC_B TxCE 30 ST 31 RTS 32 4 19 20 23 RTS_CTS_A RTS_CTS_B DTR_DSR_A DTR_DSR_B DTR 33 DCD_DCE 34 RL 35 21 65 RL(a) RL_RI LL 18 63 LL(a) LL_TM SP509 #105 #115 #114 #106) #107 #109 #125 #142 36 48 RD(a) 47 RD(b) 3 16 17 9 15 12 5 13 6 22 8 10 22 RXD_TXD_A RXD_TXD_B RXC_TXCE_A RXC_TXCE_B TXC_RXC_A TXC_RXC_B CTS_RTS_A CTS_RTS_B DSR_DTR_A DSR_DTR_B DCD_DCD_A DCD-DCD-B RI_RL RxD 37 50 RT(a) 49 RT(b) RxC 38 53 TxC(a) 51 TxC(b) TxC 39 55 CS(a) 54 CS(b) CTS 40 57 DM(a) 56 DM(b) DSR 41 60 RRT(a) 59 RRT(b) 61 IC DCD_DTE 42 RI 43 TM 3 SDEN 4 TTEN 5 STEN 6 RSEN 7 TREN 8 RRCEN 9 RLEN 10 LLEN 11 RDEN 12 RTEN 13 TxCEN 14 CSEN 15 DMEN 16 RRTEN 17 ICEN 18 TMEN 62 TM Logic Section D0 19 D1 20 D2 21 LOOPBACK 27 25 LL_TM Vcc DCE/DTE Vcc LATCH 23 TERM_OFF 22 V35TGND1 99 V35TGND2 94 35TGND3 89 V35RGND 46 V10_GND 58 * - Driver applies for DCE only on pins 15 and 12. Receiver applies for DTE only on pins 15 and 12. Driver applies for DCE only on pins 8 and 10. Receiver applies for DTE only on pins 8 and 10. Input Line Output Line Bi-directional Bus. Figure 49. Configuring SP509 to Operate as either DCE or DTE Date: 1/19/05 SP509 Enhanced WAN Multi–Protocol Serial Transceiver © Copyright 2005 Sipex Corporation 25 PACKAGE: 100 Pin LQFP D D1 0.2 RAD MAX. c 0.08 RAD MIN. PIN 1 11°-13° 0°MIN C L E1 E 0°–7° 11°-13° L L1 C L A2 b DIMENSIONS Minimum/Maximum (mm) SYMBOL A A1 A2 b D D1 e E E1 N 0.05 1.35 0.17 1.40 0.22 A A1 e 100–PIN LQFP JEDEC MS-026 (BED) Variation MIN NOM MAX 1.60 0.15 1.45 0.27 Seating Plane COMMON DIMENSIONS SYMBL MIN c L L1 0.09 0.45 0.60 1.00 REF NOM MAX 0.20 0.75 16.00 BSC 14.00 BSC 0.50 BSC 16.00 BSC 14.00 BSC 100 100 PIN LQFP Date: 1/19/05 SP509 Enhanced WAN Multi–Protocol Serial Transceiver © Copyright 2005 Sipex Corporation 26 SP508 Multiprotocol Configured as DCE Interface to PortConnector Interface to System Logic Pin Pin Pin Mnemonic Number Circuit Number Pin Mnemonic 97 SD(A) Driver_1 TxD 28 100 SD(B) SDEN 3 92 TT(A) Driver_2 TxCE 29 95 TT(B) TTEN 4 87 ST(A) ST 30 Driver_3 90 ST(B) STEN 5 83 RS(A) RTS 31 Driver_4 85 RS(B) RSEN 6 75 TR(A) DTR 32 Driver_5 78 TR(B) TREN 7 81 RRC(A) DCD_DCE 33 Driver_6 79 RRC(B) RRCEN 8 65 RL(A) RL 34 Driver_7 RLEN 9 63 LL(A) LL 35 Driver_8 LLEN# 10 48 RD(A) RxD 36 Receiver_1 47 RD(B) RDEN# 11 50 RT(A) RxC 37 Receiver_2 49 RT(B) RTEN# 12 53 TxC(A) TxC 38 Receiver_3 51 TxC(B) TxCEN# 13 55 CS(A) CTS 39 Receiver_4 54 CS(B) CSEN# 14 57 DM(A) DSR 40 Receiver_5 56 DM(B) DMEN# 15 60 RRT(A) DCD_DTE 41 Receiver_6 59 RRT(B) RRTEN# 16 61 IC RI 42 Receiver_7 ICEN# 17 62 TM(A) TM 43 Receiver_8 TMEN 18 Spare drivers and receivers may be used for optional signals (Signal Quality, Rate Detect, Standby) or may be disabled using individual enable pins for each driver and receiver Recommended Signals and Port Pin Assignments X.21 V.35 RS-449 EIA-530 RS-232 or V.24 Signal Mnemo DB-25 Signal Mnemo DB-25 Signal Mnemo DB-37 Signal Mnemo M34 Signal Mnemo DB-15 Pin(F) nic Pin(F) Type nic nic Pin(F) Type nic Pin(F) Type Pin(F) Type nic Type 4 R(A) V.11 R 104 V.35 6 V.11 RD(A) 3 V.11 BB(A) 3 BB V.28 11 R(B) V.11 T 104 V.35 24 V.11 RD(B) 16 V.11 BB(B) 7** B(A) V.11 V 115 V.35 8 V.11 RT(A) 17 V.11 DD(A) 17 DD V.28 14** B(B) V.11 X 115 V.35 26 V.11 RT(B) 9 V.11 DD(B) 6 S(A) V.11 Y 114 V.35 5 ST(A) V.11 15 V.11 DB(A) 15 DB V.28 13 S(B) V.11 AA 114 V.35 23 ST(B) V.11 12 V.11 DB(B) 5 I(A) V.11 D 106 V.28 9 V.11 CS(A) 5 V.11 CB(A) 5 CB V.28 12 I(B) V.11 27 V.11 CS(B) 13 V.11 CB(B) E 107 V.28 11 V.11 DM(A) 6 V.11 CC(A) 6 CC V.28 29 V.11 DM(B) 22 V.11 CC(B) F 109 V.28 13 V.11 RR(A) 8 V.11 CF(A) 8 CF V.28 31 V.11 RR(B) 10 V.11 CF(B) J 125 V.28 22 CE V.28 V.28 V.28 V.28 TM BA DA 25 2 24 V.10 V.11 V.11 V.11 V.11 TM BA(A) BA(B) DA(A) DA(B) 25 2 12 24 11 V.10 V.11 V.11 V.11 V.11 TM SD(A) SD(B) TT(A) TT(B) 18 4 22 17 35 V.28 V.35 V.35 V.35 V.35 142 103 103 113 113 NN P S U W V.11 V.11 V.11 V.11 T(A) T(B) X(A) X(B) 2 9 7** 14** SP509 Enhanced WAN Multi–Protocol Serial Transceiver Date: 1/19/05 © Copyright 2005 Sipex Corporation DCE CONFIGURATION V.28 V.28 CA CD 4 20 V.11 V.11 V.11 V.11 CA(A) CA(B) CD(A) CD(B) 4 19 20 23 V.11 V.11 V.11 V.11 RS(A) RS(B) TR(A) TR(B) 7 25 12 30 V.28 V.28 105 108 C H V.11 V.11 C(A) C(B) 3 10 V.28 V.28 RL LL 21 18 V.10 V.10 RL LL 21 18 V.10 V.10 RL LL 14 10 V.28 V.28 140 141 N L Pin assignments and signal functions are subject to national or regional variation and proprietary / non-standard implementations ** X.21 use either B() or X(), not both Date: 1/19/05 SP509 Enhanced WAN Multi–Protocol Serial Transceiver © Copyright 2005 Sipex Corporation 27 27 Interface to System Logic Pin Number 28 3 29 4 30 5 31 6 32 7 33 8 34 9 35 10 36 11 37 12 38 13 39 14 40 15 41 16 42 17 43 18 SP508 Multiprotocol Configured as DTE Interface to PortConnector Circuit Driver_1 Driver_2 Driver_3 Driver_4 Driver_5 Driver_6 Driver_7 Driver_8 Receiver_1 Receiver_2 Receiver_3 Receiver_4 Receiver_5 Receiver_6 Receiver_7 Receiver_8 Pin Mnemonic SD(A) SD(B) TT(A) TT(B) ST(A) ST(B) RS(A) RS(B) TR(A) TR(B) RRC(A) RRC(B) RL(A) LL(A) RD(A) RD(B) RT(A) RT(B) TxC(A) TxC(B) CS(A) CS(B) DM(A) DM(B) RRT(A) RRT(B) IC TM(A) Pin Number 97 100 92 95 87 90 83 85 75 78 81 79 65 63 48 47 50 49 53 51 55 54 57 56 60 59 61 62 Recommended Signals and Port Pin Assignments RS-232 or V.24 EIA-530 DB-25 Pin(M) 2 14 24 11 RS-449 Signal Mnemo nic Type V.11 SD(A) V.11 SD(B) TT(A) V.11 TT(B) V.11 DB-37 Pin(M) 4 22 17 35 V.35 Signal Mnemo M34 Pin(M) nic Type P 103 V.35 S 103 V.35 U 113 V.35 W 113 V.35 X.21 Signal Mnemo DB-15 Pin(M) nic Type 2 T(A) V.11 9 T(B) V.11 7** X(A) V.11 14** X(B) V.11 Signal Type V.11 V.11 AppleTalk™ Mnemo nic TxD TxD + DIN-8 Pin(F) 3 6 Pin Mnemonic TxD SDEN TxCE TTEN ST STEN RTS RSEN DTR TREN DCD_DCE RRCEN RL RLEN LL LLEN# RxD RDEN# RxC RTEN# TxC TxCEN# CTS CSEN# DSR DMEN# DCD_DTE RRTEN# RI ICEN# TM TMEN Signal Mnemo DB-25 Signal Mnemo nic Pin(M) Type nic Type BA(A) V.11 2 BA V.28 BA(B) V.11 V.11 DA(A) 24 DA V.28 V.11 DA(B) V.28 V.28 CA CD 4 20 V.11 V.11 V.11/10 V.11/Z CA(A) CA(B) CD(A) CD(B) 4 19 20 23 V.11 V.11 V.11 V.11 RS(A) RS(B) TR(A) TR(B) 7 25 12 30 V.28 V.28 105 108 C H V.11 V.11 C(A) C(B) 3 10 V.10 HSKo 1 V.28 V.28 V.28 V.28 V.28 V.28 V.28 V.28 V.28 V.28 RL LL BB DD DB CB CC CF CE TM 21 18 3 17 15 5 6 8 22 25 V.10 V.10 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11/10 V.11/Z V.11 V.11 V.10 V.10 RL LL BB(A) BB(B) DD(A) DD(B) DB(A) DB(B) CB(A) CB(B) CC(A) CC(B) CF(A) CF(B) RI TM 21 18 3 16 17 9 15 12 5 13 6 22 ‡ 8 10 22 ‡ 25 V.10 V.10 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 RL LL RD(A) RD(B) RT(A) RT(B) ST(A) ST(B) CS(A) CS(B) DM(A) DM(B) RR(A) RR(B) 14 10 6 24 8 26 5 23 9 27 11 29 13 31 V.28 V.28 V.35 V.35 V.35 V.35 V.35 V.35 V.28 V.28 V.28 V.28 140 141 104 104 115 115 114 114 106 107 109 125 142 N L R T V X Y AA D E F J NN V.11 V.11 R(A) R(B) 4 11 V.11 V.11 RxDRxD+ 5 8 SP509 Enhanced WAN Multi–Protocol Serial Transceiver Date: 1/19/05 © Copyright 2005 Sipex Corporation DTE CONFIGURATION V.11 V.11 V.11 V.11 V.11 V.11 S(A) S(B) I(A) I(B) B(A) B(B) 6 13 5 12 7** 14** V.10* V.10 GND HSKi GPi 2 7 V.10 TM 18 V.28 Spare drivers and receivers may be used for optional signals (Signal Quality, Rate Detect, Standby) or may be disabled using individual enable pins for each driver and receiver Pin assignments and signal functions are subject to national or regional variation and proprietary / non-standard implementations ‡ EIA-530 uses V.11 (differential) for DSR (CC) and DTR (CD) signals; EIA-530-A uses singleended V.10 for DSR and DTR and adds RI signal on pin 22 ** X.21 use either B() or X(), not both Date: 1/19/05 SP509 Enhanced WAN Multi–Protocol Serial Transceiver © Copyright 2005 Sipex Corporation 28 28 ORDERING INFORMATION Model Temperature Range Package Types SP509CF ............................................... 0°C to +70°C ............................................................ 100 Lead LQFP Available in lead free packaging. To order add “-L” suffix to part number. Example: SP509CF = standard; SP509CF-L = lead free REVISION HISTORY DATE 3/31/04 6/14/04 8/19/04 8/19/04 REVISION A B C D DESCRIPTION Implemented tracking revision. Added tables to pages 27 and 28. Corrected pin description table and figure 49. Updated DCE/DTE tables. Corrected reference to figure 48. Corporation ANALOG EXCELLENCE Sipex Corporation Headquarters and Sales Office 233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600 Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Date: 1/19/05 SP509 Enhanced WAN Multi–Protocol Serial Transceiver © Copyright 2005 Sipex Corporation 29