SP510
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
JUNE 2011
REV. 1.0.1
GENERAL DESCRIPTION
FEATURES
The SP510 is a highly integrated physical layer
solution that is configurable to support multiple serial
standards. It incorporates eight (8) drivers and eight
(8) receivers, configurable for either differential (V.11
or V.35) or single ended (V.28 and V.10) signaling.
The device architecture is designed to support the
data and clock signals used in HDLC or SDLC serial
ports as either a DTE or DCE. SP510 enables a
Serial Communications Controller (SCC) to
implement a variety of serial port types including
V.24, V.25, V.36, EIA-530, EIA-530-A, X.21, RS-232.
Operating configuration is in-system programmable
using the mode-select pins. The V.11 and V.35 modes
contain built in bus termination that may be switched
in or out using the TERM_OFF pin.
SP510 is ideal for space constrained applications. It
requires only a single 5V supply for full operation.
The VL pin determines the receiver output voltage
(VOH). For single supply operation at 5V the VL pin
may be connected to VCC. Fully compliant V.28 and
V.10 driver output voltages are generated using
onboard charge pumps. Special power sequencing is
not required during system startup. Charge pump
outputs are internally regulated to minimize power
consumption. The SP510 requires only four 1μF
capacitors for complete functionality. The device may
be put into a 200μA low power shutdown mode when
not in active use.
• 52Mbps Differential Transmission Rates
• Adjustable Logic Level Pin (Down to 1.65V)
• +/-15kV ESD Tolerance for Analog I/O’s
• Internal Transceiver Termination Resistors for V.11/
V.35
• Interface Modes:
■
RS-232 (V.28)
■
EIA-530 (V.10 & V.11)
■
X.21 (V.11)
■
EIA-530A (V.10 & V.11)
■
RS-449/V.36
• Software Selectable Protocols with 3-Bit Word
• Eight Drivers and Eight Receivers
• V.35/V.11 Receiver Termination Network Disable
Option
• Internal Line or Digital Loopback Testing
• Adheres to NET1/NET2 and TBR2 Requirements
• Easy Flow-Through Pinout
• Single +5V Supply Voltage
• Individual Driver/Receiver Enable/Disable Controls
• Operates in DTE or DCE Mode
All receivers have fail-safe protection to put outputs
into a known state when inputs are open, terminated
but open or shorted.
TYPICAL APPLICATIONS
• Data Communication Networks
• Telecommunication Equipment
• Secured Data Communication
• CSU and DSU
• Data Routers
• Network Switches
• WAN Access Equipment
• VoIP-PBX Gateways
ORDERING INFORMATION
PART NUMBER
PACKAGE
OPERATING TEMPERATURE RANGE
DEVICE STATUS
SP510EM-L
100-pin LQFP
-40°C to +85°C
Active
SP510CM-L
100-pin LQFP
0°C to +70°C
Active
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
SP510
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.1
ABSOLUTE MAXIMUM RATINGS
Continuous Power Dissipation at Ta = +70° C
These are stress ratings only and functional
operation of the device at these ratings or any other
above those indicated in the operation sections of the
specifications below is not implied. Exposure to
absolute maximum rating conditions for extended
periods of time may affect reliability.
100-Pin QFP…………………….…1520 mW
(derate 19.0 mW / °C above 70° C)
ΘJA
52.7 °C/W, ΘJC
6.5 °C/W
Storage Temperature………...-65°C to +150°C
Lead Temperature (soldering, 10s)….. 300° C
Supply Voltage (Vcc)……………...+ 7.0V
RECOMMENDED OPERATING CONDITIONS
Logic-Interface Voltage (VL)………. VL ≤ Vcc
Supply Voltage (Vcc)... 4.75V to 5.25V
Input voltage at TTL input pins ... - 0.3V to VL+0.5V
Receiver Input voltage….. ………..±15.5V
Logic-Interface Supply Voltage (VL)…..1.65V to
5.25V
Driver output (from Ground)…… -7.5V to +12.5V
Operating Temperature Range……-40° C to +85° C
Short Circuit Duration, TxOUT to GND, Continuous
2
SP510
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.1
TABLE 1: DC ELECTRICAL CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS
Vcc = +4.75V to +5.25V, C1-C4 = 1µF. TAMB = TMIN to TMAX, unless otherwise noted. Typical values are at TAMB = +25°C
PARAMETERS
Vcc Supply Voltage
Logic Interface Voltage
ICC Shutdown
ICC Supply Current
SYMBOL
TEST CONDITIONS
VCC
VL
VCC ≥ VL
MIN.
MAX
UNIT
4.75
5.25
V
1.65
5.25
V
ICCSD
TYP
μA
200
ICC
300
mA
DRIVER INPUT AND LOGIC INPUT PINS
Logic Input High
VIH
Logic Input Low
VIL
2.0
V
0.4
V
0.4
V
VL + 0.3
V
±20
±60
mA
±0.05
±1
μA
±6.0
±15.0
V
RECEIVER OUTPUTS
Receiver Logic Output Low
VOL
IOUT = -3.2 mA
Receiver Logic Output High
VOH
IOUT = 1 mA
Receiver Output Short-Circuit
Current
IOSS
0V < VO < VCC
Receiver Output Leakage Current
IOZ
Receivers disabled.
0.4V < VO < 5.25V
VL - 0.3
V.28 / RS-232 DRIVERS
Output Voltage Swing
Short Circuit Current
VT
Output load = 3kΩ to GND
Fig. 3
VOC
Output load = Open Circuit
Fig.2
±15.0
V
ISC
VOUT = 0V, Fig 5
±100
mA
Power-Off Impedance
Fig. 6
±5.0
Ω
300
V.28 / RS-232 RECEIVERS
Input Voltage Range
-15
Input Threshold Low
0.8
15
1.2
Input Threshold High
1.7
Input Hysteresis
500
Input Resistance
Open Circuit Bias
Fig. 8
VOC
3
Fig. 9
3
5
V
V
3.0
V
mV
7
kΩ
±2.0
V
SP510
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.1
DC ELECTRICAL CHARACTERISTICS
Vcc = +4.75V to +5.25V, C1-C4 = 1µF. TAMB = TMIN to TMAX, unless otherwise noted. Typical values are at TAMB = +25°C
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN.
TYP
MAX
UNIT
±6.0
V
V.10 / RS-423 DRIVERS
Open Circuit Voltage
VOC
Fig.10
±4.0
Test Terminated Voltage
VT
Fig. 11
0.9 VOC
Short Circuit Current
ISC
Fig. 12
±150
mA
Fig. 13
±100
μA
+3.25
mA
Power-Off Current
V
V.10 / RS-423 RECEIVERS
Input Current
IIA
Fig. 15 and 16
Input Impedance
-3.25
4
15
Sensitivity
kΩ
±0.2
V
±6.0
V
V.11 / RS-422 DRIVERS
Open Circuit Voltage
VOC, VOCA,
VOCB
Fig. 17
VT
Fig. 18
Balance
ΔVT
Fig. 18
±0.4
V
Driver DC Offset
VOS
Fig. 18
+3.0
V
ΔVOS
Fig. 18
±0.4
V
ISA, ISB
Fig. 19
±150
mA
Fig. 20
±100
μA
+7
V
Test Terminated Voltage
Offset Balance
Short Circuit Output Current
Power-Off Current
±2.0
V
V.11 / RS-422 RECEIVERS
Receiver Input Range
VCM
Input Current
IIA, IIB
Fig. 21 and 23
±3.25
mV
Input Current with Termination
IIA, IIB
Fig. 24 and 25
±60.75
mA
Receiver Input Impedance
RIN
Receiver Sensitivity
VTH
Receiver Input Hysteresis
ΔVTH
-7
-10V ≤ VCM ≤ +10V
4
15
kΩ
±200
VCM = 0 V
15
mV
mV
V.35 DRIVERS (ALL VALUES MEASURE WITH TERM_OFF = ’0’)
Test Terminated Voltage
Offset
VT
Fig. 26
VOS
Fig. 26
±0.44
±0.66
V
±0.6
V
Output Overshoot
Fig. 26, VST = Steady State
Voltage
-0.2VST
+0.2VST
V
Source Impedance
Fig. 29, ZS = V2 / V1 x 50Ω
50
150
Ω
4
SP510
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.1
DC ELECTRICAL CHARACTERISTICS
Vcc = +4.75V to +5.25V, C1-C4 = 1µF. TAMB = TMIN to TMAX, unless otherwise noted. Typical values are at TAMB = +25°C
PARAMETERS
SYMBOL
Short Circuit Impedance
TEST CONDITIONS
Fig. 28
MIN.
TYP
135
MAX
UNIT
165
Ω
±200
mV
V.35 RECEIVERS (ALL VALUES MEASURE WITH TERM_OFF = ’0’)
Sensitivity
±100
Source Impedance
Fig. 30, ZS = V2 / V1 x 50Ω
90
110
Ω
Short-Circuit Impedance
Fig. 31
135
165
Ω
TRANSCEIVER LEAKAGE CURRENT
Driver Output 3-state Current
Drivers disabled, per Fig. 32
Receiver Output 3-state Current
Tx and Rx Disabled,
0.4V - Vo - 2.4V
5
μA
500
1
10
μA
SP510
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.1
TABLE 2: AC TIMING CHARACTERISTICS
TIMING CHARACTERISTICS
VCC = +4.75 to 5.25V, C1-C4 = 1µF; TAMB = TMIN to TMAX, unless noted. Typical values are at TAMB = +25°C.
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN.
TYP
MAX
UNIT
V.28 / RS-232
Maximum Transmission Rate
Driver Propagation Delay
Fig. 7
250
tDPHL,
tDPLH
0.5
kbps
1
5
μs
Transition Time
+3V to -3V, -3V to +3V per
Fig. 7
0.2
1.5
μs
Instantaneous Slew Rate
+3V to -3V, -3V to +3V per
Fig. 4
4
30
V/μs
Driver Skew
| tDPHL - tDPLH| at zero
800
ns
100
crossing
Driver Channel to Channel Skew
20
ns
Driver Output Enable Time
Tri-state to output Low
tZL
CL = 100 pF, Fig. 34 and 40,
S1 closed
2.0
μs
Driver Output Enable Time
Tri-state to output High
tZH
CL = 100 pF, Fig. 34 and 40,
S2 closed
2.0
μs
Driver Output Disable Time
Output Low to Tri-state
tLZ
CL = 15 pF, Fig. 34 and 40,
S1 closed
2.0
μs
Driver Output Disable Time
Output High to Tri-state
tHZ
CL = 15 pF, Fig. 34 and 40,
S2 closed
20
μs
Receiver Propagation Delay
tPHL, tPLH
R_IN to R_OUT, CL = 15 pF
500
ns
Receiver Skew
Receiver Output Rise / Fall Time
tR, tF
50
100
| tPHL - tPLH| at 1.5V
50
ns
CL = 15 pF
15
ns
Receiver Output Enable Time
Tri-state to output Low
tZL
CL = 100 pF, Fig. 35 and 40,
S1 closed
2.0
μs
Receiver Output Enable Time
Tri-state to output High
tZH
CL = 100 pF, Fig. 35 and 40,
S2 closed
2.0
μs
Receiver Output Disable Time
Output Low to Tri-state
tLZ
CL = 15 pF, Fig. 35 and 40,
2.0
μs
Receiver Output Disable Time
Output High to Tri-state
tHZ
2.0
μs
2
ms
Charge Pump Rise Time
S1 closed
CL = 15 pF, Fig. 35 and 40,
S2 closed
Shutdown to normal operation
V.10 / RS-423
Maximum Transmission Rate
250
6
kbps
SP510
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.1
TIMING CHARACTERISTICS
VCC = +4.75 to 5.25V, C1-C4 = 1µF; TAMB = TMIN to TMAX, unless noted. Typical values are at TAMB = +25°C.
PARAMETERS
SYMBOL
Driver Propagation Delay
TEST CONDITIONS
MIN.
TYP
MAX
UNIT
30
150
500
ns
10% to 90% - Fig. 14
500
ns
| tDPHL - tDPLH| at zero cross-
100
ns
tPHL, tPLH
Driver Rise / Fall Time
tR, tF
Driver Skew
ing
Driver Output Enable Time
Tri-state to Output Low
tZL
CL = 100 pF, Fig. 34 and 40,
S1 closed
2
μs
Driver Output Enable Time
Tri-state to Output High
tZH
CL = 100 pF, Fig. 34 and 40,
S2 closed
2
μs
Driver Output Disable Time
Output Low to Tri-state
tLZ
CL = 15 pF, Fig. 34 and 40,
S1 closed
2
μs
Driver Output Disable Time
Output High to Tri-state
tHZ
CL = 15 pF, Fig. 34 and 40,
S2 closed
2
μs
Receiver Propagation Delay
tPHL, tPLH
500
ns
100
Receiver Output Enable Time
Tri-state to output Low
tZL
CL = 100 pF, Fig. 35 and 40,
S1 closed
2
μs
Receiver Output Enable Time
Tri-state to output High
tZH
CL = 100 pF, Fig. 35 and 40,
S2 closed
2
μs
Receiver Output Disable Time
Output Low to Tri-state
tLZ
CL = 15 pF, Fig. 35 and 40,
S1 closed
2
μs
Receiver Output Disable Time
Output High to Tri-state
tHZ
CL = 15 pF, Fig. 35 and 40,
S1 closed
Receiver Output Rise / Fall Time
tR, tF
Receiver Skew
CL = 15 pF
15
ns
| tPHL - tPLH| at 1.5V
5
ns
HIGH SPEED V.11 / RS-422 (DRIVERS 1, 2 & 3, RECEIVERS 1, 2 & 3)
Maximum Bit Rate
NRZI Encoding
52
0.5
Driver Rise and Fall Time
tR, tF
Fig. 22 and 36, 10-90%
Propagation Delay Time
tDPHL,
tDPLH
Fig. 33 and 36, CL = 50 pF
Differential Skew
Mbps
6
ns
25
ns
| tDPHL - tDPLH|
3.8
ns
5
Driver Output Enable Time
Tri-state to Output Low
tZL
CL = 100 pF, Fig. 34 and 37,
S1 closed
100
ns
Driver Output Enable Time
Tri-state to Output High
tZH
CL = 100 pF, Fig. 34 and 37,
S2 closed
100
ns
Driver Output Disable Time
Output Low to Tri-state
tLZ
CL = 15 pF, Fig. 34 and 37,
S1 closed
100
ns
7
SP510
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.1
TIMING CHARACTERISTICS
VCC = +4.75 to 5.25V, C1-C4 = 1µF; TAMB = TMIN to TMAX, unless noted. Typical values are at TAMB = +25°C.
PARAMETERS
SYMBOL
Driver Output Disable Time
Output High to Tri-state
tHZ
Receiver Propagation Delay
tPHL, tPLH
TEST CONDITIONS
MIN.
TYP
CL = 15 pF, Fig. 34 and 37,
S2 closed
Fig. 33, 36
CL = 50 pF
20
| tPHL - tPLH| Fig. 33, 36
Receiver Skew
MAX
UNIT
100
ns
50
ns
3.8
ns
CL = 50 pF
Receiver Output Enable Time
Tri-state to Output Low
tZL
CL = 100 pF, Fig. 35 and 39,
S1 closed
100
ns
Receiver Output Enable Time
Tri-state to Output High
tZH
CL = 100 pF, Fig. 35 and 39,
S2 closed
100
ns
Receiver Output Disable Time
Output Low to Tri-state
tLZ
CL = 15 pF, Fig. 35 and 39,
S1 closed
100
ns
Receiver Output Disable Time
Output High to Tri-state
tHZ
CL = 15 pF, Fig. 35 and 39,
S2 closed
100
ns
6
ns
Receiver Output Rise / Fall Time
tR, tF
3.0 V < VL < 5.5V
0.5
1.65 V < VL < 3.0V
CL = 50 pF
Channel to channel Skew
2
ns
V.11 / RS-422 HANDSHAKE SIGNALS (DRIVERS 4, 5 & 6, RECEIVERS 4, 5 & 6)
Maximum Transmission Rate
Fig. 33
10
Mbps
Driver Rise and Fall Time
tR, tF
Fig. 22 and 36
2
10
ns
Propagation Delay Time
tDPHL,
tDPLH
Fig. 33 and 36, CL = 50 pF
20
50
ns
10
ns
| tDPHL - tDPLH |
Driver Propagation Delay Skew
Driver Channel to Channel Skew
2
ns
Driver Output Enable Time
Tri-state to Output Low
tZL
CL = 100 pF, Fig. 34 and 37,
S1 closed
100
ns
Driver Output Enable Time
Tri-state to Output High
tZH
CL = 100 pF, Fig. 34 and 37,
S2 closed
100
ns
Driver Output Disable Time
Output Low to Tri-state
tLZ
CL = 15 pF, Fig. 34 and 37,
S1 closed
100
ns
Driver Output Disable Time
Output High to Tri-state
tHZ
CL = 15 pF, Fig. 34 and 37,
S2 closed
100
ns
Receiver Propagation Delay
tPHL, tPLH
50
ns
Fig. 33, 36
CL = 50 pF
8
20
SP510
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.1
TIMING CHARACTERISTICS
VCC = +4.75 to 5.25V, C1-C4 = 1µF; TAMB = TMIN to TMAX, unless noted. Typical values are at TAMB = +25°C.
PARAMETERS
SYMBOL
TEST CONDITIONS
| tPHL -
Receiver Skew
MIN.
TYP
tPLH| Fig. 33, 36
MAX
UNIT
10
ns
CL = 50 pF
Receiver Output Enable Time
Tri-state to Output Low
tZL
CL = 100 pF, Fig. 35 and 39,
S1 closed
100
ns
Receiver Output Enable Time
Tri-state to Output High
tZH
CL = 100 pF, Fig. 35 and 39,
S2 closed
100
ns
Receiver Output Disable Time
Output Low to Tri-state
tLZ
CL = 15 pF, Fig. 35 and 39,
S1 closed
100
ns
Receiver Output Disable Time
Output Low to Tri-state
tHZ
CL = 15 pF, Fig. 35 and 39,
S2 closed
100
ns
20
ns
Receiver Output Rise / Fall Time
tR , tF
1
Channel to Channel Skew
2
ns
V.35 (DRIVERS 1, 2 & 3, RECEIVERS 1, 2 & 3)
Maximum Transmission Rate
Fig. 33, fMAX = 20 MHz
Driver Rise and Fall Time
tR , tF
Propagation Delay Time
tDPHL ,
tDPLH
Mbps
Fig. 29
Fig. 33 and 36, CL = 50 pF
| tDPHL -
Driver Differential Skew
40
20
tDPLH| Fig. 33 and
10
ns
50
ns
5.0
ns
36
Driver Channel to Channel Skew
2
ns
Driver Output Enable Time
Tri-state to Output Low
tZL
CL = 100 pF, Fig. 34 and 37,
S1 closed
200
ns
Driver Output Enable Time
Tri-state to Output High
tZH
CL = 100 pF, Fig. 34 and 37,
S2 closed
200
ns
Driver Output Disable Time
Output Low to Tri-state
tLZ
CL = 15 pF, Fig. 34 and 37,
S1 closed
200
ns
Driver Output Disable Time
Output High to Tri-state
tHZ
CL = 15 pF, Fig. 34 and 37,
S2 closed
200
ns
Receiver Propagation Delay
tPHL , tPLH
30
ns
5.0
ns
200
ns
Fig. 33, 38
CL = 50 pF
| tPHL -
Receiver Skew
tPLH| Fig. 33 and 38
18
CL = 50 pF
Receiver Output Enable Time
Tri-state to Output Low
tZL
CL = 100 pF, Fig. 35 and 39,
S1 closed
9
SP510
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.1
TIMING CHARACTERISTICS
VCC = +4.75 to 5.25V, C1-C4 = 1µF; TAMB = TMIN to TMAX, unless noted. Typical values are at TAMB = +25°C.
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN.
TYP
MAX
UNIT
Receiver Output Enable Time
Tri-state to Output High
tZH
CL = 100 pF, Fig. 35 and 39,
S2 closed
200
ns
Receiver Output Disable Time
Output Low to Tri-state
tLZ
CL = 15 pF, Fig. 35 and 39,
S1 closed
200
ns
Receiver Output Disable Time
Output High to Tri-state
tHZ
CL = 15 pF, Fig. 35 and 39,
S2 closed
200
ns
10
SP510
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.1
SP510
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
VL
GND
SDEN
TTEN
STEN
RSEN
TREN
RRCEN
RLEN
LLEN#
RDEN#
RTEN#
TXCEN#
CSEN#
DMEN#
RRTEN#
ICEN#
TMEN
D0
D1
D2
TERM_OFF
D_LATCH#
NC
GND
NC
VCC
TR(b)
RRC(b)
VCC
RRC(a)
GND
RS(a)
VCC
RS(b)
GND
ST(a)
VCC
V35TGND3
ST(b)
GND
TT(a)
VCC
V35TGND2
TT(b)
GND
SD(a)
VCC
V35TGND1
SD(b)
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
TR(a)
GND
VDD
C1P
VCC
C2P
C1N
GND
C2N
VSS1
RL(a)
VCC
LL(a)
TM(a)
IC
RRT(a)
RRT(b)
GNDV10
DM(a)
DM(b)
CS(a)
CS(b)
TXC(a)
GND
TXC(b)
FIGURE 1. PIN OUT DIAGRAM
11
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
RT(a)
RT(b)
RD(a)
RD(b)
V35RGND
VL
GND
TM
RI
DCD_DTE
DSR
CTS
TXC
RXC
RXD
LL
RL
DCD_DCE
DTR
RTS
ST
TX_CE
TXD
LOOPBACK#
VCC
SP510
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.1
TABLE 3: PIN DESCRIPTIONS BY FUNCTION
Pin Name
Pin Number
I/O
DESCRIPTION
DIFFERENTIAL DRIVERS
TxD
28
I
TTL
TxD Driver Input
SD(b) / SD(a)
100, 97
O
TTL
Differential Transmit data non-inverting (b) and inverting
(a) outputs
V35TGND1
99
I
SDEN
3
I
TTL
TxD Driver Enable
TxCE
29
I
TTL
TxCE Driver Input
TT(b) / TT(a)
95, 92
O
TTL
Differential TxCE non-inverting (b) and inverting (a) outputs
V35TGND2
94
I
TTEN
4
I
TTL
TxCE Driver Enable
ST
30
I
TTL
ST Driver Input
ST(b) / ST(a)
90, 87
O
TTL
Differential ST non-inverting (b) and inverting (a) outputs
V35TGND3
89
I
STEN
5
I
TTL
ST Driver Enable
RTS
31
I
TTL
RTS Driver Input
RS(b) / RS(a)
85, 83
O
TTL
Differential RTS non-inverting (b) and inverting (a) outputs
RSEN
6
I
TTL
RTS Driver Enable
DTR
32
I
TTL
DTR Driver Input
TR(b) / TR(a)
78, 75
O
TTL
Differential DTR non-inverting (b) and inverting (a) outputs
TREN
7
I
TTL
DTR Driver Enable
DCD_DCE
33
I
TTL
DCD_DCE Driver Input
RRC(b) / RRC(a)
79, 81
O
TTL
Differential DCD non-inverting (b) and inverting (a) outputs
RRCEN
8
I
TTL
DCD Driver Enable
SD Termination Reference
TT Termination Reference
ST Termination Reference
SINGLE ENDED DRIVERS
RL
34
I
TTL
RL Driver Input
RL(a)
65
O
TTL
RL Driver Output
RLEN
9
I
TTL
RL Driver Enable
LL
35
I
TTL
LL Driver Input
LL(a)
63
O
TTL
LL Driver Output
LLEN#
10
I
TTL
LL Driver Enable, active low
12
SP510
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.1
Pin Name
Pin Number
I/O
DESCRIPTION
DIFFERENTIAL RECEIVERS
RxD
36
O
TTL
RxD Receiver Output
RD(b) / RD(a)
47, 48
I
TTL
Differential RXD non-inverting (b) and inverting (a) inputs
RDEN#
11
I
TTL
RxD Receiver Enable, active low
RxC
37
O
TTL
RxC Receiver Output
RT(b) / RT(a)
49, 50
I
TTL
Differential RXC non-inverting (b) and inverting (a) inputs
RTEN#
12
I
TTL
RxC Receiver Enable, active low
TxC
38
O
TTL
TxC Receiver Output
TxC(b) / TxC(a)
51, 53
I
TTL
Differential TxC non-inverting (b) and inverting (a) inputs
TxCEN#
13
I
TTL
TxC Receiver Enable, active low
CTS
39
O
TTL
CTS Receiver Output
CS(b) / CS(a)
54, 55
I
TTL
Differential CTS non-inverting (b) and inverting (a) inputs
CSEN#
14
I
TTL
CTS Receiver Enable, active low
DSR
40
O
TTL
DSR Receiver Output
DM(b) / DM(a)
56, 57
I
TTL
Differential DSR non-inverting (b) and inverting (a) inputs
DMEN#
15
I
TTL
DSR Receiver Enable, active low
DCD_DTE
41
O
TTL
DCD_DTE Receiver Output
RRT(b) / RRT(a)
59, 60
I
TTL
Differential DCD_DTE non-inverting (b) and inverting (a)
inputs
RRTEN#
16
I
TTL
DCD_DTE Receiver Enable, active low
SINGLE ENDED RECEIVERS
IC
61
I
TTL
RI Receiver Input
RI
42
O
TTL
RI Receiver Output
ICEN#
17
I
TTL
RI Receiver Enable, active low
TM(a)
62
I
TTL
TM Receiver Input
TM
43
O
TTL
TM Receiver Output
TMEN
18
I
TTL
TM Receiver Enable
PROTOCOL MODE SELECTION SIGNALS
D2, D1, D0
21, 20, 19
I
Mode Select - Refer to Table 5 and Table 6
TTL
13
SP510
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
Pin Name
Pin Number
I/O
REV. 1.0.1
DESCRIPTION
Charge Pump Signals
C1P, C1N
72, 69
I
Charge Pump Capacitor 1 +/- inputs. Connect a 1 μF
capacitor between C1P and C1N pins.
C2P, C2N
70, 67
I
Charge Pump Capacitor 2 +/- inputs. Connect a 1 μF
capacitor between C2P and C2N pins.
VSS1
66
I
-2xVCC Charge Pump
VDD
73
I
2xVCC Charge Pump
GENERAL CONTROL SIGNALS
LOOPBACK#
27
I
TTL
Loopback mode enable, active low
D_LATCH#
23
I
Decoder Latch, active low
TERM_OFF
22
I
Termination disable
RESERVED PINS
NC
24, 76
No Connect
POWER AND GROUND SIGNALS
VCC
26, 64, 71, 77,
80, 84, 88, 98
I
5V supply.
VL
1, 45
I
Logic I/O Power Supply Input
GND
2, 25, 44, 52,
68, 74, 82, 86,
91, 96
I
Ground.
GNDV10
58
I
V.10 Receiver Ground Reference
V35RGND
46
O
Receiver Termination Reference
NOTE: Pin type: I = Input, O = Output, I/O = Input/output.
14
SP510
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.1
TABLE 4: PIN DESCRIPTIONS BY PIN NUMBER
PIN DESCRIPTIONS BY PIN NUMBER
1
VL
Logic I/O Power Supply Input
32
DTR
2
DTR Driver TTL Input
GND
Ground
33
DCD_DCE
3
SDEN
TxD Driver Enable Input
34
RL
RL Driver TTL Input
4
TTEN
TxCE Driver Enable Input
35
LL
LL Driver TTL Input
5
STEN
ST Driver Enable Input
36
RxD
RxD Receiver TTL Output
6
RSEN
RTS Driver Enable Input
37
RxC
RxC Receiver TTL Output
7
TREN
DTR Driver Enable Input
38
TxC
TxC Receiver TTL Output
8
RRCEN
DCD Driver Enable Input
39
CTS
CTS Receiver TTL Output
9
RLEN
RL Driver Enable Input
40
DSR
DSR Receiver TTL Output
10
LLEN#
LL Driver Enable Input
41
DCD_DTE
11
RDEN#
RxD Receiver Enable Input
42
RI
RI Receiver TTL Output
12
RTEN#
RxC Receiver Enable Input
43
TM
TM Receiver TTL Output
13
TxCEN#
TxC Receiver Enable Input
44
GND
14
CSEN#
CTS Receiver Enable Input
45
VL
15
DMEN#
DSR Receiver Enable Input
46
V35RGND
16
RRTEN#
DCD_DTE Receiver Enable Input
47
RD(b)
RXD Non-Inverting Input
17
ICEN#
RI Receiver Enable Input
48
RD(a)
RXD Inverting Input
18
TMEN
TM Receiver Enable Input
49
RT(b)
RxC Non-Inverting Input
19
D0
Mode Select Input - Bit 0
50
RT(a)
RxC Inverting Input
20
D1
Mode Select Input - Bit 1
51
TxC(b)
TxC Non-Inverting Input
21
D2
Mode Select Input - Bit 2
52
GND
DCD_DCE Driver TTL Input
DCD_DTE Receiver TTL Output
Ground
Logic I/O Power Supply Input
Receiver Termination Reference
Ground
22
TERM_OFF Termination Disable Input
53
TxC(a)
TxC Inverting Input
23
D_LATCH#
Decoder Latch Input
54
CS(b)
CTS Non-Inverting Input
24
NC
No Connect
55
CS(a)
CTS Inverting Input
25
GND
Ground
56
DM(b)
DSR Non-Inverting Input
26
Vcc
Power Supply Input
57
DM(a)
DSR Inverting Input
27
LOOPBACK#
Loopback Mode Enable Input
58
GNDV10
28
TxD
TxD Driver TTL Input
59
RRT(b)
DCD_DTE Non-Inverting Input
29
TxCE
TxCE Driver TTL Input
60
RRT(a)
DCD_DTE Inverting Input
30
ST
ST Driver TTL Input
61
IC
RI Receiver Input
31
RTS
RTS Driver TTL Input
62
TM(a)
TM Receiver Input
15
V.10 Rx Ground Reference
SP510
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.1
PIN DESCRIPTIONS BY PIN NUMBER
63
LL(a)
LL Driver Output
82
GND
Ground
64
VCC
Power Supply Input
83
RS(a)
RTS Inverting Output
65
RL(a)
RL Driver Output
84
VCC
Power Supply Input
66
VSS1
-2xVCC Charge Pump
85
RS(b)
RTS Non-Inverting Output
67
C2N
Charge Pump Capacitor
86
GND
Ground
68
GND
Ground
87
ST(a)
ST Inverting Output
69
C1N
Charge Pump Capacitor
88
VCC
Power Supply Input
70
C2P
Charge Pump Capacitor
89
71
VCC
Power Supply Input
90
ST(b)
ST Non-Inverting Output
72
C1P
Charge Pump Capacitor
91
GND
Ground
73
VDD
2xVCC Charge Pump
92
TT(a)
TxCE Inverting Output
74
GND
Ground
93
VCC
5V Power Supply
75
TR(a)
DTR Inverting Output
94
76
NC
No Connect
95
TT(b)
TxCE Non-Inverting Output
77
VCC
Power Supply Input
96
GND
Ground
78
TR(b)
DTR Non-Inverting Output
97
SD(a)
TxD Inverting Output
79
RRC(b)
DCD Non-Inverting Output
98
VCC
5V Power Supply
80
VCC
Power Supply Input
99
81
RRC(a)
DCD Inverting Output
100
16
V35TGND3 ST Termination Reference
V35TGND2 TT Termination Reference
V35TGND1 SD Termination Reference
SD(b)
TxD Non-Inverting Output
SP510
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.1
TABLE 5: DRIVER MODE SELECTION
EIA530A
MODE
RS-449
MODE
(V.36)
011
100
101
110
111
V.11
V.28
V.11
V.11
V.11
High-Z
TxD(a)
V.35
V.11
High-Z
V.11
V.11
V.11
High-Z
TxD(b)
T2OUT(a)
V.35
V.11
V.28
V.11
V.11
V.11
High-Z
TxCE(a)
T2OUT(b)
V.35
V.11
High-Z
V.11
V.11
V.11
High-Z
TxCE(b)
T3OUT(a)
V.35
V.11
V.28
V.11
V.11
V.11
High-Z
TxC_DCE(a)
T3OUT(b)
V.35
V.11
High-Z
V.11
V.11
V.11
High-Z
TxC_DCE(b)
T4OUT(a)
V.28
V.11
V.28
V.11
V.11
V.11
High-Z
RTS(a)
T4OUT(b)
High-Z
V.11
High-Z
V.11
V.11
V.11
High-Z
RTS(b)
T5OUT(a)
V.28
V.11
V.28
V.10
V.11
V.11
High-Z
DTR(a)
T5OUT(b)
High-Z
V.11
High-Z
High-Z
V.11
V.11
High-Z
DTR(b)
T6OUT(a)
V.28
V.11
V.28
V.11
V.11
V.11
High-Z
DCD_DCE(a)
T6OUT(b)
High-Z
V.11
High-Z
V.11
V.11
V.11
High-Z
DCD_DCE(b)
T7OUT(a)
V.28
V.10
V.28
V.10
V.10
High-Z
High-Z
RL
T8OUT(a)
V.28
V.10
V.28
V.10
V.10
High-Z
High-Z
LL
DRIVER OUTPUT
PIN
V.35
MODE
EIA-530
MODE
RS-232
MODE
(V.28)
MODE (D0, D1,
D2)
001
010
T1OUT(a)
V.35
T1OUT(b)
17
X.21
MODE
(V.11)
SHUTDOWN
SUGGESTED
SIGNAL
SP510
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.1
TABLE 6: RECEIVER MODE SELECTION
EIA530A
MODE
RS-449
MODE
(V.36)
011
100
101
110
111
V.11
V.28
V.11
V.11
V.11
High-Z
RxD(a)
V.35
V.11
High-Z
V.11
V.11
V.11
High-Z
RxD(b)
R2IN(a)
V.35
V.11
V.28
V.11
V.11
V.11
High-Z
RxCE(a)
R2IN(b)
V.35
V.11
High-Z
V.11
V.11
V.11
High-Z
RxCE(b)
R3IN(a)
V.35
V.11
V.28
V.11
V.11
V.11
High-Z
TxC_DTE(a)
R3IN(b)
V.35
V.11
High-Z
V.11
V.11
V.11
High-Z
TxC_DTE(b)
R4IN(a)
V.28
V.11
V.28
V.11
V.11
V.11
High-Z
CTS(a)
R4IN(b)
High-Z
V.11
High-Z
V.11
V.11
V.11
High-Z
CTS(b)
R5IN(a)
V.28
V.11
V.28
V.10
V.11
V.11
High-Z
DSR(a)
R5IN(b)
High-Z
V.11
High-Z
High-Z
V.11
V.11
High-Z
DSR(b)
R6IN(a)
V.28
V.11
V.28
V.11
V.11
V.11
High-Z
DCD_DTE(a)
R6IN(b)
High-Z
V.11
High-Z
V.11
V.11
V.11
High-Z
DCD_DTE(b)
R7IN(a)
V.28
V.10
V.28
V.10
V.10
High-Z
High-Z
RI
R8IN(a)
V.28
V.10
V.28
V.10
V.10
High-Z
High-Z
TM
RECEIVER INPUT
PIN
V.35
MODE
EIA-530
MODE
RS-232
MODE
(V.28)
MODE (D0, D1,
D2)
001
010
R1IN(a)
V.35
R1IN(b)
18
X.21
MODE
(V.11)
SHUTDOWN
SUGGESTED
SIGNAL
SP510
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.1
TABLE 7: V.11 & V.35 DRIVERS
INPUTS
TABLE 11: V.10 DRIVERS
OUTPUTS
INPUTS
OUTPUTS
TX_EN#
TX_IN
TX(A)
TX(B)
TX_EN#
TX_IN
TX(A)
TX(B)
1
1
0
1
1
1
< -4V
> 30 kΩ
1
0
1
0
1
0
> +4V
> 30 kΩ
TABLE 8: V.11 & V.35 RECEIVERS
TABLE 12: V.10 RECEIVERS
INPUTS
OUTPUTS
INPUTS
OUTPUTS
RX(A) - RX(B)
RO
RX(A) - RX(B)
RO
≥ 200 mV
1
≥ +0.3V
0
≤ −200 mV
0
≤ −0.3V
1
Open / shorted
1
Open / ground
1
TABLE 9: V.28 DRIVERS
INPUTS
OUTPUTS
TX_EN#
TX_IN
TX(A)
TX(B)
1
1
< -5V
> 30 kΩ
1
0
> +5V
> 30 kΩ
TABLE 10: V.28 RECEIVERS
INPUTS
OUTPUTS
RX(A) - RX(B)
RO
≥ +3V
0
≤ −3V
1
Open / ground
1
19
SP510
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.1
FIGURE 2. V.28 DRIVER OUTPUT OPEN CIRCUIT VOLT-
FIGURE 5. V.28 DRIVER OUTPUT SHORT CIRCUIT CUR-
AGE
RENT
FIGURE 6. V.28 DRIVER OUTPUT POWER-OFF IMPEDFIGURE 3. V.28 DRIVER OUTPUT LOADED VOLTAGE
ANCE
FIGURE 4. V.28 DRIVER OUTPUT SLEW RATE
FIGURE 7. V.28 DRIVER OUTPUT RISE/FALL TIME
20
SP510
REV. 1.0.1
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
FIGURE 8. V.28 RECEIVER INPUT IMPEDANCE
FIGURE 11. V.10 DRIVER OUTPUT TEST TERMINATED
VOLTAGE
FIGURE 9. V.28 RECEIVER INPUT OPEN-CIRCUIT BIAS
FIGURE 12. V.10 DRIVER OUTPUT SHORT-CIRCUIT
CURRENT
FIGURE 10. V.10 DRIVER OUTPUT OPEN-CIRCUIT
VOLTAGE
FIGURE 13. V.10 DRIVER OUTPUT POWER-OFF IMPEDANCE
21
SP510
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
FIGURE 14. V.10 DRIVER OUTPUT TRANSITION TIME
REV. 1.0.1
FIGURE 17. V.11 DRIVER OUTPUT TEST TERMINATED
VOLTGE
FIGURE 15. V.10 RECEIVER INPUT CURRENT
FIGURE 18. V.11 DRIVER OUTPUT TEST TERMINATED
VOLTAGE
FIGURE 16. V.10 RECEIVER INPUT IV GRAPH
FIGURE 19. V.11 DRIVER OUTPUT SHORT-CIRCUIT
CURRENT
22
SP510
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.1
FIGURE 20. V.11 DRIVER OUTPUT POWER-OFF CUR-
FIGURE 21. V.11 RECEIVER INPUT CURRENT
RENT
VCC = 0V
A
A
Iia
±10V
Ixa
±0.25V
B
B
C
C
VCC = 0V
A
±10V
A
±0.25V
B
B
Ixb
C
C
23
Iib
SP510
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.1
FIGURE 24. V.11 RECEIVER INPUT CURRENT WITH TERMINATION
FIGURE 22. V.11 DRIVER OUTPUT RISE/FALL TIME
A
Iia
±6V
100 to
150
B
C
FIGURE 23. V.11 RECEIVER INPUT IV GRAPH
A
±6V
100 to
150
B
C
24
Iib
SP510
REV. 1.0.1
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
FIGURE 25. V.11 RECEIVER INPUT IV GRAPH WITH TERMINATION
FIGURE 26. V.35 DRIVER OUTPUT TEST TERMINATED VOLTAGE
FIGURE 27. V.35 DRIVER OUTPUT SOURCE IMPEDANCE
25
SP510
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
FIGURE 28. V.35 DRIVER OUTPUT SHORT-CIRCUIT IMPEDANCE
FIGURE 29. V.35 DRIVER OUTPUT RISE/FALL TIME
FIGURE 30. V.35 RECEIVER INPUT SOURCE IMPEDANCE
26
REV. 1.0.1
SP510
REV. 1.0.1
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
FIGURE 31. V.35 RECEIVER INPUT SHORT-CIRCUIT IMPEDANCE
FIGURE 32. DRIVER OUTPUT CURRENT LEAKAGE TEST
FIGURE 33. DRIVER / RECEIVER TIMING TEST CIRCUIT
27
SP510
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
FIGURE 34. DRIVER TIMING TEST LOAD CIRCUIT
FIGURE 35. RECEIVER TIMING TEST LOAD CIRCUIT
FIGURE 36. DRIVER PROPAGATON DELAYS
28
REV. 1.0.1
SP510
REV. 1.0.1
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
FIGURE 37. DRIVER ENABLE AND DISABLE TIMES
FIGURE 38. RECEIVER PROPAGATION DELAYS
FIGURE 39. RECEIVER ENABLE AND DISABLE TIMES
29
SP510
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
FIGURE 40. V.28 (RS-232) AND V.10 (RS-423) DRIVER ENABLE AND DISABLE TIMES
FIGURE 41. TYPICAL V.28 DRIVER OUTPUT WAVEFORM
30
REV. 1.0.1
SP510
REV. 1.0.1
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
FIGURE 42. TYPICAL V.10 DRIVER OUTPUT WAVEFORM
FIGURE 43. TYPICAL V.11 DRIVER OUTPUT WAVEFORM
FIGURE 44. TYPICAL V.35 DRIVER OUTPUT WAVEFORM
31
SP510
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.1
FIGURE 45. FUNCTIONAL DIAGRAM
+5V (decoupling capacitor not shown)
VCC pins (26, 64, 71, 77, 80, 84, 88, 93, 98)
GND pins (2, 25, 44, 52, 68, 74, 82, 86, 91, 96)
VL pins (1 and 46)
N.C. pins (24 and 76)
Logic Voltage
1μF
1μF
72
1μF
VCC
VL
73 VDD
V35RGND
RD(a)
RxD
RDEN
RD(b)
69
C1+
70
C1-
C2+
67
C2-
VSS
1μF
46
48
28
97
99
100
3
36
11
47
29
92
94
95
4
50
RT(a)
RT(b)
37
12
49
TxC(a)
53
RxC
RTEN
TxC
TxCEN
TxC(b)
CS(a)
55
CS(b)
39
14
54
DM(a)
57
CTS
CSEN
DSR
DMEN
40
15
DM(b)
56
RRT(a)
60
RRT(b)
41
16
59
DCD_DTE
RRTEN
IC
RI
ICEN
30
87
89
90
5
38
13
51
TM
TMEN
23
TTEN
ST
ST(a)
V35TGND3
ST(b)
STEN
DCD_DCE
10
V.10-GND
TT(b)
33
81
63
SP510
V35TGND2
TR(b)
35
D2
TT(a)
78
7
9
D1
TxCE
DTR
65
21
SDEN
32
75
42
17
20
SD(b)
RS(b)
34
D0
V35TGND1
85
6
8
19
SD(a)
RTS
61
43
18
TxD
31
83
79
62
TM(a)
66
Regulated Charge Pump
RS(a)
RSEN
TR(a)
TREN
RRC(a)
RRC(b)
RRCEN
RL
RL(a)
RLEN
LL
LL(a)
LLEN
58
D-LATCH
22
TERM-OFF
27
LOOPBACK
GND
RECEIVER TERMINATION NETWORK
V.35 MODE
V.11 MODE
V.35 DRIVER TERMINATION NETWORK
51ohms
51ohms
V.35 MODE
124ohms
124ohms
TX ENABLE
RX ENABLE
51ohms
51ohms
32
SP510
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.1
FIGURE 46. SP510 LOOPBACK PATH
SD(a)
TxD
SD(b)
RD(a)
RxD
RD(b)
TT(a)
TxCE
TT(b)
RT(a)
RxC
RT(b)
ST(a)
ST
ST(b)
TxC(a)
TxC
TxC(b)
RS(a)
RTS
RS(b)
CS(a)
CTS
CS(b)
TR(a)
DTR
TR(b)
DM(a)
DSR
DM(b)
RRC(a)
DCD_DCE
RRC(b)
RRT(a)
DCD_DTE
RRT(b)
RL
RL(a)
RI
IC
LL
LL(a)
TM
TM(a)
33
34
Input Line
Output Line
I/O Lines represented by double arrowhead signifies a bi-directional bus.
* - Driver applies f or DCE only on pins 15 and 12.
Receiver applies for DTE only on pins 15 and 12.
Driver applies f or DCE only on pins 8 and 10.
Receiver applies for DTE only on pins 8 and 10.
DCE/DTE
#142 (TM)
#125 (RI)
VL
DTE
#109 (DCD)
#107 (DSR)
#106 (CTS)
#114 (TxC)
#115 (RXC)
#105 (RXD)
#141 (LL)
#140 (RL)
#109 (DCD)DCE
#108 (DTR)
#105 (RTS)
#113 (TXCE)
#103 (TxD)
+5V
10μ F
TM
RI
DCD_DTE
DSR
CTS
TxC
RxC
RxD
LL
RL
DCD_DCE
DTR
RTS
ST
TxCE
TxD
RDEN
RTEN
TxCEN
DMEN
CSEN
RRTEN
ICEN
TMEN
GND
D2
D1
D0
VSS
V10_GND
V35RGND
V35TGND3
V35TGND2
V35TGND1
LOOPBACK
TERM_OFF
D_LATCH
SP510
Logic Section
Transceiver Section
Charge Pump Section
C2-
1μ F
VDD VL C1+ C1- C2+
SDEN
TTEN
STEN
TREN
RSEN
RRCEN
RLEN
LLEN
VCC
1μ F
Logic Voltage
1μ F
1μ F
VL
SIGNAL GND (10 Pins)
25 (V.10,V.28)
Doc. #:
Typical SP510 DB-26 Serial Port Configuration
Reference Design Schematic
0
Rev.
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
Date:
Title :
Customer:
LL_TM
RI_RL
RXD_TXD_A
RXD_TXD_B
RXC_TXCE_A
RXC_TXCE_B
*TXC_RXC_A
*TXC_RXC_B
CTS_RTS_A
CTS_RTS_B
DSR_DTR_A
DSR_DTR_B
DCD_DCD_A
DCD_DCD_B
22 (V.10,V.28)
LL_TM
3 (V.11,V.35,V.28)
16 (V.11,V.35)
17 (V.11,V.35,V.28)
9 (V.11,V.35)
15 (V.11,V.35,V.28)
12 (V.11,V.35)
5 (V.11,V.28)
13 (V.11)
6 (V.11,V.28)
22 (V.11)
8 (V.11,V.28)
10 (V.11)
RL_RI
RTS_CTS_A
RTS_CTS_B
DTR_DSR_A
DTR_DSR_B
TXD_RXD_A
TXD_RXD_B
TXCE_TXC_A
TXCE_TXC_B
Signal (DTE_DCE)
18 (V.10,V.28)
21 (V.10,V.28)
4 (V.11,V.28)
19 (V.11)
20 (V.11,V.28)
23 (V.11)
2 (V.11,V.35,V.28)
14 (V.11,V.35)
24 (V.11,V.35,V.28)
11 (V.11,V.35)
μ DB-26 Serial Port Connector Pins
SP510
REV. 1.0.1
FIGURE 47. TYPICAL OPERATING CONFIGURATION TO SERIAL PORT CONNECTOR WITH DCE/DTE PROGRAMMABIL-
ITY
SP510
REV. 1.0.1
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
Thermal Considerations
High speed devices like the SP510 dissipate heat during normal operation. Actual power dissipation is a
function of the switching frequency and loading. For maximum system performance and reliability designers
should ensure sufficient air flow. Other commonly used methods for managing heat include heat sinks for
higher powered devices, forced air flow (fans) and lower density board stuffing.
PCB Design
The use of multi layer printed circuit boards is recommended to provide both a better ground plane and a
thermal path for heat dissipation. If possible, the ground plane should face the bottom of the package to form
the thermal conduction plane. Two-sided printed circuit boards may be used where board dimensions and
package count are small, but multi-layer boards allow for improved signal routing as well as improved signal
integrity. A multi layer board allows the use of microstrip line techniques to provide for high speed signal
interconnections. On multi-layer boards route the high speed signal lines on the inner layers.
35
SP510
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
36
REV. 1.0.1
SP510
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.1
REVISION HISTORY
DATE
REVISION
DESCRIPTION
December 2009
Rev 1.0.0
Final datasheet.
June 2011
Rev 1.0.1
Correct type error on mode select tables and update ordering information.
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user’s specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or
to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 2011 EXAR Corporation
Datasheet June 2011.
Send your serial transceiver technical inquiry with technical details to hotline: serialtechsupport@exar.com.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
37
工商网监
湘ICP备2023018690号
