SP510E
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
JANUARY 2020
REV. 1.0.2
GENERAL DESCRIPTION
FEATURES
The SP510E is a highly integrated physical layer
solution that is configurable to support multiple serial
standards. It incorporates eight drivers and eight
receivers (8TX/8RX), configurable for either
differential (V.11 or V.35) or single ended (V.28 and
V.10) signaling.
Up to 52Mbps Differential Transmission Rates
±15kV HBM ESD Tolerance for Analog I/O Pins
Integrated Termination Resistors for V.11/V.35
Eight Drivers and Eight Receivers (8TX/8RX)
Adjustable Logic Level Pin VL (Down to 1.65V)
SP510E enables a Serial Communications Controller
to implement a variety of serial port types including
V.24, V.25, V.36, EIA-530, EIA-530-A, X.21, RS-232.
The device architecture is designed to support the
data and clock signals used in HDLC or SDLC serial
ports as either DTE or DCE.
Software Selectable Protocols with 3-Bit Word:
Operating configuration is programmable in system
using the mode-select pins. The V.11 and V.35 modes
include internal bus termination that may be switched
in or out using the TERM_OFF pin.
Internal Line or Digital Loopback Testing
Adheres to NET1/NET2 and TBR2 Requirements
Easy Flow-Through Pinout
Single +5V Supply Voltage
Individual Driver/Receiver Enable/Disable Controls
Operates in DTE or DCE Mode
Pin Compatible Upgrade for SP509, SP508
- RS-232 (V.28)
- EIA-530 (V.10 & V.11)
- EIA-530A (V.10 & V.11)
- X.21 (V.11)
- RS-449/V.36
The SP510E is ideal for space constrained
applications. It requires only a single 5V supply for full
operation. The VL pin determines the receiver output
voltage (VOH, down to 1.65V), for interfacing with
lower voltage CPUs and FPGAs. For single supply
operation at 5V the VL pin will be connected to VCC.
Fully compliant V.28 and V.10 driver output voltages
are generated using the onboard charge pump.
Special power sequencing is not required during
system startup. Charge pump outputs are internally
regulated to minimize power consumption. The
SP510E requires only four 1µF capacitors for
complete functionality. The device may be put into a
low power shutdown mode when not in active use.
TYPICAL APPLICATIONS
Data Communication Networks
Telecommunication Equipment
Secured Data Communication
CSU and DSU
Data Routers
Network Switches
WAN Access Equipment
VoIP-PBX Gateways
All receivers have fail-safe protection to put outputs
into an output-high state when inputs are open,
shorted, or terminated but idle.
ORDERING INFORMATION(1)
PART NUMBER
OPERATING TEMPERATURE RANGE
PACKAGE
PACKAGING METHOD
LEAD-FREE(2)
SP510EEF-L
-40°C to +85°C
100-pin LQFP
Tray
Yes
SP510ECF-L
0°C to +70°C
100-pin LQFP
Tray
Yes
NOTES:
1. Refer to http://www.maxlinear.com/SP510E for most up-to-date Ordering Information.
2. Visit www.maxlinear.com for additional information on Environmental Rating.
1
SP510E
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.2
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation of the device at these ratings or any other above those
indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum
rating conditions for extended periods of time may affect reliability.
Supply Voltage VCC
+7.0V
Logic-Interface Voltage (VL)
VL VCC
Receiver DC Input Voltage
±15.5V
-0.3V to (VCC + 0.5V)
Input Voltage at TTL Input Pins
Driver Output Voltage (from Ground)
-7.5V to +12.5V
Short Circuit Duration, TxOUT to GND
Continuous
Storage Temperature Range
-65°C to +150°C
Lead Temperature (soldering, 10s)
+300°C
Continuous Power Dissipation at TAMB = +70C
100-Pin LQFP
(derate 19mW/°C above +70°C)
JA = 52.7°C/W, JC = 6.5°C/W
1520mW
ESD PROTECTION
TX Output & RX Input Pins
±15
kV
Human Body Model
All Other Pins
±2
kV
Human Body Model
2
SP510E
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.2
TABLE 1: DC ELECTRICAL CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS
Vcc = +4.75V to +5.25V, C1-C4 = 1µF. TAMB = TMIN to TMAX, unless otherwise noted. Typical values are at TAMB = +25°C
PARAMETERS
VCC Supply Voltage
SYMBOL
VCC
Logic Interface Voltage
VL
ICC Supply Current
ICC
ICC Shutdown
TEST CONDITIONS
VL VCC
MIN
MAX
UNIT
4.75
5.25
V
1.65
5.25
V
300
mA
ICCSD
TYP
200
µA
DRIVER INPUT AND LOGIC INPUT PINS
Logic Input High
VIH
Logic Input Low
VIL
1.6
V
0.4
V
0.4
V
VL+0.3
V
±20
±60
mA
±0.05
±1
µA
±6
±15
V
RECEIVER OUTPUTS
Receiver Logic Output Low
VOL
IOUT = -3.2 mA
Receiver Logic Output High
VOH
IOUT = 1 mA
Receiver Output
Short-Circuit Current
IOSS
0V < VO < VCC
Receiver Output
Leakage Current
IOZ
Receivers disabled
0.4V < VO < 5.25V
VT
Output load = 3k to GND
Figure 3
VL-0.3
V.28 / RS-232 DRIVERS
Output Voltage Swing
Short Circuit Current
±5
VOC
Open Circuit Output
Figure 2
±15
V
ISC
VOUT = 0V, Figure 5
±100
mA
Power-Off Impedance
Figure 6
300
10M
V.28 / RS-232 RECEIVERS
Input Voltage Range
-15
Input Threshold Low
0.8
15
1.2
Input Threshold High
1.7
Input Hysteresis
500
Input Resistance
Open Circuit Bias
Figure 8
VOC
Figure 9
3
3
5
V
V
3
V
mV
7
k
±2
V
SP510E
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.2
DC ELECTRICAL CHARACTERISTICS
Vcc = +4.75V to +5.25V, C1-C4 = 1µF. TAMB = TMIN to TMAX, unless otherwise noted. Typical values are at TAMB = +25°C
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
±6
V
V.10 / RS-423 DRIVERS
Open Circuit Voltage
VOC
Figure 10
±4
Test Terminated Voltage
VT
Figure 11
0.9VOC
Short Circuit Current
ISC
Figure 12
±150
mA
Figure 13
±100
µA
+3.25
mA
Power-Off Current
V
V.10 / RS-423 RECEIVERS
Input Current
IIA
Figure 15 and Figure 16
Input Impedance
-3.25
4
15
Sensitivity
k
±0.2
V
±6
V
V.11 / RS-422 DRIVERS
Open Circuit Voltage
VOCA,VOCB
Figure 17
VT
Figure 18
Balance
VT
Figure 18
±0.4
V
Driver DC Offset
VOS
Figure 18
3
V
VOS
Figure 18
±0.4
V
ISA, ISB
Figure 19
±150
mA
Figure 20
±100
µA
+7
V
Test Terminated Voltage
Offset Balance
Short Circuit Output Current
Power-Off Current
±2
V
V.11 / RS-422 RECEIVERS
Receiver Input Range
VCM
-7
Input Current
IIA, IIB
Figure 21 and Figure 23
±3.25
mV
Input Current with Termination
IIA, IIB
Figure 24 and Figure 25
±60.75
mA
Receiver Input Impedance
RIN
Receiver Sensitivity
VTH
Receiver Input Hysteresis
VTH
-10V VCM +10V
4
15
k
±0.2
VCM = 0 V
4
15
V
mV
SP510E
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.2
DC ELECTRICAL CHARACTERISTICS
Vcc = +4.75V to +5.25V, C1-C4 = 1µF. TAMB = TMIN to TMAX, unless otherwise noted. Typical values are at TAMB = +25°C
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
±0.66
V
±0.6
V
-0.2VST
+0.2VST
V
V.35 DRIVERS (ALL VALUES MEASURED WITH TERM_OFF = ’0’)
Test Terminated Voltage
Offset
VT
Figure 26
VOS
Figure 26
±0.44
Output Overshoot
Figure 26,
VST = Steady State Voltage
Source Impedance
Figure 29
ZS = V2 / V1 x 50
50
150
Short Circuit Impedance
Figure 28
135
165
±200
mV
V.35 RECEIVERS (ALL VALUES MEASURED WITH TERM_OFF = ’0’)
Sensitivity
±100
Source Impedance
Figure 30
ZS = V2 / V1 x 50
90
110
Short-Circuit Impedance
Figure 31
135
165
TRANSCEIVER LEAKAGE CURRENT
Driver Output Tri-state Current
Drivers disabled, Figure 32
Receiver Output Tri-state Current
Tx and Rx Disabled,
0.4V VO 2.4V
5
500
1
µA
10
µA
SP510E
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.2
TABLE 2: AC TIMING CHARACTERISTICS
TIMING CHARACTERISTICS
VCC = +4.75 to 5.25V, C1-C4 = 1µF; TAMB = TMIN to TMAX, unless noted. Typical values are at TAMB = +25°C.
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V.28 / RS-232 DRIVER
Maximum Transmission Rate
Driver Propagation Delay
Figure 7
tDPHL, tDPLH
250
0.5
kbps
1
5
µs
Driver Transition Time
+3V to -3V, Figure 7
0.2
1.5
µs
Instantaneous Slew Rate
+3V to -3V, Figure 4
4
30
V/µs
800
ns
tDPHL - tDPLH
Driver Skew
100
at zero crossing
Driver Channel to Channel Skew
20
Driver Output Enable Time
Tri-state to Output Low
tDZL
Driver Output Enable Time
Tri-state to Output High
tDZH
Driver Output Disable Time
Output Low to Tri-state
tDLZ
Driver Output Disable Time
Output High to Tri-state
tDHZ
CL = 100 pF, S1 closed
Figure 34 and Figure 40
CL = 100 pF, S2 closed
Figure 34 and Figure 40
CL = 15 pF, S1 closed
Figure 34 and Figure 40
CL = 15 pF, S2 closed
Figure 34 and Figure 40
ns
2
µs
2
µs
2
µs
2
µs
500
ns
V.28 / RS-232 RECEIVER
Receiver Propagation Delay
tPHL, tPLH
R_IN to R_OUT, CL = 15 pF
tPHL - tPLHat 1.5V
Receiver Skew
Receiver Channel to Channel Skew
Receiver Output Rise / Fall Time
tR, tF
Receiver Output Enable Time
Tri-state to Output Low
tZL
Receiver Output Enable Time
Tri-state to Output High
tZH
Receiver Output Disable Time
Output Low to Tri-state
tLZ
Receiver Output Disable Time
Output High to Tri-state
tHZ
Charge Pump Rise Time
CL = 15 pF
CL = 100 pF, S1 closed
Figure 35 and Figure 40
CL = 100 pF, S2 closed
Figure 35 and Figure 40
CL = 15 pF, S1 closed
Figure 35 and Figure 40
CL = 15 pF, S2 closed
Figure 35 and Figure 40
Shutdown to operational
6
50
100
50
ns
20
ns
15
ns
2
µs
2
µs
2
µs
2
µs
2
ms
SP510E
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.2
TIMING CHARACTERISTICS
VCC = +4.75 to 5.25V, C1-C4 = 1µF; TAMB = TMIN to TMAX, unless noted. Typical values are at TAMB = +25°C.
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V.10 / RS-423 DRIVER
Maximum Transmission Rate
Driver Propagation Delay
Driver Rise / Fall Time
250
tDPHL, tDPLH
tDR, tDF
30
kbps
150
10% to 90%, Figure 14
tDPHL - tDPLH
Driver Skew
at zero crossing
Driver Channel to Channel Skew
500
ns
500
ns
100
ns
5
Driver Output Enable Time
Tri-state to Output Low
tDZL
Driver Output Enable Time
Tri-state to Output High
tDZH
Driver Output Disable Time
Output Low to Tri-state
tDLZ
Driver Output Disable Time
Output High to Tri-state
tDHZ
CL = 100 pF, S1 closed
Figure 34 and Figure 40
CL = 100 pF, S2 closed
Figure 34 and Figure 40
CL = 15 pF, S1 closed
Figure 34 and Figure 40
CL = 15 pF, S2 closed
Figure 34 and Figure 40
ns
2
µs
2
µs
2
µs
2
µs
500
ns
V.10 / RS-423 RECEIVER
Receiver Propagation Delay
Receiver Output Rise / Fall Time
tPHL, tPLH
tR, tF
Receiver Skew
100
CL = 15 pF
15
ns
tPHL - tPLHat 1.5V
5
ns
5
ns
Receiver Channel to Channel Skew
Receiver Output Enable Time
Tri-state to Output Low
tZL
Receiver Output Enable Time
Tri-state to Output High
tZH
Receiver Output Disable Time
Output Low to Tri-state
tLZ
Receiver Output Disable Time
Output High to Tri-state
tHZ
CL = 100 pF, S1 closed
Figure 35 and Figure 40
CL = 100 pF, S2 closed
Figure 35 and Figure 40
CL = 15 pF, S1 closed
Figure 35 and Figure 40
CL = 15 pF, S2 closed
Figure 35 and Figure 40
7
2
µs
2
µs
2
µs
2
µs
SP510E
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.2
TIMING CHARACTERISTICS
VCC = +4.75 to 5.25V, C1-C4 = 1µF; TAMB = TMIN to TMAX, unless noted. Typical values are at TAMB = +25°C.
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
HIGH SPEED V.11 / RS-422 (DRIVERS 1, 2 & 3)
Maximum Bit Rate
Driver Rise and Fall Time
Driver Propagation Delay Time
52
tDR, tDF
tDPHL, tDPLH
Mbps
10-90%
Figure 22 and Figure 36
CL = 50 pF
Figure 33 and Figure 36
20
tDPHL - tDPLHCL = 50 pF
Driver Skew
Figure 33 and Figure 36
Driver Channel to Channel Skew
6
ns
50
ns
3.8
ns
2
Driver Output Enable Time
Tri-state to Output Low
tDZL
Driver Output Enable Time
Tri-state to Output High
tDZH
Driver Output Disable Time
Output Low to Tri-state
tDLZ
Driver Output Disable Time
Output High to Tri-state
tDHZ
CL = 100 pF, S1 closed
Figure 34 and Figure 37
CL = 100 pF, S2 closed
Figure 34 and Figure 37
CL = 15 pF, S1 closed
Figure 34 and Figure 37
CL = 15 pF, S2 closed
Figure 34 and Figure 37
ns
100
ns
100
ns
100
ns
100
ns
6
ns
50
ns
3.8
ns
HIGH SPEED V.11 / RS-422 (RECEIVERS 1, 2 & 3)
Receiver Output Rise / Fall Time
Receiver Propagation Delay
tR, tF
tPHL, tPLH
CL = 50 pF
CL = 50 pF
Figure 33 and Figure 38
20
tPHL - tPLHCL = 50 pF
Receiver Skew
Figure 33 and Figure 38
Receiver Channel to Channel Skew
2
Receiver Output Enable Time
Tri-state to Output Low
tZL
Receiver Output Enable Time
Tri-state to Output High
tZH
Receiver Output Disable Time
Output Low to Tri-state
tLZ
Receiver Output Disable Time
Output High to Tri-state
tHZ
CL = 100 pF, S1 closed
Figure 35 and Figure 39
CL = 100 pF, S2 closed
Figure 35 and Figure 39
CL = 15 pF, S1 closed
Figure 35 and Figure 39
CL = 15 pF, S2 closed
Figure 35 and Figure 39
8
ns
100
ns
100
ns
100
ns
100
ns
SP510E
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.2
TIMING CHARACTERISTICS
VCC = +4.75 to 5.25V, C1-C4 = 1µF; TAMB = TMIN to TMAX, unless noted. Typical values are at TAMB = +25°C.
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V.11 / RS-422 HANDSHAKE SIGNALS (DRIVERS 4, 5 & 6)
Maximum Bit Rate
Driver Rise and Fall Time
Driver Propagation Delay Time
Figure 33
tDR, tDF
tDPHL, tDPLH
Figure 22 and Figure 36
CL = 50 pF
Figure 33 and Figure 36
10
Mbps
2
10
ns
20
50
ns
10
ns
tDPHL - tDPLH, CL = 50 pF
Driver Skew
Figure 33 and Figure 36
2
Driver Channel to Channel Skew
Driver Output Enable Time
Tri-state to Output Low
tDZL
Driver Output Enable Time
Tri-state to Output High
tDZH
Driver Output Disable Time
Output Low to Tri-state
tDLZ
Driver Output Disable Time
Output High to Tri-state
tDHZ
CL = 100 pF, S1 closed
Figure 34 and Figure 37
CL = 100 pF, S2 closed
Figure 34 and Figure 37
CL = 15 pF, S1 closed
Figure 34 and Figure 37
CL = 15 pF, S2 closed
Figure 34 and Figure 37
ns
100
ns
100
ns
100
ns
100
ns
20
ns
50
ns
10
ns
V.11 / RS-422 HANDSHAKE SIGNALS (RECEIVERS 4, 5 & 6)
Receiver Output Rise / Fall Time
Receiver Propagation Delay
tR, tF
tPHL, tPLH
CL = 50 pF
CL = 50 pF
Figure 33 and Figure 38
20
tPHL - tPLHCL = 50 pF
Receiver Skew
Figure 33 and Figure 38
Receiver Channel to Channel Skew
2
Receiver Output Enable Time
Tri-state to Output Low
tZL
Receiver Output Enable Time
Tri-state to Output High
tZH
Receiver Output Disable Time
Output Low to Tri-state
tLZ
Receiver Output Disable Time
Output High to Tri-state
tHZ
CL = 100 pF, S1 closed
Figure 35 and Figure 39
CL = 100 pF, S2 closed
Figure 35 and Figure 39
CL = 15 pF, S1 closed
Figure 35 and Figure 39
CL = 15 pF, S2 closed
Figure 35 and Figure 39
9
ns
100
ns
100
ns
100
ns
100
ns
SP510E
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.2
TIMING CHARACTERISTICS
VCC = +4.75 to 5.25V, C1-C4 = 1µF; TAMB = TMIN to TMAX, unless noted. Typical values are at TAMB = +25°C.
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
fMAX = 20 MHz, Figure 33
40
TYP
MAX
UNIT
V.35 (DRIVERS 1, 2 & 3)
Maximum Bit Rate
Driver Rise and Fall Time
Driver Propagation Delay Time
tDR, tDF
tDPHL, tDPLH
Figure 29
CL = 50 pF
Figure 33 and Figure 36
tDPHL -
Driver Skew
Mbps
tDPLHCL = 50 pF
Figure 33 and Figure 36
Driver Channel to Channel Skew
10
ns
25
50
ns
2
5
ns
2
Driver Output Enable Time
Tri-state to Output Low
tDZL
Driver Output Enable Time
Tri-state to Output High
tDZH
Driver Output Disable Time
Output Low to Tri-state
tDLZ
Driver Output Disable Time
Output High to Tri-state
tDHZ
CL = 100 pF, S1 closed
Figure 34 and Figure 37
CL = 100 pF, S2 closed
Figure 34 and Figure 37
CL = 15 pF, S1 closed
Figure 34 and Figure 37
CL = 15 pF, S2 closed
Figure 34 and Figure 37
ns
200
ns
200
ns
200
ns
200
ns
50
ns
5
ns
V.35 (RECEIVERS 1, 2 & 3)
Receiver Propagation Delay
tPHL, tPLH
CL = 50 pF
Figure 33 and Figure 38
tPHL -
Receiver Skew
30
tPLHCL = 50 pF
Figure 33 and Figure 38
Receiver Channel to Channel Skew
2
Receiver Output Enable Time
Tri-state to Output Low
tZL
Receiver Output Enable Time
Tri-state to Output High
tZH
Receiver Output Disable Time
Output Low to Tri-state
tLZ
Receiver Output Disable Time
Output High to Tri-state
tHZ
CL = 100 pF, S1 closed
Figure 35 and Figure 39
CL = 100 pF, S2 closed
Figure 35 and Figure 39
CL = 15 pF, S1 closed
Figure 35 and Figure 39
CL = 15 pF, S2 closed
Figure 35 and Figure 39
10
ns
200
ns
200
ns
200
ns
200
ns
SP510E
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.2
FIGURE 1. PIN OUT DIAGRAM
NC
VCC
TR(b)
RRC(b)
VCC
RRC(a)
GND
RS(a)
VCC
RS(b)
GND
ST(a)
VCC
35TGND3
ST(b)
GND
TT(a)
VCC
35TGND2
TT(b)
GND
SD(a)
VCC
35TGND1
SD(b)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
VL
GND
SDEN
TTEN
STEN
RSEN
TREN
RRCEN
RLEN
LLEN#
RDEN#
RTEN#
TXCEN#
CSEN#
DMEN#
RRTEN#
ICEN#
TMEN
D0
D1
D2
TERM_OFF
D_LATCH#
NC
GND
SP510E
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
RT(a)
RT(b)
RD(a)
RD(b)
V35RGND
VL
GND
TM
RI
DCD_DTE
DSR
CTS
TXC
RXC
RXD
LL
RL
DCD_DCE
DTR
RTS
ST
TX_CE
TXD
LOOPBACK
VCC
11
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
TR(a)
GND
VDD
C1P
VCC
C2P
C1N
GND
C2N
VSS1
RL(a)
VCC
LL(a)
TM(a)
IC
RRT(a)
RRT(b)
GNDV10
DM(a)
DM(b)
CS(a)
CS(b)
TXC(a)
GND
TXC(b)
SP510E
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.2
TABLE 3: PIN DESCRIPTIONS BY FUNCTION
PIN NAME
PIN NUMBER
I/O
DESCRIPTION
DIFFERENTIAL DRIVERS
TxD
28
I
TTL
TxD Driver Input
SD(b) / SD(a)
100, 97
O
TTL
Differential Transmit data non-inverting (b) and inverting (a)
outputs
V35TGND1
99
I
SDEN
3
I
TTL
TxD Driver Enable
TxCE
29
I
TTL
TxCE Driver Input
TT(b) / TT(a)
95, 92
O
TTL
Differential TxCE non-inverting (b) and inverting (a) outputs
V35TGND2
94
I
TTEN
4
I
TTL
TxCE Driver Enable
ST
30
I
TTL
ST Driver Input
ST(b) / ST(a)
90, 87
O
TTL
Differential ST non-inverting (b) and inverting (a) outputs
V35TGND3
89
I
STEN
5
I
TTL
ST Driver Enable
RTS
31
I
TTL
RTS Driver Input
RS(b) / RS(a)
85, 83
O
TTL
RSEN
6
I
TTL
RTS Driver Enable
DTR
32
I
TTL
DTR Driver Input
TR(b) / TR(a)
78, 75
O
TTL
Differential DTR non-inverting (b) and inverting (a) outputs
TREN
7
I
TTL
DTR Driver Enable
DCD_DCE
33
I
TTL
DCD_DCE Driver Input
RRC(b) / RRC(a)
79, 81
O
TTL
Differential DCD non-inverting (b) and inverting (a) outputs
RRCEN
8
I
TTL
DCD Driver Enable
RL
34
I
TTL
RL Driver Input
RL(a)
65
O
TTL
RL Driver Output
RLEN
9
I
TTL
RL Driver Enable
LL
35
I
TTL
LL Driver Input
LL(a)
63
O
TTL
LL Driver Output
LLEN#
10
I
TTL
LL Driver Enable, active low
SD Termination Reference
TT Termination Reference
ST Termination Reference
Differential RTS non-inverting (b) and inverting (a) outputs
SINGLE ENDED DRIVERS
12
SP510E
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.2
PIN NAME
PIN NUMBER
I/O
DESCRIPTION
DIFFERENTIAL RECEIVERS
RxD
36
O
TTL
RxD Receiver Output
RD(b) / RD(a)
47, 48
I
TTL
Differential RXD non-inverting (b) and inverting (a) inputs
RDEN#
11
I
TTL
RxD Receiver Enable, active low
RxC
37
O
TTL
RxC Receiver Output
RT(b) / RT(a)
49, 50
I
TTL
Differential RXC non-inverting (b) and inverting (a) inputs
RTEN#
12
I
TTL
RxC Receiver Enable, active low
TxC
38
O
TTL
TxC Receiver Output
TxC(b) / TxC(a)
51, 53
I
TTL
Differential TxC non-inverting (b) and inverting (a) inputs
TxCEN#
13
I
TTL
TxC Receiver Enable, active low
CTS
39
O
TTL
CTS Receiver Output
CS(b) / CS(a)
54, 55
I
TTL
Differential CTS non-inverting (b) and inverting (a) inputs
CSEN#
14
I
TTL
CTS Receiver Enable, active low
DSR
40
O
TTL
DSR Receiver Output
DM(b) / DM(a)
56, 57
I
TTL
Differential DSR non-inverting (b) and inverting (a) inputs
DMEN#
15
I
TTL
DSR Receiver Enable, active low
DCD_DTE
41
O
TTL
DCD_DTE Receiver Output
RRT(b) / RRT(a)
59, 60
I
TTL
Differential DCD_DTE non-inverting (b) and inverting (a)
inputs
RRTEN#
16
I
TTL
DCD_DTE Receiver Enable, active low
IC
61
I
TTL
RI Receiver Input
RI
42
O
TTL
RI Receiver Output
ICEN#
17
I
TTL
RI Receiver Enable, active low
TM(a)
62
I
TTL
TM Receiver Input
TM
43
O
TTL
TM Receiver Output
TMEN
18
I
TTL
TM Receiver Enable
SINGLE ENDED RECEIVERS
13
SP510E
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
PIN NAME
PIN NUMBER
I/O
REV. 1.0.2
DESCRIPTION
PROTOCOL & MODE SELECTION PINS
D2, D1, D0
21, 20, 19
I
TTL
Mode Select - Refer to Table 5 and Table 6
CHARGE PUMP PINS
I
Charge Pump Capacitor 1 +/- inputs. Connect a 1 µF
capacitor between C1P and C1N pins.
I
Charge Pump Capacitor 2 +/- inputs. Connect a 1 µF
capacitor between C2P and C2N pins.
66
I
-2xVCC Charge Pump
73
I
2xVCC Charge Pump
LOOPBACK#
27
I
D_LATCH#
23
I
Decoder Latch, active low
TERM_OFF
22
I
Termination disable
C1P, C1N
72, 69
C2P, C2N
70, 67
VSS1
VDD
GENERAL CONTROL PINS
TTL
Loopback mode enable, active low
RESERVED PINS
NC
24, 76
No Connect
POWER AND GROUND PINS
VCC
26, 64, 71, 77,
80, 84, 88, 98
I
5V supply
VL
1, 45
I
Logic I/O Power Supply Input
GND
2, 25, 44, 52,
68, 74, 82, 86,
91, 96
I
Ground
GNDV10
58
I
V.10 Receiver Ground Reference
V35RGND
46
O
Receiver Termination Reference
NOTE: Pin type: I = Input, O = Output, I/O = Input/output.
14
SP510E
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.2
TABLE 4: PIN DESCRIPTIONS BY PIN NUMBER
PIN DESCRIPTIONS BY PIN NUMBER
1
VL
Logic I/O Power Supply Input
32
DTR
2
DTR Driver TTL Input
GND
Ground
33
DCD_DCE
3
SDEN
TxD Driver Enable Input
34
RL
RL Driver TTL Input
4
TTEN
TxCE Driver Enable Input
35
LL
LL Driver TTL Input
5
STEN
ST Driver Enable Input
36
RxD
RxD Receiver TTL Output
6
RSEN
RTS Driver Enable Input
37
RxC
RxC Receiver TTL Output
7
TREN
DTR Driver Enable Input
38
TxC
TxC Receiver TTL Output
8
RRCEN
DCD Driver Enable Input
39
CTS
CTS Receiver TTL Output
9
RLEN
RL Driver Enable Input
40
DSR
DSR Receiver TTL Output
10
LLEN#
LL Driver Enable Input
41
DCD_DTE
11
RDEN#
RxD Receiver Enable Input
42
RI
RI Receiver TTL Output
12
RTEN#
RxC Receiver Enable Input
43
TM
TM Receiver TTL Output
13
TxCEN#
TxC Receiver Enable Input
44
GND
14
CSEN#
CTS Receiver Enable Input
45
VL
15
DMEN#
DSR Receiver Enable Input
46
V35RGND
16
RRTEN#
DCD_DTE Receiver Enable Input
47
RD(b)
RXD Non-Inverting Input
17
ICEN#
RI Receiver Enable Input
48
RD(a)
RXD Inverting Input
18
TMEN
TM Receiver Enable Input
49
RT(b)
RxC Non-Inverting Input
19
D0
Mode Select Input - Bit 0
50
RT(a)
RxC Inverting Input
20
D1
Mode Select Input - Bit 1
51
TxC(b)
TxC Non-Inverting Input
21
D2
Mode Select Input - Bit 2
52
GND
DCD_DCE Driver TTL Input
DCD_DTE Receiver TTL Output
Ground
Logic I/O Power Supply Input
Receiver Termination Reference
Ground
22
TERM_OFF Termination Disable Input
53
TxC(a)
TxC Inverting Input
23
D_LATCH#
Decoder Latch Input
54
CS(b)
CTS Non-Inverting Input
24
N/C
No Connect
55
CS(a)
CTS Inverting Input
25
GND
Ground
56
DM(b)
DSR Non-Inverting Input
26
VCC
5V Power Supply Input
57
DM(a)
DSR Inverting Input
27
LOOPBACK#
Loopback Mode Enable Input
58
GNDV10
28
TxD
TxD Driver TTL Input
59
RRT(b)
DCD_DTE Non-Inverting Input
29
TxCE
TxCE Driver TTL Input
60
RRT(a)
DCD_DTE Inverting Input
30
ST
ST Driver TTL Input
61
IC
RI Receiver Input
31
RTS
RTS Driver TTL Input
62
TM(a)
TM Receiver Input
15
V.10 Rx Ground Reference
SP510E
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.2
PIN DESCRIPTIONS BY PIN NUMBER
63
LL(a)
LL Driver Output
82
GND
Ground
64
VCC
5V Power Supply Input
83
RS(a)
RTS Inverting Output
65
RL(a)
RL Driver Output
84
VCC
5V Power Supply Input
66
VSS1
-2 x VCC Charge Pump
85
RS(b)
RTS Non-Inverting Output
67
C2N
Charge Pump Capacitor
86
GND
Ground
68
GND
Ground
87
ST(a)
ST Inverting Output
69
C1N
Charge Pump Capacitor
88
VCC
5V Power Supply Input
70
C2P
Charge Pump Capacitor
89
71
VCC
5V Power Supply Input
90
ST(b)
ST Non-Inverting Output
72
C1P
Charge Pump Capacitor
91
GND
Ground
73
VDD
2 x VCC Charge Pump
92
TT(a)
TxCE Inverting Output
74
GND
Ground
93
VCC
5V Power Supply Input
75
TR(a)
DTR Inverting Output
94
76
NC
No Connect
95
TT(b)
TxCE Non-Inverting Output
77
VCC
5V Power Supply Input
96
GND
Ground
78
TR(b)
DTR Non-Inverting Output
97
SD(a)
TxD Inverting Output
79
RRC(b)
DCD Non-Inverting Output
98
VCC
5V Power Supply Input
80
VCC
5V Power Supply Input
99
81
RRC(a)
DCD Inverting Output
100
16
V35TGND3 ST Termination Reference
V35TGND2 TT Termination Reference
V35TGND1 SD Termination Reference
SD(b)
TxD Non-Inverting Output
SP510E
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.2
TABLE 5: DRIVER MODE SELECTION
EIA-530
MODE
X.21
MODE
(V.11)
V.35
MODE
RS-449
MODE
(V.36)
DRIVER OUTPUT PIN
EIA-530A
MODE
MODE (D2, D1, D0)
001
010
011
100
101
110
111
T1OUT(a)
V.11
V.11
V.11
V.35
V.11
V.28
High-Z
TxD(a)
T1OUT(b)
V.11
V.11
V.11
V.35
V.11
High-Z
High-Z
TxD(b)
T2OUT(a)
V.11
V.11
V.11
V.35
V.11
V.28
High-Z
TxCE(a)
T2OUT(b)
V.11
V.11
V.11
V.35
V.11
High-Z
High-Z
TxCE(b)
T3OUT(a)
V.11
V.11
V.11
V.35
V.11
V.28
High-Z
TxC_DCE(a)
T3OUT(b)
V.11
V.11
V.11
V.35
V.11
High-Z
High-Z
TxC_DCE(b)
T4OUT(a)
V.11
V.11
V.11
V.28
V.11
V.28
High-Z
RTS(a)
T4OUT(b)
V.11
V.11
V.11
High-Z
V.11
High-Z
High-Z
RTS(b)
T5OUT(a)
V.10
V.11
V.11
V.28
V.11
V.28
High-Z
DTR(a)
T5OUT(b)
High-Z
V.11
V.11
High-Z
V.11
High-Z
High-Z
DTR(b)
T6OUT(a)
V.11
V.11
V.11
V.28
V.11
V.28
High-Z
DCD_DCE(a)
T6OUT(b)
V.11
V.11
V.11
High-Z
V.11
High-Z
High-Z
DCD_DCE(b)
T7OUT(a)
V.10
V.10
High-Z
V.28
V.10
V.28
High-Z
RL
T8OUT(a)
V.10
V.10
High-Z
V.28
V.10
V.28
High-Z
LL
17
RS-232
MODE
(V.28)
SHUTDOWN
SUGGESTED
SIGNAL
SP510E
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.2
TABLE 6: RECEIVER MODE SELECTION
EIA-530
MODE
X.21
MODE
(V.11)
V.35
MODE
RS-449
MODE
(V.36)
RECEIVER INPUT PIN
EIA-530A
MODE
MODE (D2, D1, D0)
001
010
011
100
101
110
111
R1IN(a)
V.11
V.11
V.11
V.35
V.11
V.28
High-Z
RxD(a)
R1IN(b)
V.11
V.11
V.11
V.35
V.11
High-Z
High-Z
RxD(b)
R2IN(a)
V.11
V.11
V.11
V.35
V.11
V.28
High-Z
RxCE(a)
R2IN(b)
V.11
V.11
V.11
V.35
V.11
High-Z
High-Z
RxCE(b)
R3IN(a)
V.11
V.11
V.11
V.35
V.11
V.28
High-Z
TxC_DTE(a)
R3IN(b)
V.11
V.11
V.11
V.35
V.11
High-Z
High-Z
TxC_DTE(b)
R4IN(a)
V.11
V.11
V.11
V.28
V.11
V.28
High-Z
CTS(a)
R4IN(b)
V.11
V.11
V.11
High-Z
V.11
High-Z
High-Z
CTS(b)
R5IN(a)
V.10
V.11
V.11
V.28
V.11
V.28
High-Z
DSR(a)
R5IN(b)
High-Z
V.11
V.11
High-Z
V.11
High-Z
High-Z
DSR(b)
R6IN(a)
V.11
V.11
V.11
V.28
V.11
V.28
High-Z
DCD_DTE(a)
R6IN(b)
V.11
V.11
V.11
High-Z
V.11
High-Z
High-Z
DCD_DTE(b)
R7IN(a)
V.10
V.10
High-Z
V.28
V.10
V.28
High-Z
RI
R8IN(a)
V.10
V.10
High-Z
V.28
V.10
V.28
High-Z
TM
18
RS-232
MODE
(V.28)
SHUTDOWN
SUGGESTED
SIGNAL
SP510E
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.2
TABLE 7: V.11 & V.35 DRIVERS
TABLE 10: V.11 & V.35 RECEIVERS
INPUTS
OUTPUTS
INPUTS
OUTPUTS
TX_EN#
TX_IN
TX(A)
TX(B)
RX(A) - RX(B)
RO
1
1
0
1
200 mV
1
1
0
1
0
200 mV
0
Open / shorted
1
TABLE 11: V.28 RECEIVERS
TABLE 8: V.28 DRIVERS
INPUTS
OUTPUTS
INPUTS
OUTPUTS
TX_EN#
TX_IN
TX(A)
TX(B)
RX(A) - RX(B)
RO
1
1
< -5V
> 30 k
+3V
0
1
0
> +5V
> 30 k
3V
1
Open / ground
1
TABLE 12: V.10 RECEIVERS
TABLE 9: V.10 DRIVERS
INPUTS
OUTPUTS
INPUTS
OUTPUTS
TX_EN#
TX_IN
TX(A)
TX(B)
RX(A) - RX(B)
RO
1
1
< -4V
> 30 k
+0.3V
0
1
0
> +4V
> 30 k
3V
1
Open / ground
1
19
SP510E
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
FIGURE 2. V.28 DRIVER OUTPUT OPEN CIRCUIT VOLTAGE
A
VOC
C
FIGURE 3. V.28 DRIVER OUTPUT LOADED VOLTAGE
A
VT
3kΩ
C
FIGURE 4. V.28 DRIVER OUTPUT SLEW RATE
A
7kΩ
VT
Oscilloscope
C
Scope used for slew rate
measurement.
20
REV. 1.0.2
SP510E
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.2
FIGURE 5. V.28 DRIVER OUTPUT SHORT CIRCUIT CURRENT
A
Isc
C
FIGURE 6. V.28 DRIVER OUTPUT POWER-OFF IMPEDANCE
V CC = 0V
A
Ix
±2V
C
FIGURE 7. V.28 DRIVER OUTPUT RISE/FALL TIME
A
3kΩ
2500pF
Oscilloscope
C
21
SP510E
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
FIGURE 8. V.28 RECEIVER INPUT IMPEDANCE
A
Iia
±15V
C
FIGURE 9. V.28 RECEIVER INPUT OPEN-CIRCUIT BIAS
A
voc
C
FIGURE 10. V.10 DRIVER OUTPUT OPEN-CIRCUIT VOLTAGE
A
3.9kΩ
VOC
C
22
REV. 1.0.2
SP510E
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.2
FIGURE 11. V.10 DRIVER OUTPUT TEST TERMINATED VOLTAGE
A
Vt
450Ω
C
FIGURE 12. V.10 DRIVER OUTPUT SHORT-CIRCUIT CURRENT
A
Isc
C
FIGURE 13. V.10 DRIVER OUTPUT POWER-OFF IMPEDANCE
VCC = 0V
A
Ix
±0.25V
C
23
SP510E
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
FIGURE 14. V.10 DRIVER OUTPUT TRANSITION TIME
A
Oscilloscope
450Ω
C
FIGURE 15. V.10 RECEIVER INPUT CURRENT
A
Iia
±10V
C
FIGURE 16. V.10 RECEIVER INPUT IV GRAPH
V.10 RECEIVER
+3.25mA
-10V
-3V
+3V
+10V
Maximum Input Current
vesus Voltage
-3.25mA
24
REV. 1.0.2
SP510E
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.2
FIGURE 17. V.11 DRIVER OUTPUT TEST TERMINATED VOLTAGE
A
V
OCA
VOC
3.9kΩ
V
OCB
B
C
FIGURE 18. V.11 DRIVER OUTPUT TEST TERMINATED VOLTAGE
A
50Ω
VT
50Ω
B
V
OS
C
FIGURE 19. V.11 DRIVER OUTPUT SHORT-CIRCUIT CURRENT
A
Isa
Isb
B
C
25
SP510E
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
FIGURE 20. V.11 DRIVER OUTPUT POWER-OFF CURRENT
VCC = 0V
A
Ixa
±0.25V
B
C
VCC = 0V
A
±0.25V
Ixb
B
C
26
REV. 1.0.2
SP510E
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.2
FIGURE 21. V.11 RECEIVER INPUT CURRENT
A
Iia
±10V
B
C
A
±10V
Iib
B
C
27
SP510E
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.2
FIGURE 22. V.11 DRIVER OUTPUT RISE/FALL TIME
A
50Ω
Oscilloscope
50Ω
B
50Ω
C
FIGURE 23. V.11 RECEIVER INPUT IV GRAPH
V.11 RECEIVER
+3.25mA
-10V
-3V
+3V
+10V
Maximum Input Current
versus Voltage
-3.25mA
28
VE
SP510E
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.2
FIGURE 24. V.11 RECEIVER INPUT CURRENT WITH TERMINATION
A
Iia
±6V
100Ω to
150Ω
B
C
A
±6V
100Ω to
150Ω
Iib
B
C
29
SP510E
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
FIGURE 25. V.11 RECEIVER INPUT IV GRAPH WITH TERMINATION
V.11 RECEIVER
w/ Optional Cable Termination
(100Ω to 150Ω)
i [mA] = V [V] / 0.1
i [mA] = V [V] - 3) / 4.0
-6V
-3V
+3V
+6V
i [mA] = V [V] - 3) / 4.0
Maximum Input Current
versus Voltage
i [mA] = V [V] / 0.1
FIGURE 26. V.35 DRIVER OUTPUT TEST TERMINATED VOLTAGE
A
50Ω
VT
50Ω
VOS
B
C
FIGURE 27. V.35 DRIVER OUTPUT SOURCE IMPEDANCE
V1
A
50Ω
24kHz, 550mVp-p
Sine Wave
V2
B
C
30
REV. 1.0.2
SP510E
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.2
FIGURE 28. V.35 DRIVER OUTPUT SHORT-CIRCUIT IMPEDANCE
A
ISC
B
± 2V
C
FIGURE 29. V.35 DRIVER OUTPUT RISE/FALL TIME
A
50Ω
Oscilloscope
50Ω
B
50Ω
C
FIGURE 30. V.35 RECEIVER INPUT SOURCE IMPEDANCE
V1
A
50Ω
24kHz, 550mVp-p
Sine Wave
V2
B
C
31
SP510E
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.2
FIGURE 31. V.35 RECEIVER INPUT SHORT-CIRCUIT IMPEDANCE
A
Isc
B
±2V
C
FIGURE 32. DRIVER OUTPUT CURRENT LEAKAGE TEST
Any one of the three conditions for disabling the driver.
VCC = 0V
1
1
1
D2
D1
D0
A
VCC
IZSC
±10V
Logic “1”
B
32
SP510E
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.2
FIGURE 33. DRIVER / RECEIVER TIMING TEST CIRCUIT
CL1
B
B
TIN
ROUT
A
A
CL2
15pF
fIN (50% Duty Cycle, 2.5VP-P)
FIGURE 34. DRIVER TIMING TEST LOAD CIRCUIT
Output
Under
Test
S1
500Ω
VCC
CL
S2
FIGURE 35. RECEIVER TIMING TEST LOAD CIRCUIT
1KΩ
Test Point
Receiver
Output
VCC
S1
CRL
1KΩ
S2
FIGURE 36. DRIVER PROPAGATING DELAYS
f > 10MHz; tR < 10ns; tF < 10ns
DRIVER
INPUT
DRIVER
OUTPUT
+3V
1.5V
0V
A
1.5V
tPLH
VO 1/2VO
1/2VO
B
tDPLH
DIFFERENTIAL
OUTPUT
VB – VA
tPHL
VO+
0V
VO–
tDPHL
tR
tF
tSKEW = | tDPLH - tDPHL |
33
SP510E
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.2
FIGURE 37. DRIVER ENABLE AND DISABLE TIMES
Mx or Tx_Enable
+3V
1.5V
0V
1.5V
tZL
tLZ
5V
2.3V
A, B
VOL
VOH
A, B
2.3V
0V
Output normally LOW
0.5V
Output normally HIGH
0.5V
tZH
tHZ
FIGURE 38. RECEIVER PROPAGATION DELAYS
f > 10MHz; tR < 10ns; tF < 10ns
V0D2+
0V
A–B
0V
INPUT
V0D2–
OUTPUT
VOH
(VOH - VOL)/2
(VOH - VOL)/2
RECEIVER OUT
VOL
tPHL
tPLH
tSKEW = | tPHL - tPLH |
FIGURE 39. RECEIVER ENABLE AND DISABLE TIMES
f = 1MHz; tR < 10ns; tF < 10ns
DECx +3V
1.5V
RCVRENABLE
0V
1.5V
tLZ
tZL
5V
1.5V
RECEIVER OUT
VIL
Output normally LOW
0.5V
Output normally HIGH
0.5V
VIH
RECEIVER OUT
1.5V
0V
tZH
tHZ
34
SP510E
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.2
FIGURE 40. V.28 (RS-232) AND V.10 (RS-423) DRIVER ENABLE AND DISABLE TIMES
+3V
f = 60kHz; tR < 10ns; tF < 10ns
1.5V
1.5V
Tx_Enable
0V
0V
TOUT
VOL
+3V
tLZ
tZL
VOL - 0.5V
VOL - 0.5V
Output LOW
f = 60kHz; tR < 10ns; tF < 10ns
1.5V
1.5V
Tx_Enable
0V
VOH
tZH
tHZ
Output HIGH
VOH - 0.5V
TOUT
0V
FIGURE 41. TYPICAL V.28 DRIVER OUTPUT WAVEFORM
35
SP510E
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
FIGURE 42. TYPICAL V.10 DRIVER OUTPUT WAVEFORM
FIGURE 43. TYPICAL V.11 DRIVER OUTPUT WAVEFORM
36
REV. 1.0.2
SP510E
REV. 1.0.2
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
FIGURE 44. TYPICAL V.35 DRIVER OUTPUT WAVEFORM
37
SP510E
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.2
FIGURE 45. FUNCTIONAL DIAGRAM
+5V (decoupling capacitor not shown)
VCC pins (26, 64, 71, 77, 80, 84, 88, 93, 98)
GND pins (2, 25, 44, 52, 68, 74, 82, 86, 91, 96)
VL pins (1 and 46)
N.C. pins (24 and 76)
Logic Voltage
1μF
1μF
72
1μF
VCC
VL
73 VDD
C1+
69
C1-
70
C2+
67
C2-
VSS
66
Regulated Charge Pump
1μF
V35RGND
RD(a)
RxD
RDEN
46
48
28
97
99
100
3
36
11
47
RD(b)
29
92
94
95
4
50
RT(a)
RT(b)
37
12
49
TxC(a)
53
RxC
RTEN
TxC
TxCEN
38
13
TxC(b)
51
CS(a)
55
CS(b)
39
14
54
DM(a)
57
CTS
CSEN
DSR
DMEN
40
15
DM(b)
56
RRT(a)
60
DCD_DTE
RRTEN
RRT(b)
IC
RI
ICEN
30
87
89
90
5
10
23
22
27
ST
ST(a)
V35TGND3
ST(b)
STEN
DCD_DCE
63
V.10-GND
TTEN
33
81
35
SP510E
TT(b)
TR(b)
65
D1
V35TGND2
78
7
42
17
21
TT(a)
DTR
34
20
TxCE
32
75
61
D0
SDEN
RS(b)
8
19
SD(b)
85
6
9
TM
TMEN
V35TGND1
RTS
79
43
18
SD(a)
31
83
41
16
59
62
TM(a)
TxD
RS(a)
RSEN
TR(a)
TREN
RRC(a)
RRC(b)
RRCEN
RL
RL(a)
RLEN
LL
LL(a)
LLEN
58
D2
D-LATCH
TERM-OFF
LOOPBACK
GND
RECEIVER TERMINATION NETWORK
V.35 MODE
V.11 MODE
V.35 DRIVER TERMINATION NETWORK
51ohms
51ohms
V.35 MODE
124ohms
124ohms
TX ENABLE
RX ENABLE
51ohms
51ohms
38
SP510E
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.2
FIGURE 46. SP510E LOOPBACK PATH
SD(a)
TxD
SD(b)
RD(a)
RxD
RD(b)
TT(a)
TxCE
TT(b)
RT(a)
RxC
RT(b)
ST(a)
ST
ST(b)
TxC(a)
TxC
TxC(b)
RS(a)
RTS
RS(b)
CS(a)
CTS
CS(b)
TR(a)
DTR
TR(b)
DM(a)
DSR
DM(b)
RRC(a)
DCD_DCE
RRC(b)
RRT(a)
DCD_DTE
RRT(b)
RL
RL(a)
RI
IC
LL
LL(a)
TM
TM(a)
FIGURE
47.
39
40
+5V
DTE
10μ F
TM
RI
DCD_DTE
DSR
CTS
TxC
RxC
RxD
LL
RL
DCD_DCE
DTR
RTS
ST
TxCE
TxD
C1+
1μ F
RDEN
RTEN
TxCEN
DMEN
CSEN
RRTEN
ICEN
TMEN
GND
D2
D1
D0
V10_GND
V35RGND
V35TGND3
V35TGND2
V35TGND1
LOOPBACK
TERM_OFF
D_LATCH
SP510E
Logic Section
Transceiver Section
VSS
1μ F
Logic Voltage
C1- C2+ C2- VL
1μ F
Charge Pump Section
VDD
SDEN
TTEN
STEN
TREN
RSEN
RRCEN
RLEN
LLEN
VCC
1μ F
+5V
SIGNAL GND (10 Pins )
25 (V.10,V.28)
Date:
Title :
Customer:
Reference Design Schematic
Doc. #:
Typical SP508 DB-26 Serial Port Configuration
LL_TM
RI_RL
RXD_TXD_A
RXD_TXD_B
RXC_TXCE_A
RXC_TXCE_B
*TXC_RXC_A
*TXC_RXC_B
CTS_RTS_A
CTS_RTS_B
DSR_DTR_A
DSR_DTR_B
DCD_DCD_A
DCD_DCD_B
22 (V.10,V.28)
LL_TM
3 (V.11,V.35, V.28)
16 (V.11,V.35)
17 (V.11,V.35, V.28)
9 (V.11,V.35)
15 (V.11,V.35, V.28)
12 (V.11,V.35)
5 (V.11,V.28)
13 (V.11)
6 (V.11,V.28)
22 (V.11)
8 (V.11,V.28)
10 (V.11)
RL_RI
RTS_CTS_A
RTS_CTS_B
DTR_DSR_A
DTR_DSR_B
TXD_RXD_A
TXD_RXD_B
TXCE_TXC_A
TXCE_TXC_B
Signal (DTE_DCE)
18 (V.10,V.28)
21 (V.10,V.28)
4 (V.11,V.28)
19 (V.11)
20 (V.11,V.28)
23 (V.11)
2 (V.11,V.35, V.28)
14 (V.11,V.35)
24 (V.11,V.35, V.28)
11 (V.11,V.35)
μ DB-26 Serial Port Connector Pins
0
Rev.
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
Input Line
Output Line
I/O Lines represented by double arrowhead signifies a bi-directional bus.
* - Driver applies f or DCE only on pins 15 and 12.
Receiver applies for DTE only on pins 15 and 12.
Driver applies f or DCE only on pins 8 and 10.
Receiver applies for DTE only on pins 8 and 10.
DCE/DTE
#142 (TM)
#125 (RI)
#109 (DCD)
#107 (DSR)
#106 (CTS)
#114 (TxC)
#115 (RXC)
#105 (RXD)
#141 (LL)
#140 (RL)
#109 (DCD)DCE
#108 (DTR)
#105 (RTS)
#113 (TXCE)
#103 (TxD)
+5V
SP510E
REV. 1.0.2
FIGURE 48. TYPICAL CONFIGURATION TO SERIAL PORT CONNECTOR WITH DCE/DTE PROGRAMMABILITY
SP510E
REV. 1.0.2
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
Thermal Considerations
High speed devices like the SP510E dissipate heat during normal operation. Actual power dissipation is a
function of the switching frequency and loading. For maximum system performance and reliability designers
should ensure sufficient air flow. Other commonly used methods for managing heat include heat sinks for
higher powered devices, forced air flow (fans) and lower density board stuffing.
PCB Design
The use of multi layer printed circuit boards is recommended to provide both a better ground plane and a
thermal path for heat dissipation. If possible, the ground plane should face the bottom of the package to form
the thermal conduction plane. Two-sided printed circuit boards may be used where board dimensions and
package count are small, but multi-layer boards allow for improved signal routing as well as improved signal
integrity. A multi-layer board allows microstrip line techniques for high speed signal interconnections when the
high speed signal lines on the inner layers.
41
SP510E
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.2
`
42
SP510E
ULTRA HIGH SPEED MULTIPROTOCOL TRANSCEIVER
REV. 1.0.2
REVISION HISTORY
DATE
REVISION
DESCRIPTION
July 2012
1.0.0
Production Release
February 2014
1.0.1
Updated Exar logo and package drawing, corrected typo in tables 5 & 6.
January 2020
1.0.2
Update to MaxLinear logo. Update ordering information.
MaxLinear, Inc.
5966 La Place Court, Suite 100
Carlsbad, CA 92008
760.692.0711 p.
760.444.8598 f.
www.maxlinear.com
The content of this document is furnished for informational use only, is subject to change without notice, and should not be construed as a commitment by
MaxLinear, Inc. MaxLinear, Inc. assumes no responsibility or liability for any errors or inaccuracies that may appear in the informational content contained in
this guide. Complying with all applicable copyright laws is the responsibility of the user. Without limiting the rights under copyright, no part of this document
may be reproduced into, stored in, or introduced into a retrieval system, or transmitted in any form or by any means (electronic, mechanical, photocopying,
recording, or otherwise), or for any purpose, without the express written permission of MaxLinear, Inc.
Maxlinear, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be
expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless MaxLinear, Inc. receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all
such risks; (c) potential liability of MaxLinear, Inc. is adequately protected under the circumstances.
MaxLinear, Inc. may have patents, patent applications, trademarks, copyrights, or other intellectual property rights covering subject matter in this document.
Except as expressly provided in any written license agreement from MaxLinear, Inc., the furnishing of this document does not give you any license to these
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