SP6123CN-L

® SP6123/SP6123A Low Voltage, Synchronous Step-Down PWM Controller Ideal for 2A to 10A, Small Footprint, DC-DC Power Converters FEATURES ■ Optimized for Single Supply, 3V - 5.5V Applications 8 BST GL 1 ■ High Efficiency: Greater Than 95% Possible SP6123 7 GH VCC 2 8 Pin nSOIC ■ Accurate Fixed 300kHz (SP6123) or 500kHz GND 3 6 SWN (SP6123A) Frequency Operation 5 VFB COMP 4 ■ Fast Transient Response ■ Internal Soft Start Circuit Now Available in Lead Free Packaging ■ Accurate 0.8V Reference Allows Low Output Voltages APPLICATIONS ■ Resistor Programmable Output Voltage ■ DSP ■ Loss-less Current Limit with High Side RDS(ON) ■ Microprocessor Core Sensing ■ I/O & Logic ■ Hiccup Mode Current Limit Protection ■ Industrial Control ■ Dual N-Channel MOSFET Synchronous Driver ■ Distributed Power ■ Quiescent Current: 500µA, 30µA in Shutdown ■ 8-Pin Surface Mount Package ■ Low Voltage Power DESCRIPTION The SP6123 is a fixed frequency, voltage mode, synchronous PWM controller designed to work from a single 5V or 3.3V input supply, providing excellent AC and DC regulation for high efficiency power conversion. Requiring only few external components, the SP6123 packaged in an 8-pin NSOIC, is especially suited for low voltage applications where cost, small size and high efficiency are critical. The operating frequency is internally set to 300kHz (SP6123) or 500kHz (SP6123A), allowing small inductor values and minimizing PC board space. The SP6123 drives an all N-channel synchronous power MOSFET stage for improved efficiency and includes an accurate 0.8V reference for low output voltage applications. TYPICAL APPLICATION CIRCUIT 3V to 5.5V IN MBR0530 VIN CB 2.2µF GL BST VCC GH GND COMP CIN 680µF CBST 1µF 0.8V to 5.0V 2A to 10A (1.6V, 4A shown) FDS6890A SP6123A L1 SWN VOUT 1.5µH VFB R1 10k CP 56pF RZ 15k COUT1 470µF COUT2 470µF COUT3 1µF CC 4.7nF R2 10k FDS6890A STPS2L25U Date: 9/13/04 SP6123 Low Voltage, Synchronous Step Down PWM Controller 1 © Copyright 2004 Sipex Corporation ABSOLUTE MAXIMUM RATINGS These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. All other pins ................................ -0.3V to VCC + 0.3V VCC ....................................................................................................... 7V BST .................................................................. 13.2V BST-SWN .............................................................. 7V Power Dissipation Lead Temperature (Soldering, 10 sec) ............ 300°C ESD Rating. ................................................ 2kV HBM Peak Output Current < 10µs GH,GL .................................................................. 2A Storage Temperature ........................ -65°C to 150°C ELECTRICAL CHARACTERISTICS Unless otherwise specified: 0°C < TA < 70°C, 3.0V < VCC < 5.5V, CCOMP = 22nF, CGH = CGL = 3.3nF, VFB = 0.8V, SWN = GND=0V, typical value for design guideline only. PARAMETER MIN TYP MAX UNITS CONDITIONS QUIESCENT CURRENT VCC Supply Current 0.5 1.0 mA No Switching VCC Supply Current (Disabled) 30 60 µA COMP = 0V ERROR AMPLIFIER Error Amplifier Transconductance 0.6 mS COMP Sink Current 15 35 60 µA VFB = 0.9V, COMP = 0.9V, No Faults COMP Source Current 15 35 60 µA VFB = 0.7V, COMP = 2V COMP Output Impedance 3 VFB Input Bias Current Error Amplifier Reference 0.788 0.8 MΩ 100 nA 0.812 V Trimmed with Error Amp in Unity Gain OSCILLATOR & DELAY PATH Internal Oscillator Frequency 270 300 330 kHz SP6123 Internal Oscillator Frequency 450 500 550 kHz SP6123A Max. Controlled Duty Cycle 90 93 Minimum Duty Cycle Minimum GH Pulse Width % 0 % Comp=0.7V 100 250 ns VCC > 4.5V, Ramp up COMP voltage until GH starts switching 200 240 mV VCC - VSWN ; Temp = 25 °C; VBST - VCC > 2.5V CURRENT LIMIT Internal Current Limit Threshold 160 Current Limit Threshold Temperature Coefficient Current Limit Time Constant 0.34 %/C 15 us SOFT START, SHUTDOWN, UVLO Internal Soft Start Slew Rate SP6123A SP6123 0.60 0.3 0.95 0.6 COMP Discharge Current 185 µA COMP = 0.5V, Fault Initiated COMP Clamp Voltage 0.55 0.65 0.75 V VFB = 0.9V 65 µA COMP = 0.5V, VFB = 0.9V COMP Clamp Current 0.2 0.1 10 Shutdown Threshold Voltage 30 0.39 V Measured at COMP Pin 2 5 10 µA COMP = 0.2V, Measured at COMP pin VCC Start Threshold 2.63 2.8 2.95 V VCC Stop Threshold 2.47 2.7 2.9 V Shutdown Input Pull-up Current Date: 9/13/04 0.29 0.34 V/ms V/ms SP6123 Low Voltage, Synchronous Step Down PWM Controller 2 © Copyright 2004 Sipex Corporation ELECTRICAL CHARACTERISTICS Unless otherwise specified: 0°C < TA < 70°C, 3.0V < VCC < 5.5V, CCOMP = 22nF, CGH = CGL = 3.3nF, VFB = 0.8V, SWN = GND=0V, typical value for design guideline only. PARAMETER MIN TYP MAX UNITS CONDITIONS GATE DRIVERS GH Rise Time 110 ns VCC > 4.5V GH Fall Time 110 ns VCC > 4.5V GL Rise Time 110 ns VCC > 4.5V GL Fall Time 110 ns VCC > 4.5V GH to GL Non-Overlap Time 100 ns VCC > 4.5V GL to GH Non-Overlap Time 100 ns VCC > 4.5V PIN DESCRIPTION PIN N0. PIN NAME DESCRIPTION 1 GL High current driver output for the low side MOSFET switch. It is always low if GH is high. GL swings from GND to VCC. 2 VCC Positive input supply for the control circuitry and the low side gate driver. Properly bypass this pin to GND with a low ESL/ESR ceramic capacitor. 3 GND Ground pin. Both power and control circuitry of the IC is referenced to this pin. 4 COMP 5 VFB 6 SWN Lower supply rail for the GH high-side gate driver. It also connects to the Current Limit comparator. Connect this pin to the switching node at the junction between the two external power MOSFET transistors. This pin monitors the voltage drop across the RDS(ON) of the high side N-channel MOSFET while it is conducting. When this drop exceeds the internal 200mV threshold, the overcurrent comparator sets the fault latch and terminates the output pulses. The controller stops switching and goes through a hiccup sequence. This prevents excessive power dissipation in the external power MOSFETS during an overload condition. An internal delay circuit prevents that very short and mild overload conditions, that could occur during a load transient, from activating the current limit circuit. 7 GH High current driver output for the high side MOSFET switch. It is always low if GL is high or during a fault. GH swings from SWN to BST. 8 BST High side driver supply pin. Connect BST to the external boost diode and capacitor as shown in the application schematic of page #1. Voltage between BST and SWN should not exceed 5.5V. Date: 9/13/04 Output of the Error Amplifier. It is internally connected to the non-inverting input of the PWM comparator. A lead-lag network is typically connected to the COMP pinto compensate the feedback loop in order to optimize the dynamic performance of the voltage mode control loop. Sleep mode can be invoked by pulling the COMP pin below 0.3V with an external open-drain or open-collector transistor. Supply current is reduced to 30µA (typical) in shutdown. An internal 5µA pull-up ensures start-up. Feedback Voltage Pin. It is the inverting input of the Error Amplifier and serves as the output voltage feedback point for the Buck converter. The output voltage is sensed and can be adjusted through an external resistor divider. SP6123 Low Voltage, Synchronous Step Down PWM Controller 3 © Copyright 2004 Sipex Corporation BLOCK DIAGRAM 1V Reference 0.8V - DRIVER ENABLE + SHUTDOWN FAULT + SOFTSTART 350mV GM ERROR AMP 5µA PWM COMP - RESET Dominant PWM Logic R - + VFB 5 8 BST + 7 GH Synchronous Driver 1 GL Q S COMP 4 6 SWN VCC 2 UVLO 750mV RAMP 2.8V ON 2.7V OFF GH + Reset Dominant COMP S Q Over Current (Gated S&H) + X 2.5 SWN 3 GND F = 300kHz; SP6123 F = 500kHz; SP6123A SHUTDOWN FAULT R + 500mV (4000 ppm/°C) - OPERATION General Overview MOSFET switch allowing for significant efficiency improvements. The SP6123 includes two fast MOSFET drivers with internal non-overlap circuitry and drives a pair of N-channel power transistors. The SP6123 includes an internal soft-start circuit that provides controlled ramp up of the output voltage, preventing overshoot and inrush current at power up. The SP6123 is a constant frequency, voltage mode, synchronous PWM controller designed for low voltage, DC/DC step down converters. It is intended to provide complete control for a high power, high efficiency, precisely regulated output voltage from a highly integrated 8-pin solution. The internal free-running oscillator accurately sets the PWM frequency at 300kHz or 500kHz without requiring any external elements and allows the use of physically small, low value external components without compromising performance. A transconductance amplifier is used for the error amplifier, which compares an attenuated sample of the output voltage with a precision, 0.8V reference voltage. The output of the error amplifier (COMP), is compared to a 0.75V peak-to-peak ramp waveform to provide PWM control. The COMP pin provides access to the output of the error amplifier and allows the use of external components to stabilize the voltage loop. Current limiting is implemented by monitoring the voltage drop across the RDS(ON) of the high side N-channel MOSFET while it is conducting, thereby eliminating the need for an external sense resistor. The overcurrent comparator has a built-in threshold of 200mV . When the overcurrent threshold is exceeded, the overcurrent comparator sets the fault latch and terminates the output pulses. The controller stops switching and goes through a hiccup sequence. This prevents excessive power dissipation in the external power MOSFETs during an overload condition. An internal delay circuit prevents that very short and mild overload conditions, that could occur during a load transient, activate the current limit circuit. High efficiency is obtained through the use of synchronous rectification. Synchronous regulators replace the catch diode in the standard buck converter with a low R DS(ON) N-channel Date: 9/13/04 SP6123 Low Voltage, Synchronous Step Down PWM Controller 4 © Copyright 2004 Sipex Corporation OPERATION OPERATION: continued Soft Start A low power sleep mode can be invoked in the SP6123 by externally forcing the COMP pin below 0.3V. Quiescent supply current in sleep mode is typically less than 30µA. An internal 5µA pull-up current at the COMP pin brings the SP6123 out of shutdown mode. Soft start is required on step-down controllers to prevent excess inrush current through the power train during start-up. Typically this is managed by sourcing a controlled current into a timing capacitor and then using the voltage across this capacitor to slowly ramp up either the error amp reference or the error amp output (COMP). The control loop creates narrow width driver pulses while the output voltage is low and allows these pulses to increase to their steady-state duty cycle as the output voltage increases to its regulated value. As a result of controlling the inductor volt*second product during startup, inrush current is also controlled. An internal 0.8V 1.5% reference allows output voltage adjustment for low voltage applications. The SP6123 also includes an accurate undervoltage lockout that shuts down the controller when the input voltage falls below 2.7V. Output overvoltage protection is achieved by turning off the high side switch and turning on the low side N-channel MOSFET 100% of the time. Enable In the SP6123 the duration of the soft-start is controlled by an internal timing circuit that provides a 0.27V/ms slew-rate, which is used during startup and overcurrent to set the hiccup time. The SP6123 implements soft-start by ramping up the error amplifier reference voltage providing a controlled slew-rate of the output voltage, thereby preventing overshoot and inrush current at power up. Low quiescent mode or “Sleep Mode” is initiated by pulling the COMP pin below 0.3V with an external open-drain or open-collector transistor. Supply current is reduced to 30µA (typical) in shutdown. On power-up, assuming that VCC has exceeded the UVLO start threshold (2.8V), an internal 5µA pull-up current at the COMP pin brings the SP6123 out of shutdown mode and ensures start-up. During normal operating conditions and in absence of a fault, an internal clamp prevents the COMP pin from swinging below 0.6V. This guarantees that during mild transient conditions, due either to line or load variations, the SP6123 does not enter shutdown unless it is externally activated. The presence of the output capacitor creates extra current draw during startup. Simply stated, dVOUT/dt requires an average sustained current in the output capacitor and this current must be considered while calculating peak inrush current and over current thresholds. An approximate expression to determine the excess inrush current due to the dVOUT/dt of the output capacitor COUT is: During Sleep Mode, the high side and low side MOSFETS are turned off and the internal soft start voltage is held low. VOUT Iinrush = COUT x SSS x 0.8V UVLO Where, Assuming that there is not shutdown condition present, then the voltage on the VCC pin determines operation of the SP6123. As VCC rises, the UVLO block monitors VCC and keeps the high side and low side MOSFETS off and the internal SS voltage low until VCC reaches 2.8V. If no faults are present, the SP6123 will initiate a soft start when VCC exceeds 2.8 V. SSS = Softstart slew rate, 0.6V/ms for SP6123A and 0.3V/ms for SP6123. As the figure shows, the SS voltage controls a variety of signals. First, provided all the external fault conditions are removed, an internal 5µA pull-up at the COMP pin brings the SP6123 out of shutdown mode. The internal timing circuit is then activated and controls the rampup of the error amp reference voltage. The COMP pin is pulled to 0.7V by the internal Hysteresis (about 100mV) in the UVLO comparator provides noise immunity at start-up. Date: 9/13/04 SP6123 Low Voltage, Synchronous Step Down PWM Controller 5 © Copyright 2004 Sipex Corporation OPERATION Hiccup Mode clamp and then gradually charges preventing the error amplifier from forcing the loop to maximum duty cycle. As the COMP voltage crosses about 1V (valley voltage of the PWM ramp), the driver begins to switch the high side MOSFET with narrow pulses in an effort to keep the converter output regulated . The SP6123 operates at low duty cycle as the COMP voltage increases above 1V. As the error amp reference ramps upward, the driver pulses widen until a steady state value is reached and the output voltage is regulated to the final value ending the soft start charge cycle. When the converter enters a fault mode, the SP6123 holds the high side and low side MOSFETs off for a finite period of time. Provided that the SP6123 is enabled, this time is set by the internal charge of the soft-start capacitor. In the event of an overcurrent condition, the current sense comparator sets the fault latch, which in turn discharge the internal SS capacitor, the COMP pin and holds the output drivers off. During this condition, the SP6123 stays off for the time it takes to discharge the COMP pin down to the 0.27V shutdown threshold. At this point, the fault latch is reset, but before the SP6123 is allowed to attempt restart, the COMP pin has to charge back to 1V before any output switching can be initiated. Then, the regulator attempts to restart normally by delivering short gate pulses and if the overcurrent condition is still present, the cycle will repeat itself. However, if upon restart, the overcurrent condition is still present, the SP6123 will detect the fault and remain in a fault state until COMP reaches about VCC-1V thereby increasing the MOSFET offtime. This protection scheme minimizes thermal stress to the regulator components as the overcurrent condition persists. COMP 1V 0.7 V 0.3 V 0V Internal SS Voltage Error Amp Reference Voltage 0.8 V VOUT = VREF * (1+R1/R2) The simplified waveforms that describe the hiccup mode operation are shown below. 0V VCC-VSWN I(L) 200 mV Inductor Current 0V 0A VCOMP 3V V(VCC) FAULT 0V 1.0 V 0.3 V V(VCC) VBST GH Voltage SWN Voltage 0V VSWN TIME TIME Date: 9/13/04 SP6123 Low Voltage, Synchronous Step Down PWM Controller 6 © Copyright 2004 Sipex Corporation OPERATION A more detailed description of the waveform is shown below. SP6123 OVER CURRENT (HICCUP MODE) Test Conditions VFB = 0.7V VCC = 5.0V BST = 5.0V SWN - tied to GND through 1k Resistor COMP – released from GND Overcurrent Detected GH Turns Off (Fault Mode Enabled) Internal SSTART rises until ~ VCC-1V, then gives command to attempt RESTART GH COMP Clamps ~ 3V COMP After pop, COMP retains internal SSTART slope ENABLE Part 5µA PULLUP slope to 0.3V; 35µA PULLUP to 0.7V Attempt RESTART Date: 9/13/04 SP6123 Low Voltage, Synchronous Step Down PWM Controller 7 Internal SSTART passes V(VFB), COMP pops to ~ internal SSTART voltage +0.7V © Copyright 2004 Sipex Corporation OPERATION Over Current Protection lems in the external MOSFETs. Over current protection on the SP6123 is implemented through detection of an excess voltage condition across the high side NMOS switch during conduction. This is typically referred to as high side RDS(ON) detection and eliminates the need of an external sense resistor. The over current comparator charges an internal sampling capacitor each time V(VCC)-V(SWN) exceeds the 200mV (typ) internal threshold and the GH voltage is high. The discharge/charge current ratio on the sampling capacitor is about 2%. Therefore, provided that the over current condition persists, the capacitor voltage will be pumped up during each time GH switches high. This voltage will trigger an over current condition upon reaching a CMOS inverter threshold. There are many advantages to this approach. First, the filtering action of the gated scheme protects against false and undesirable triggering that could occur during a minor transient overload condition or supply line noise. Furthermore, the total amount of time to trigger the fault depends on the on-time of the high side NMOS switch. Fifteen, 1µs pulses are equivalent to thirty, 500ns pulses or one, 15µs pulse, however, depending on the period, each scenario takes a different amount of total time to trigger a fault. Therefore, the fault becomes an indicator of average power in the high side switch. The 200mV overcurrent threshold has a 3400 ppm/°C temperature coefficients in an effort to first order match the thermal characteristics of the RDS(ON) of the high side NMOS switch. It assumed that the SP6123 will be used in compact designs where there is a high amount of thermal coupling between the high side switch and the controller. The following figure shows typical waveforms for the output drivers. As with all synchronous designs, care must be taken to ensure that the MOSFETs are properly chosen for non-overlap time, enhancement gate drive voltage, “on” resistance RDS(ON), reverse transfer capacitance Crss, input voltage and maximum output current. GATE DRIVER TEST CONDITIONS 5V FALL TIME GH(GL) 2V 10 % 5V 90 % GL(GH) RISE TIME 2V 10 % NON-OVERLAP V(BST) GH Voltage 0V V(VCC) GL Voltage 0V V(VCC=VIN) SWN Voltage ~0V Output Drivers - V(Diode) V The SP6123, unlike some other bipolar controller IC’s, incorporates gate drivers with rail-torail swing that help prevent spurious turn on due to capacitive coupling. The driver stage consists of one high side NMOS, 4Ω driver, GH, and one low side, 4 Ω, NMOS driver, GL, optimized for driving external power MOSFET’s in a synchronous buck topology. The output drivers also provide gate drive non-overlap mechanism that provides a dead time between GH and GL transitions to avoid potential shoot-through probDate: 9/13/04 90 % ~ 2*V(VIN) BST Voltage ~ V(VIN) TIME SP6123 Low Voltage, Synchronous Step Down PWM Controller 8 © Copyright 2004 Sipex Corporation APPLICATIONS INFORMATION a gradual saturation characteristic but can introduce considerable ac core loss, especially when the inductor value is relatively low and the ripple current is high. Ferrite materials, on the other hand, are more expensive and have an abrupt saturation characteristic with the inductance dropping sharply when the peak design current is exceeded. Nevertheless, they are preferred at high switching frequencies because they present very low core loss and the design only needs to prevent saturation. Inductor Selection There are many factors to consider in selecting the inductor including cost, efficiency, size and EMI. In a typical SP6123 circuit, the inductor is chosen primarily for value, saturation current and DC resistance. Increasing the inductor value will decrease output voltage ripple, but degrade transient response. Low inductor values provide the smallest size, but cause large ripple currents, poor efficiency and more output capacitance to smooth out the larger ripple current. The inductor must also be able to handle the peak current at the switching frequency without saturating, and the copper resistance in the winding should be kept as low as possible to minimize resistive power loss. A good compromise between size, loss and cost is to set the inductor ripple current to be within 20% to 40% of the maximum output current. The power dissipated in the inductor is equal to the sum of the core and copper losses. To minimize copper losses, the winding resistance needs to be minimized, but this usually comes at the expense of a larger inductor. Core losses have a more significant contribution at low output current where the copper losses are at a minimum, and can typically be neglected at higher output currents where the copper losses dominate. Core loss information is usually available from the magnetic vendor. The switching frequency and the inductor operating point determine the inductor value as follows: L= VOUT (V IN (max) − VOUT ) The copper loss in the inductor can be calculated using the following equation: VIN (max) FS Kr I OUT ( max) PL( Cu) = I L2 ( RMS ) RWINDING where: where IL(RMS) is the RMS inductor current that can be calculated as follows: FS = switching frequency Kr = ratio of the peak to peak inductor ripple current to the maximum output current IL(RMS) = IOUT(max) 1 + The peak to peak inductor ripple current is: I PP = IOUT(max) ) 2 The required ESR (Equivalent Series Resistance) and capacitance drive the selection of the type and quantity of the output capacitors. The ESR must be small enough that both the resistive voltage deviation due to a step change in the load current and the output ripple voltage do not exceed the tolerance limits expected on the output voltage. During an output load transient, the output capacitor must supply all the additional current demanded by the load until the SP6123 adjusts the inductor current to the new value. Therefore the capacitance must be large enough so that the output voltage is held up while the inductor current ramps up or down to VI N (max) FS L Once the required inductor value is selected, the proper selection of core material is based on peak inductor current and efficiency requirements. The core material must be large enough not to saturate at the peak inductor current I PP 2 and provide low core loss at the high switching frequency. Low cost powdered iron cores have Date: 9/13/04 ( IPP Output Capacitor Selection VOUT (VIN (max) − VOUT ) I PEAK = I OUT (max) + 1 3 SP6123 Low Voltage, Synchronous Step Down PWM Controller 9 © Copyright 2004 Sipex Corporation APPLICATIONS INFORMATION the value corresponding to the new load current. Additionally, the ESR in the output capacitor causes a step in the output voltage equal to the ESR value multiplied by the change in load current. Because of the fast transient response provided by the SP6123 when exposed to output load transient, the output capacitor is typically chosen for ESR , not for capacitance value. pacitors. These capacitors have a lower ESR than tantalum capacitors, reducing the total number of capacitance required for a given transient response. Input Capacitor Selection The input capacitor should be selected for ripple current rating, capacitance and voltage rating. The input capacitor must meet the ripple current requirement imposed by the switching current. In continuous conduction mode, the source current of the high-side MOSFET is approximately a square wave of duty cycle VOUT/ VIN. Most of this current is supplied by the input bypass capacitors. The RMS value of input capacitor current is determined at the maximum output current and under the assumption that the peak to peak inductor ripple current is low, it is given by: The output capacitor’s ESR, combined with the inductor ripple current, is typically the main contributor to output voltage ripple. The maximum allowable ESR required to maintain a specified output voltage ripple can be calculated by: RESR ≤ ∆VOUT I PP where: ∆VOUT = peak to peak output voltage ripple IPP = peak to peak inductor ripple current ICIN(rms) = IOUT(max) √D(1 - D) The worse case occurs when the duty cycle, D, is 50% and gives an RMS current value equal to IOUT/2. Select input capacitors with adequate ripple current rating to ensure reliable operation. The total output ripple is a combination of the ESR and the output capacitance value and can be calculated as follows: ( ∆VOUT = IPP (1 – D) COUTFS ) 2 The power dissipated in the input capacitor is: + (IPPRESR)2 2 PCIN = ICIN ( rms ) R ESR ( CIN ) where: This can become a significant part of power losses in a converter and hurt the overall energy transfer efficiency. D = duty cycle equal to VOUT/VIN COUT = output capacitance value The input voltage ripple primarily depends on the input capacitor ESR and capacitance. Ignoring the inductor ripple current, the input voltage ripple can be determined by: Recommended capacitors that can be used effectively in SP6123 applications are: low-ESR aluminum electrolytic capacitors, OS-CON capacitors that provide a very high performance/ size ratio for electrolytic capacitors and lowESR tantalum capacitors. AVX TPS series and Kemet T510 surface mount capacitors are popular tantalum capacitors that work well in SP6123 applications. POSCAP from Sanyo is a solid electrolytic chip capacitor that has low ESR and high capacitance. For the same ESR value, POSCAP has lower profile compared with tantalum capacitor. ∆ VIN = I out (max) RE SR (CIN ) + FS C INV IN 2 The capacitor type suitable for the output capacitors can also be used for the input capacitors. However, exercise extra caution when tantalum capacitors are considered. Tantalum capacitors are known for catastrophic failure when exposed to surge current, and input capacitors are prone to such surge current when power supplies are connected ‘live’ to low impedance Panasonic offers the SP series of specialty polymer aluminum electrolytic surface mount caDate: 9/13/04 I OUT ( MAX )VOUT (VI N − VOUT ) SP6123 Low Voltage, Synchronous Step Down PWM Controller 10 © Copyright 2004 Sipex Corporation APPLICATIONS INFORMATION 2 PCL(max) = RDS(ON)IOUT(max) (1 - D), power sources. Certain tantalum capacitors, such as AVX TPS series, are surge tested. For generic tantalum capacitors, use 2:1 voltage derating to protect the input capacitors from surge fallout. where: PCH(max) = conduction losses of the high side MOSFET MOSFET Selection PCL(max) = conduction losses of the low side MOSFET The losses associated with MOSFETs can be divided into conduction and switching losses. Conduction losses are related to the on resistance of MOSFETs, and increase with the load current. Switching losses occur on each on/off transition when the MOSFETs experience both high current and voltage. Since the bottom MOSFET switches current from/to a paralleled diode (either its own body diode or an external Schottky diode), the voltage across the MOSFET is no more than 1V during switching transition. As a result, its switching losses are negligible. The switching losses are difficult to quantify due to all the variables affecting turn on/off time. However, making the assumption that the turn on and turn off transition times are equal, the transition time can be approximated by: RDS(ON) = drain to source on resistance. The total power losses of the top MOSFET are the sum of switching and conduction losses. For synchronous buck converters of efficiency over 90%, allow no more than 4% power losses for high or low side MOSFETs. For input voltages of 3.3V and 5V, conduction losses often dominate switching losses. Therefore, lowering the RDS(ON) of the MOSFETs always improves efficiency even though it gives rise to higher switching losses due to increased CISS . Total gate charge is the charge required to turn the MOSFETs on and off under the specified operating conditions (VGS and VDS). The gate charge is provided by the SP6123 gate drive circuitry. (At 500kHz switching frequency, the gate charge is the dominant source of power dissipation in the SP6123). At low output levels, this power dissipation is noticeable as a reduction in efficiency. The average current required to drive the high side and low side MOSFETs is: tT = CISSVIN , IG where CISS is the MOSFET’s input capacitance, or the sum of the gate-to-source capacitance, CGS, and the drain-to-gate capacitance, CGD. This parameter can be directly obtained from the MOSFET’s data sheet. IG(av) = QGHFS + QGLFS, where QGH and QGL are the total charge for the high side and the low side MOSFETs respectively. IG is the gate drive current provided by the SP6123 (approximately 1A at VIN=5V) and VIN is the input supply voltage. Considering that the gate charge current comes from the input supply voltage VIN, the power dissipated in the SP6123 due to the gate drive is: Therefore an approximate expression for the switching losses associated with the high side MOSFET can be given as: PGATE DRIVE = VINIG(av) PSH(max) = (VIN(max) + VF)IOUT(max)tTFS , Top and bottom MOSFETs experience unequal conduction losses if their on time is unequal. For applications running at large or small duty cycle, it makes sense to use different top and bottom MOSFETs. Alternatively, parallel multiple MOSFETs to conduct large duty factor. where tT is the switching transition time and VF is the free wheeling diode drop. Switching losses need to be taken into account for high switching frequency, since they are directly proportional to switching frequency. The conduction losses associated with top and bottom MOSFETs are determined by RDS(ON) varies greatly with the gate driver voltage. The MOSFET vendors often specify RDS(ON) on multiple gate to source voltages (VGS), as well as provide typical curve of RDS(ON) versus 2 PCH(max) = RDS(ON)IOUT(max) D Date: 9/13/04 SP6123 Low Voltage, Synchronous Step Down PWM Controller 11 © Copyright 2004 Sipex Corporation APPLICATIONS INFORMATION forward voltage. The reverse voltage across the diode is equal to input voltage, and the diode must be able to handle the peak current equal to the maximum load current. VGS. For 5V input, use the RDS(ON) specified at 4.5V VGS. At the time of this publication, vendors, such as Fairchild, Siliconix and International Rectifier, have started to specify RDS(ON) at VGS less than 3V. This data is necessary for designs where the MOSFETs are driven with 3.3V. The power dissipation of the Schottky diode is determined by PDIODE = 2VFIOUTTNOLFS Thermal calculation must be conducted to ensure the MOSFET can handle the maximum load current. The junction temperature of the MOSFET, determined as follows, must stay below the maximum rating. TJ ( max) = T A (max) + PMOSFET (max) Rθ JA where TNOL = non-overlap time between GL and GH. VF = forward voltage of the Schottky diode. COMP , ® R1 C2 SP6123 C1 where TA(max) = maximum ambient temperature PMOSFET(max) = maximum power dissipation of the MOSFET Figure 1. The RC network connected to the COMP pin provides a pole and a zero to control loop. RθJA = junction to ambient thermal resistance. Loop Compensation Design RθJA of the device depends greatly on the board layout, as well as device package. Significant thermal improvement can be achieved in the maximum power dissipation through the proper design of copper mounting pads on the circuit board. For example, in a SO-8 package, placing two 0.04 square inches copper pad directly under the package, without occupying additional board space, can increase the maximum power dissipation from approximately 1 to 1.2W. For DPAK package, enlarging the tap mounting pad to 1 square inches reduces the RθJA from 96°C/W to 40°C/W. The goal of loop compensation is to manipulate loop frequency response such that its gain crosses over 0db at a slope of -20db/dec. The SP6123 has a transconductance error amplifier and requires the compensation network to be connected between the COMP pin and ground, as shown in Figure 1. The first step of compensation design is to pick the loop crossover frequency. High crossover frequency is desirable for fast transient response, but often jeopardize the system stability. Crossover frequency should be higher than the ESR zero but less than 1/5 of the switching frequency. The ESR zero is contributed by the ESR associated with the output capacitors and can be determined by Schottky Diode Selection When paralleled with the bottom MOSFET, an optional Schottky diode can improve efficiency and reduce noise. Without this Schottky diode, the body diode of the bottom MOSFET conducts the current during the non-overlap time when both MOSFETs are turned off. Unfortunately, the body diode has high forward voltage and reverse recovery problem. The reverse recovery of the body diode causes additional switching noises when the diode turns off. The Schottky diode alleviates this noise and additionally improves efficiency thanks to its low Date: 9/13/04 fZ(ESR) = 1 2πCOUTRESR Crossover frequency of 20kHz is a sound first try if low ESR tantalum capacitors or POSCAPs are used at the output. The next step is to calculate the complex conjugate poles contributed by the LC output filter, SP6123 Low Voltage, Synchronous Step Down PWM Controller 12 © Copyright 2004 Sipex Corporation APPLICATIONS INFORMATION fP(LC) = 1 erosion of phase margin. Therefore, the value of the C2 can be derived from 2π√ LCOUT The open loop gain of the whole system can be divided into the gain of the error amplifier, PWM modulator, buck converter, and feedback resistor divider. In order to crossover at the selected frequency fco, the gain of the error amplifier has to compensate for the attenuation caused by the rest of the loop at this frequency. In the RC network shown in Figure 1, the product of R1 and the error amplifier transconductance determines this gain. Therefore, R1 can be determined from the following equation that takes into account the typical error amplifier transconductance, reference voltage and PWM ramp built into the SP6123. C2 = 1 20πfCOR1 Figure 2 illustrates the overall loop frequency response and frequency of each pole and zero. To fine-tune the compensation, it is necessary to physically measure the frequency response using a network analyzer. Gain -20db/dec -40db/dec Loop R1 = 2083VOUT fCO fZ(ESR) VIN fP(LC)2 -20db/dec f In Figure 1, R1 and C1 provides a zero fZ1 which needs to be placed at or below fP(LC). If fZ1 is made equal to fP(LC) for convenience, the value of C1 can be calculated as C1 = -20db/dec -20db/dec Error Amplifier 1 2πfP(LC)R1 f fZ1 fP(LC) The optional C2 generates a pole fP1 with R1 to cut down high frequency noise for reliable operation. This pole should be placed one decade higher than the crossover frequency to avoid fZ(ESR) fCO fP1 Figure 2. Frequency response of a stable system and its error amplifier. 3V to 5.5V D1 MBR0530 R1 5.0 CIN 47µF Ceramic CBST 1µF BST 8 1 GL 2 V CC 3 CB 2.2µF 4 GND GH 7 SP6123A U1 COMP Q1 FDS6890A VFB RZ CZ 20k 680pF 1.6V/4A 1µH 5 D2 Q1 FDS6890A CP 47pF L1 SWN 6 STPS2L25U R2 80k C1 330pF COUT 4x47µF Ceramic R3 80k Figure 3. SP6123 Buck converter design with ceramic output capacitors. Date: 9/13/04 SP6123 Low Voltage, Synchronous Step Down PWM Controller 13 © Copyright 2004 Sipex Corporation APPLICATIONS INFORMATION Most electrolytic and tantalum capacitors come with adequate ESR value to generate a zero below power supplies’ crossover frequency. This is crucial to a stable close loop system. However, this same system can become unstable if ceramic output capacitors are used. The low ESR associated with ceramic capacitors can push the ESR zero above the crossover frequency and often higher than 1MHz. In this case, type III compensation is required to provide additional low frequency zero for adequate phase margin and thus stable operation. In SP6123, GM (error amplifier transconductance) and ROUT (error amplifier output impedance) are specified at 0.6ms and 3MΩ, respectively. For frequencies above the second zero fZ2, the feedback gain rises at 20dB/dec and is equal to AFB = 2πfRZC1 However, the error amplifier gain AEA declines at -20dB/dec due to CP. AEA = The design of type III compensation using SP6123 transconductance error amplifier is quite straightforward. First, the resonant frequency of the LC output filter could be derived from 1 fr = = 11.6kHz 2π√ L1COUT GM 2πfCP When AFB is less than AEA, the compensated error amplifier gain is dominated by AFB. As a result, it shows up as a positive 20dB/dec slope. However, when the rising AFB crosses the falling AEA at one particular frequency, the compensated error amplifier gain is now solely determined by AEA. Therefore, the 20dB/dec slope is converted to a -20dB/dec slope, and the bode plot demonstrates a double pole at this frequency which is equal to The values and references used in all the calculations agree with the schematic shown in Figure 3. Select values of R2, C1, RZ and CZ to place two zeros below or equal to the LC resonant frequency. Those two zeros are located at: 1 fZ1 = = 6kHz 2 π R2 C 1 1 fZ2 = = 11.7kHz 2 π RZ C Z There is low frequency pole determined by both the error amplifier gain and feedback gain. It occurs at 1 fP1 = = 3.25Hz 2π(R2 // R3)CZGMROUT 1 fP2 = 2π GM CPC1RZ = 221kHz Select CP such that fP2 is located at least a decade higher than the crossover frequency. As shown in Figure 4, this type III compensation generates a close loop system with 50 degree phase margin and crossover frequency at 20kHz. This ensures a stable regulated power supply with tight DC regulation and fast transient response. 200 Phase 100 0 Gain -100 -200 10Hz 100Hz 100Hz 1.0kHz 10kHz 1.0MHz 10MHz Frequency Figure 4. Bode Plot for schematic shown in Figure 3. VIN = 3.3V and VOUT = 1.6V, no load. Date: 9/13/04 SP6123 Low Voltage, Synchronous Step Down PWM Controller 14 © Copyright 2004 Sipex Corporation APPLICATIONS INFORMATION Overcurrent Protection Output Voltage Program Over current protection on the SP6123 is implemented through detection of an excess voltage condition across the high side switch during conduction. This is typically referred to as high side RDS(ON) detection. By using the RDS(ON) of Q1 to measure the output current, the current limit circuit eliminates the sense resistor that would otherwise be required and the corresponding loss associated with it. This improves the overall efficiency and reduces the number of components in the power path benefiting size and cost. RDS(ON) sensing is by default inaccurate and is primarily meant to protect the power supply during a fault condition. The overcurrent trip point will vary from unit to unit as the RDS(ON) of MOSFET varies. The SP6123 provides a built-in 200mV threshold between the VCC and SWN pins. As shown in Figure 5, the voltage divider connecting to the VFB pin programs the output voltage according to R VOUT = 0.8(1 + 1 ) R2 where 0.8V is the internal reference voltage. Select R2 in the range of 10k to 100k, and R1 can be calculated using R1 = R2(VOUT – 0.8) 0.8 VOUT The overcurrent threshold can be calculated as IMAX = 200mV RDS(ON) SP6123 VFB R2 To ensure accurate current sensing, the VCC pin should be connected directly to the drain of the high side MOSFET. A RC filter on the VCC pin is not recommended because it would artificially alter the current signal and reduce the overcurrent threshold from the value given by the equation. Date: 9/13/04 R1 ® Figure 5. A voltage divider connected to the VFB pin programs the output voltage. SP6123 Low Voltage, Synchronous Step Down PWM Controller 15 © Copyright 2004 Sipex Corporation LAYOUT GUIDELINE PCB layout plays a critical role in proper function of the converters and EMI control. In switch mode power supplies, loops carrying high di/dt give rise to EMI and ground bounces. The goal of layout optimization is to identify these loops and minimize them. It is also crucial on how to connect the controller ground such that its operation is not affected by noise. The following guideline should be followed to ensure proper operation. 4. The VCC bypass capacitor should be right next to the VCC and GND pins. 5. The trace connecting the feedback resistors to the output should be short, direct and far away from the switch node, and switching components. 6. Minimize the trace between GH/GL and the gates of the MOSFETs to reduce the impedance driving the MOSFETs. This is especially important for the bottom MOSFET that tends to turn on through its Miller capacitor when the switch node swings high. 1. A ground plane is recommended for minimizing noises, copper losses and maximizing heat dissipation. 7. Minimize the loop composed of input capacitors, top/bottom MOSFETs and Schottky diode. This loop carries high di/dt current. Also increase the trace width to reduce copper losses. 2. Begin the layout by placing the power components first. Orient the power circuitry to achieve a clean power flow path. If possible make all the connections on one side of the PCB with wide, copper filled areas. 8. Maximize the trace width of the loop connecting the inductor, output capacitors, Schottky diode and bottom MOSFET. 3. Connect the ground of feedback divider and compensation components directly to the GND pin of the IC using a dedicated ground trace. Then connect this pin as close as possible to the ground of the output capacitor. Date: 9/13/04 SP6123 Low Voltage, Synchronous Step Down PWM Controller 16 © Copyright 2004 Sipex Corporation PACKAGE: 8 PIN NSOIC D e E/2 E1 E SEE VIEW C E1/2 1 b INDEX AREA (D/2 X E1/2) Ø1 TOP VIEW Gauge Plane L2 Seating Plane Ø1 Ø L L1 VIEW C A2 A SEATING PLANE A1 SIDE VIEW 8 Pin NSOIC (JEDEC MS-012, AA - VARIATION) b WITH PLATING DIMENSIONS Minimum/Maximum (mm) COMMON HEIGHT DIMENSION SYMBOL A A1 A2 b c D E E1 e L L1 L2 Ø Ø1 Date: 9/13/04 MIN NOM MAX 1.75 1.35 0.25 0.10 1.25 1.65 0.31 0.51 0.17 0.25 4.90 BSC 6.00 BSC 3.90 BSC 1.27 BSC 0.40 1.27 1.04 REF 0.25 BSC 0º 8º 5º 15º c BASE METAL CONTACT AREA PACKAGE: 8 PIN NSOIC (Narrow refers to symbol E1) SP6123 Low Voltage, Synchronous Step Down PWM Controller 17 © Copyright 2004 Sipex Corporation ORDERING INFORMATION Part Number Operating Temperature Range Package Type 500kHz SP6123ACN ............................................. 0˚C to +70˚C ........................................... 8-Pin NSOIC SP6123ACN/TR ....................................... 0˚C to +70˚C ........................................... 8-Pin NSOIC 300kHz SP6123CN ............................................... 0˚C to +70˚C ........................................... 8-Pin NSOIC SP6123CN/TR ......................................... 0˚C to +70˚C .......................................... 8-Pin NSOIC Available in lead free packaging. To order add "-L" suffix to part number. Example: SP6123CN/TR = standard; SP6123CN-L/TR = lead free /TR = Tape and Reel Pack quantity is 2500 for NSOIC. Corporation ANALOG EXCELLENCE Sipex Corporation Headquarters and Sales Office 233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600 Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Date: 9/13/04 SP6123 Low Voltage, Synchronous Step Down PWM Controller 18 © Copyright 2004 Sipex Corporation