SP6136
VCC
UV
VI N
BST
16
15
14
13
12 GH
1
SP6136
2
16 Pin QFN
3mm x 3mm
3
6
7
PWRGD
11
SWN
10
ISP
9
ISN
8
SS
5
EN
4
COM P
FEATURES
■ 5V to 24V Input step down converter
■ Up to 7A output in a small form factor
■ Highly integrated design, minimal components
GL
■ UVLO Detects Both VCC and VIN
PGND
■ Overcurrent circuit protection with auto-restart
■ Power Good Output, ENABLE Input
■ Maximum Controllable Duty Cycle Ratio up to 92% GND
■ Wide BW amp allows Type II or III compensation VFB
■ Programmable Soft Start
■ Fast Transient Response
■ Available in Lead Free, RoHS Compliant
16-Pin QFN package
■ External Driver Enable/Disable
■ U.S. Patent #6,922,041
IN
Synchronous Buck Controller
DESCRIPTION
The SP6136 is a synchronous step-down switching regulator controller optimized for high
efficiency. The part is designed to be especially attractive for single supply step down conversion from 5V to 24V. The SP6136 is designed to drive a pair of external NFETs using
a fixed 600 KHz frequency, PWM voltage mode architecture. Protection features include
UVLO, thermal shutdown, output short circuit protection, and overcurrent protection with
auto restart. The device also features a PWRGD output and an enable input. The SP6136
is available in a space saving 16-pin QFN and offers excellent thermal performance.
TYPICAL APPLICATION CIRCUIT
VIN
C3
0.1uF
CIN
22uF
DBST
CVCC
4.7uF
CBST
0.1uF
SD101AWS
GND
GH
VCC
R5
MT, Si4354DY
18.5 mΩ, 30V
BST
VIN
12V
Inter-Technical SC7232-2R2
2.2uH, 13A, 10.4mΩ
10kΩ
VOUT
PWRGD
SWN
POWERGOOD
MB, Si4886DY
13.5 mΩ, 30V
UVIN
NC
EN
ENABLE
SP6136
RS1
5.11KΩ
COUT
100uF
RS2
5.11KΩ
GL
GND
3.3V
0-7A
RS3
10KΩ
ISP
GND
PGND
CSP
6.8nF
ISN
CSS
47nF
VFB
CZ3
270pF
CF1
22pF
CS
0.1uF
SS
COMP
CP1
12 pF
R1
68.1kΩ, 1%
RZ3
1kΩ
R2
21.5kΩ, 1%
CZ2
560pF
RZ2
30.9kΩ
Note: Die attach paddle is internally connected to GND.
Oct 31-06 Rev L
SP6136 Synchronous Buck Controller
© 2006 Sipex Corporation
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation of the device at
these ratings or any other above those indicated in the operation sections
of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
Peak Output Current < 10µs
GH,GL.............................................................................................. 2A
VCC .................................................................................................. 6V
VIN .............................................................................................. 24.5V
BST................................................................................................. 30V
BST-SWN......................................................................................... 7V
SWN.....................................................................................-2V to 24V
GH...........................................................................-0.3V to BST+0.3V
GH-SWN........................................................................................... 6V
Storage Temperature.................................................... -65°C to 150°C
Power Dissipation............................................................................ 1W
ESD Rating............................................................................ 2kV HBM
Thermal Resistance.............................................................. 41.9°C/W
All other pins.............................................................-0.3V to VCC+0.3V
ELECTRICAL SPECIFICATIONS
Unless otherwise specified: -40°C < TAMB < 85°C, 4.5V < VCC < 5.5V, BST=VCC, SWN = GND = PGND = 0.0V, UVIN = 3.0V, CVCC
= 10µF, CCOMP = 0.1µF, CGH = CGL = 3.3nF, CSS = 50nF, RPWRGD = 10KΩ.
PARAMETER
MIN
TYP
MAX UNITS CONDITIONS
QUIESCENT CURRENT
VIN Supply Current
1.5
3.0
mA
VFB = 1V (no switching)
VCC Supply Current
1.5
3.0
mA
VFB = 1V (no switching)
BST Supply Current
0.2
0.4
mA
VFB = 1V (no switching)
PROTECTION: UVLO
VCC UVLO Start
Threshold
4.00
4.25
4.5
V
VCC UVLO Hysteresis
150
200
250
mV
UVIN Start Threshold
2.35
2.50
2.65
V
Apply voltage to UVIN pin
UVIN Hysteresis
200
300
400
mV
Apply voltage to UVIN pin
VIN Start Threshold
9.0
9.5
10.0
V
UVIN Floating
VIN Hysteresis
300
mV
UVIN Floating
Enable Pullup Current
0.4
µA
Apply voltage to EN pin
2X Gain Config.
ERROR AMPLIFIER REFERENCE
Error Amplifier Reference 0.792
0.800
0.808
V
Error Amplifier Reference
Over Line and Tempera- 0.788
ture
0.800
0.812
V
COMP Sink Current
70
150
230
µA
COMP Source Current
-230
-150
-70
µA
VFB Input Bias Current
1
50
100
nA
COMP Common Mode
Output Range
1.9
3.0
3.2
V
COMP Pin Clamp
Voltage
3.2
3.5
3.8
V
Oct 31-06 Rev L
SP6136 Synchronous Buck Controller
VFB = 0.7V
© 2006 Sipex Corporation
ELECTRICAL SPECIFICATIONS
Unless otherwise specified: -40°C < TAMB < +85°C, 4.5V < VCC < 5.5V, BST=VCC,SWN = GND = PGND = 0.0V, UVIN = 3.0V,
CVCC = 0.1µF, CCOMP = 0.1µF, CGH = CGL = 3.3nF, CSS = 50nF.
PARAMETER
MIN
TYP
MAX UNITS
CONDITIONS
CONTROL LOOP: PWM COMPARATOR, RAMP & LOOP DELAY PATH
Ramp Offset
Ramp Amplitude
1.7
2.0
2.3
V
0.80
1.0
1.20
V
50
100
ns
GH Minimum Pulse Width
TA = 25˚C
Maximum Controllable Duty
Ratio
92
%
Maximum Duty Ratio
100
%
Internal Oscillator Frequency
520
600
680
kHz
SS Charge Current:
-16
-10
-4
µA
SS Discharge Current:
1.0
2.0
3.0
mA
VCC Output Voltage
4.6
5.0
5.4
V
Dropout Voltage
250
500
750
mV
-10
-7.5
-5
%
2.0
4.0
%
10
mA
VFB = 0.7V,
VPWRGD = 0.2V
Measured VREF
(0.8V) - VFB
Guaranteed by
design
TIMERS: SOFTSTART
Fault Present
VCC Linear Regulator
VIN = 6 to 23V,
ILOAD = 0mA to 30mA
IVCC = 30mA
Power Good Output
Power Good Threshold
Power Good Hysteresis
Power Good Sink Current
1.0
PROTECTION: Short Circuit & Thermal
Short Circuit Threshold
Voltage
0.2
0.25
0.3
V
Overcurrent Threshold
Voltage
54
60
66
mV
ISP, ISN Common Mode
Range
0
3.3
V
Hiccup Timeout
90
110
130
ms
Thermal Shutdown
Temperature
135
145
155
˚C
10
3.3
˚C
Thermal Hysteresis
Oct 31-06 Rev L
SP6136 Synchronous Buck Controller
Measured ISP - ISN
© 2006 Sipex Corporation
ELECTRICAL SPECIFICATIONS
Unless otherwise specified: -40°C < TAMB < +85°C, 4.5V < VCC < 5.5V, BST=VCC,SWN = PGND = GND = 0.0V, UVIN = 3.0V, CVCC
= 0.1µF, CCOMP = 0.1µF, CGH = CGL = 3.3nF, CSS = 50nF.
PARAMETER
MIN TYP MAX UNITS
CONDITIONS
OUTPUT: NFET GATE DRIVERS
GH & GL Rise Times
35
50
ns
Measured 10% to 90%
GH & GL Fall Times
30
40
ns
Measured 90% to 10%
GL to GH Non Overlap Time
45
70
ns
GH & GL Measured at
2.0V
SWN to GL Non Overlap
Time
25
40
ns
Measured SWN =
100mV to GL = 2.0V
50
85
KΩ
Driver Pull Down Resistance
1.5
1.9
Ω
Driver Pull Up Resistance
2.5
3.9
Ω
GH & GL Pull Down
Resistance
15
Block Diagram
VCC
5
NON SYNCH. STARTUP
COMPARATOR
COMP
SS
GL HOLD OFF
1.6 V
VFBINT
VFB
4
VCC
Gm ERROR AMPLIFIER
VCC
10 uA
VPOS
SOFTSTART INPUT
SS
13 BST
PW M LO O P
0.1V
R
Q
POS REF
8
RESET
DOMINANT
FAULT
Gm
FAULT
12 GH
QPWM
S
FAULT
11 SWN
SYNCHRO NO US
DRIVER
1
GL
2
PGND
600 kHZ
RAMP = 1V
CLK
CLOCK PULSE GENERATOR
2.8 V
VCC
REFERENCE
CORE
16
1.3 V
0.8V
VCC
REF OK
1 uA
EN
ENABLE
COMPARATOR
6
1.7V ON
1.0V OFF
POWER FAULT
4.25 V ON
4.05 V OFF
FAULT
VCC UVLO
THERMAL
SHUTDOWN
LINEAR
REGULATOR
14
HICCUP FAULT
UVLO CO MPARATORS
Oct 31-06 Rev L
10
9
ISP
ISN
COUNTER
CLR
REF OK
60 mV
VIN UVLO
50KΩ
GND
CLK
100ms Delay
OVER CURRENT
DETECTION
15
2.50 V ON
2.20 V OFF
3
R
SHORT CIRCUIT
DETECTION
VFBINT
140KΩ
UVIN
S
Q
0.25V
VPOS
VIN
SET
DOMINANT
145ºC ON
135ºC OFF
5V
7
PWRGD
Power Good
VFB
0.74 V ON
0.72 V OFF
THERMAL AND O VER CURRENT PROTECTIO N
SP6136 Synchronous Buck Controller
© 2006 Sipex Corporation
PIN DESCRIPTION
PIN
PIN
#
NAME
DESCRIPTION
1
GL
High current driver output for the low side NFET switch. It is always low if GH is high or
during a fault. Resistor pull down ensures low state at low voltage.
2
PGND
Ground Pin. The power circuitry is referenced to this pin. Return separately from other
ground traces to the (-) terminal of Cout.
3
GND
Ground pin. The control circuitry of the IC is referenced to this pin.
4
VFB
Feedback Voltage and Short Circuit Detection pin. It is the inverting input of the Error
Amplifier and serves as the output voltage feedback point for the Buck Converter. The
output voltage is sensed and can be adjusted through an external resistor divider.
Whenever VFB drops 0.25V below the positive reference, a short circuit fault is detected
and the IC enters hiccup mode.
5
COMP
6
EN
7
PWRGD
8
SS
9
ISN
Negative Input for the Sense Comparator. There should be a 60mV offset between PSENSE
and NSENSE. Offset accuracy +10%.
10
ISP
Positive Input for the Inductor Current Sense.
11
SWN
Lower supply rail for the GH high-side gate driver. Connect this pin to the switching node at
the junction between the two external power MOSFET transistors.
12
GH
High current driver output for the high side NFET switch. It is always low if GL is high or during a fault.
13
BST
High side driver supply pin. Connect BST to the external boost diode and capacitor as shown
in the Application Schematic of page 1. High side driver is connected between BST pin and SWN pin.
14
VIN
Supply Input -- supplies power to the internal LDO.
15
UVIN
Under Voltage lock-out for VIN voltage. Internally has a resistor divider from VIN to ground.
Can be overridden with external resistors.
16
VCC
Output of the Internal LDO. If VIN is less than 5V then Vcc should be powered from an
external 5V supply.
Output of the Error Amplifier. It is internally connected to the non-inverting input of the PWM
comparator. An optimal filter combination is chosen and connected to this pin and either
ground or VFB to stabilize the voltage mode loop.
Enable Pin. Pulling this pin below 0.4V will place the IC into sleep mode. This pin is
internally pulled to VCC with a 1µA current source.
Power Good Output. This open drain output is pulled low when VOUT is outside of the
regulation. Connect an external resistor to pull high.
Soft Start/Fault Flag. Connect an external capacitor between SS and GND to set the soft
start rate based on the 10µA source current. The SS pin is held low via a 1mA (min) current
during all fault conditions.
Note: Die attach paddle is internally connected to GND.
THEORY OF OPERATION
General Overview
tion schemes. A precision 0.8V reference
present on the positive terminal of the error
amplifier permits the programming of the
output voltage down to 0.8V via the VFB pin.
The output of the error amplifier, COMP,
compared to a 1V peak-to-peak ramp is
responsible for trailing edge PWM control.
This voltage ramp and PWM control logic
are governed by the internal oscillator that
accurately sets the PWM frequency to 600kHz.
The SP6136 is a fixed frequency, voltage
mode, synchronous PWM controller optimized for high efficiency. The part has been
designed to be especially attractive for single
supply input voltages ranging between 5V
and 24V.
The heart of the SP6136 is a wide bandwidth
transconductance amplifier designed to accommodate Type II and Type III compensaOct 31-06 Rev L
SP6136 Synchronous Buck Controller
© 2006 Sipex Corporation
THEORY OF OPERATION
The SP6136 contains two unique control
features that are very powerful in distributed
applications. First, non-synchronous driver
control is enabled during start up to prohibit
the low side NFET from pulling down the output until the high side NFET has attempted to
turn on. Second, a 100% duty cycle timeout
ensures that the low side NFET is periodically
enhanced during extended periods at 100%
duty cycle. This guarantees the synchronized
refreshing of the BST capacitor during very
large duty ratios.
and the 0.8V reference voltage. Therefore,
the excess current source can be redefined
as:
10µA
IVIN, X = Cout • ΔVout •
(Css X 0.8V)
Hiccup
Upon the detection of a power, thermal, or
short-circuit fault, the SP6136 is forced into
an idle state for a minimum of 200ms. The
SS and COMP pins are immediately pulled
low, and the gate drivers are held off for the
duration of the timeout period. Power and
thermal faults have to be removed before a
restart may be attempted, whereas, a shortcircuit fault is internally cleared shortly after
the fault latch is set. Therefore, a restart attempt is guaranteed every 200ms (typical) as
long as the short-circuit condition persists.
The SP6136 also contains a number of valuable protection features. A programmable
input UVLO allows a user to set the exact
value at which the conversion voltage is
at a safe point to begin down conversion,
and an internal VCC UVLO ensures that
the controller itself has enough voltage to
properly operate. Other protection features
include thermal shutdown and short-circuit
detection. In the event that either a thermal,
short-circuit, or UVLO fault is detected, the
SP6136 is forced into an idle state where the
output drivers are held off for a finite period
before a re-start is attempted.
A short-circuit detection comparator has
also been included in the SP6136 to protect
against the accidental short or severe build
up of current at the output of the power converter. This comparator constantly monitors
the inputs to the error amplifier, and if the
VFB pin ever falls more than 250mV (typical)
below the voltage reference, a short-circuit
fault is set. Because the SS pin overrides the
internal 0.8V reference during soft start, the
SP6136 is capable of detecting short-circuit
faults throughout the duration of soft start as
well as in regular operation.
Soft Start
“Soft Start” is achieved when a power converter ramps up the output voltage while
controlling the magnitude of the input supply source current. In a modern step down
converter, ramping up the non-inverting input
of the error amplifier controls soft start. As a
result, excess source current can be defined
as the current required to charge the output
capacitor
IVIN, X
=
Error Amplifier & Voltage Loop
As stated before, the heart of the SP6136
voltage error loop is a high performance,
wide bandwidth transconductance amplifier. Because of the amplifier’s current
limited (+100µA) transconductance, there
are many ways to compensate the voltage
loop or to control the COMP pin externally.
If a simple, single pole, single zero response
is required, then compensation can be as
simple as an RC circuit to ground. If a more
complex compensation is required, then the
amplifier has enough bandwidth (45° at 4
Cout • ΔVout
∆TSoft-start
The SP6136 provides the user with the option to program the soft start rate by tying
a capacitor from the SS pin to GND. The
selection of this capacitor is based on the
10µA pull up current present at the SS pin
Oct 31-06 Rev L
SP6136 Synchronous Buck Controller
© 2006 Sipex Corporation
THEORY OF OPERATION
MHz) and enough gain (60 dB) to run Type III
compensation schemes with adequate gain
and phase margins at crossover frequencies
greater than 200 kHz.
included to prevent the IC from malfunctioning at extreme temperatures.
The common mode output of the error amplifier (COMP) is 0.9V to 2.2V. Therefore, the
PWM voltage ramp has been set between
1.0V and 2.0V to ensure proper 0% to 100%
duty cycle capability. The voltage loop also
includes two other very important features.
One is a non-synchronous start up mode.
Basically, the GL driver cannot turn on unless
the GH driver has attempted to turn on or
the SS pin has exceeded 1.7V. This feature
prevents the controller from “dragging down”
the output voltage during startup or in fault
modes. The second feature is a 100% duty
cycle timeout that ensures synchronized
refreshing of the BST capacitor at very high
duty ratios. In the event that the GH driver is
on for 20 continuous clock cycles, a reset is
given to the PWM flip flop half way through
the 20th cycle. This forces GL to rise for the
remainder of the cycle, in turn refreshing the
BST capacitor.
Over-current is detected by monitoring a
differential voltage across the output inductor as shown in figure 1. Inputs to an
over-current detection comparator, set to
trigger at 60 mV nominal, are connected to
the inductor as shown.
Since the average voltage sensed by the
comparator is equal to the product of inductor current and inductor DC resistance
(DCR) then Imax = 60mV / DCR. Solving
this equation for the specific inductor in circuit 1, Imax = 14.6A. When Imax is reached,
a 220 ms time-out is initiated, during which
top and bottom drivers are turned off. Following the time-out, a restart is attempted.
If the fault condition persists, then the timeout is repeated (referred to as hiccup).
Over-Current Protection
SP613X
L = 2.7uH, DCR = 4.mOhm
SWN
Gate Drivers
RS
5.11K
The SP6136 contains a pair of powerful 2W
Pull-up and 1.5W Pull-down drivers. These
state-of-the-art drivers are designed to drive
an external NFET capable of handling up to
30A. Rise, fall, and non-overlap times have
all been minimized to achieve maximum
efficiency. All drive pins GH, GL, & SWN
are monitored continuously to ensure that
only one external NFET is ever on at any
given time.
Vout
RS2
5.K
ISP
ISN
CSP
6.8nF
CS
0.uF
Figure 1: Over-current detection circuit
Thermal & Short-Circuit Protection
Because the SP6136 is designed to drive
large NFETs running at high current, there is
a chance that either the controller or power
converter will become too hot. Therefore, an
internal thermal shutdown (145°C) has been
Oct 31-06 Rev L
SP6136 Synchronous Buck Controller
© 2006 Sipex Corporation
APPLICATION INFORMATION
Increasing the Current Limit
RS3 =
If it is desired to set Imax > {60mV / DCR} (in
this case larger than 14.6A), then a resistor
RS3 should be added as shown in figure 2.
RS3 forms a resistor divider and reduces the
voltage seen by the comparator.
RS2 • [VOUT - 60mV + (IMAX•DCR)].........(2)
60mV - (IMAX • DCR)
As an example: for Imax of 12A and Vout of 3.3V,
calculated RS3 is 1.5MΩ (232KΩ standard).
Since: 60mV
(Imax • DCR)
=
RS3
{RS1 + RS2 + RS3}
SP613X
L = 2.7uH, DCR = 4.mOhm
Solving for RS3 we get:
SWN
[60mV • (RS1 + RS2)]
[(Imax • DCR) – 60mV]
RS3 =
.......(1)
RS
5.11K
Vout
RS2
5.K
ISP
As an example: if desired Imax is 17A, then
RS3 = 63.4KΩ.
ISN
CSP
6.8nF
CS
0.uF
RS3
.5MOhm
SP613X
L = 2.7uH, DCR = 4.mOhm
Vout
SWN
RS
5.K
RS2
5.K
Figure 3- Over-current detection circuit
for Imax < {60mV / DCR}
RS3
63.4K
ISP
ISN
CSP
6.8nF
CS
0.uF
Power MOSFET Selection
There are four main criterion in selecting
Power MOSFETs for buck conversion:
Voltage rating BVdss
On resistance Rds(on)
Gate-to-drain charge Qgd
Package type
Figure 2- Over-current detection circuit
for Imax > 60mV / DCR
●
Decreasing the Current Limit
●
●
If it is required to set Imax < {60mV / DCR}, a
resistor is added as shown in figure 3. RS3
increases the net voltage detected by the
current-sense comparator. Voltage at the
positive and negative terminal of comparator is given by:
●
In order to better illustrate the MOSFET selection process, the following buck converter
design example will be used: Vin = 12V, Vout
= 3.3V, Iout = 10A, f = 2000KHz, DCR =
4.5mΩ (inductor DC resistance), efficiency
= 94% and Ta = 40˚C.
VSP = Vout + (Imax • DCR)
VSN = Vout • {RS3 / (RS2 + RS3)}
Select the voltage rating based on maximum
input voltage of the converter. A commonly
used practice is to specify BVdss at least
twice the maximum converter input voltage.
This is done to safeguard against switching
transients that may break down the MOSFET.
For converters with Vin of less than 10V, a
Since the comparator is triggered at 60mV:
VSP-VSN = 60 mV
Combining the above equations and solving for RS3:
Oct 31-06 Rev L
SP6136 Synchronous Buck Controller
© 2006 Sipex Corporation
APPLICATION INFORMATION
20V rated MOSFET is sufficient. For converters with 10-15Vin, as in the above example,
select a 30V MOSFET.
The calculation of Rds(on) for Top and Bottom
MOSFETs is interrelated and can be done
using the following procedure:
Rds(on) =
[I out • (Vout/Vin) • 1.5]
= 10.7W.
Gate-to-drain charge Qgd for the top MOSFET needs to be specified. A simplified
expression for switching losses is:
1)
Calculate the maximum permissible
power dissipation P(dissipation) based on
required efficiency. The converter in the
above example should deliver an output
power Pout = 3.3V•10A = 33W. For a target
efficiency of 94%, input power Pin is given
by Pin = Pout/0.94 = 35.1W. Maximum allowable power dissipation is then:
{
Ps = Iout • Vin • f • Vin + Iout
dv/dt
di/dt
}
...................(3)
where dv/dt and di/dt are the rates at which
voltage and current transition across the top
MOSFET respectively, and f is the switching
frequency. Voltage switching time (Vin /dv/dt)
is related to Qgd:
P(dissipation) = Pin – Pout = 2.1 W
2) Calculate the total power dissipation in
top and bottom MOSFETs P(MOSFET) by subtracting inductor losses from P(dissipation)
calculated in step 1. To simplify, disregard
core losses; then PL = I2rms • DCR • 1.4,
where 1.4 accounts for the increase in DCR
at operating temperature. For the above
example PL = 0.63W. Then:
P(MOSFET) = 2.1W – 0.63W = 1.47W.
(Vin /dv/dt) = Qgd/ig............................... (4)
where ig is Current charging the gate-to-drain
capacitance. It can be calculated from:
ig = (Vdrive-Vgate)/Rdrive......................(5)
where Vdrive is the drive voltage of the
SP6136 top driver minus the drop across the
boost diode (approximately 4.5V); Vgate is
the top MOSFET’s gate voltage corresponding to Iout (assume 2.5V) and Rdrive is the
internal resistance of the SP6136 top driver
(assume 2Ω average for turn-on and turn-off).
Substituting these values in equation (5) we
get ig = 1A. Substituting for ig in equation
3) Calculate Rds(on) of the bottom MOSFET
by allocating 40% of calculated losses to it.
40% dissipation allocation reflects the fact
that the the top MOSFET has essentially no
switching loss. Then P(bottom) = 0.4X1.47W
= 0.59W. Rds(on) = P/(I2rms • 1.5) where Irms
= Iout • {1-(Vout/Vin)}0.5 and 1.5 accounts
for the increase in Rds(on) at the operating
temperature. Then:
P
Rds(on) =
2
[{I out • (1-Vout/Vin)} • 1.5]
(4), we get (Vin /dv/dt) = Qgd. Substituting
for (Vin /dv/dt) in equation (3) we have:
Ps = Iout • Vin • f • {Qgd + (Iout / di/dt)}
= 5.4 Ω.
Solving for Qgd we get:
4) Allocate 60% of the calculated losses
to the top MOSFET, P(top) = 0.6X1.47 =
0.88W. Assume conduction losses equal
to switching losses, then P = 0.5X0.88W =
0.44W. Since it operates at the duty cycle
of D=Vin/Vout; then:
Oct 31-06 Rev L
P
2
Qgd =
{I
Ps
out • Vin • f
}
_ Iout .............. (6)
di/dt
Di/dt is usually limited by parasitic DC-Loop
Inductance (Lp) according to di/dt = Vin/Lp.
SP6136 Synchronous Buck Controller
© 2006 Sipex Corporation
APPLICATION INFORMATION
side regulation. The PWRGD pin can be
connected to VCC with an external 10KΩ
resistor. During startup, output regulates
when Soft Start (SS) reaches 0.8V (the reference voltage). PWRGD is enabled when SS
reaches 1.6V. PWRGD output can be used
as a “Power on Reset”. The simplest way to
adjust delay of the “Power on Reset” signal
with respect to Vout in regulation is with the
Soft Start Capacitor (CSS) and is given by:
CSS = (Iss • Tdelay)/0.8 where Iss is the Soft
Start charge current (10µA nominal).
Lp is due to wiring and PCB traces connecting
input capacitors and switching MOSFETs.
For typical Lp of 12nH and Vin of 12V, di/dt
is 1A/ns. Substituting for di/dt in equation
(6) we get Qgd = 2 nC.
In selecting a package type, the main considerations are cost, power/current handling
capability and space constraints. A larger
package in general offers higher power and
current handling at increased cost. Package
selection can be narrowed down by calculating the required junction-to-ambient thermal
resistance θja:
θja = {Tj(max) - Ta(max))} /
Under Voltage Lock Out (UVLO)
The SP6136 has two separate UVLO comparators to monitor the bias (Vcc) and Input
(Vin) voltages independently. The Vcc UVLO
is internally set to 4.25V. The Vin UVLO is
programmable through UVIN pin. When
UVIN pin is greater than 2.5V the SP6136
is permitted to start up pending the removal
of all other faults. A pair of internal resistors
is connected to UVIN as shown in figure 4.
Therefore without external biasing the Vin
start threshold is 9.5V. A small capacitor may
be required between UVIN and GND to filter
out noise. For applications with Vin of 5V or
3.3V, connect UVIN directly to Vin.
........... (7)
P(max)
Where: Tj(max) is the die maximum temperature rating, Ta(max) is maximum ambient
temperature, and P(max) is maximum power
dissipated in the die.
It is common practice to add a guard-band
of 25˚C to the junction temperature rating.
Following this convention, a 150˚C rated
MOSFET will be designed to operate at 125˚C
(i.e., Tj(max) = 125˚C). P(max) = 0.88W (from
section 4) and Ta(max) = 40˚C as specified in
the design example. Substituting in equation
(7) we get θja = 96.6 ˚C/W.
SP613X
VIN
For the top MOSFET, we now have determined the following requirements; BVdss =
30V, Rds(on) = 10.7mΩ, Qgd = 2 nC and θja
< 96.6˚C/W. An SO-8 MOSFET that meets the
requirements is Vishay-Siliconix’s Si4394DY;
BVdss = 30V, Rds(on) = 9.75mΩ @ Vgs = 4.5V,
Qgd = 2.1nC and θja = 90 ˚C/W.
R4
40K
UVIN
+
2.5V ON
2.2V OFF
R5
50K
GND
The bottom MOSFET has the requirements of
BVdss = 30V and Rds(on) = 5.4mΩ. VishaySiliconix’s Si4320DY meets the requirements;
BVdss = 30V, Rds(on) = 4mΩ @ Vgs = 4.5V.
Figure 4- Internal and external bias of UVIN
To program the Vin start threshold, use a
pair of external resistors as shown. If external
resistors are an order of magnitude smaller
Power Good
Power Good (PWRGD) is an open drain
output that is pulled low when Vout is outOct 31-06 Rev L
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APPLICATION INFORMATION
than internal resistors, then the Vin start
threshold is given by:
Once the required inductor value is selected,
the proper selection of core material is based
on peak inductor current and efficiency requirements. The core must be large enough
not to saturate at the peak inductor current
ipeak = iout(max) + Ipp/2
Vin(start) = 2.5 • (R4+R5)/R5................ (8)
For example, if it is required to have a Vin
start threshold of 7V, then let R5 = 5KΩ and
using equation (9) we get R4 = 9.09KW.
and provide low core loss at the high switching frequency. Low cost powdered iron cores
have a gradual saturation characteristic
but can introduce considerable ac core
loss, especially when the inductor value is
relatively low and the ripple current is high.
Ferrite materials, on the other hand, are more
expensive and have an abrupt saturation
characteristic with the inductance dropping
sharply when the peak design current is
exceeded. Nevertheless, they are preferred
at high switching frequencies because they
present very low core loss and the design
only needs to prevent saturation. In general,
ferrite or molypermalloy materials are the
better choice for all but the most cost sensitive applications.
Inductor Selection
There are many factors to consider in selecting the inductor including cost, efficiency,
size and EMI. In a typical SP6136 circuit,
the inductor is chosen primarily for value,
saturation current and DC resistance. Increasing the inductor value will decrease
output voltage ripple, but degrade transient
response. Low inductor values provide the
smallest size, but cause large ripple currents, poor efficiency and need more output
capacitance to smooth out the larger ripple
current. The inductor must also be able to
handle the peak current at the switching
frequency without saturating, and the copper
resistance in the winding should be kept as
low as possible to minimize resistive power
loss. A good compromise between size, loss
and cost is to set the inductor ripple current
to be within 20% to 40% of the maximum
output current.
The switching frequency and the inductor
operating point determine the inductor value
as follows:
L=
The power dissipated in the inductor is equal
to the sum of the core and copper losses.
To minimize copper losses, the winding
resistance needs to be minimized, but this
usually comes at the expense of a larger
inductor. Core losses have a more significant
contribution at low output current where the
copper losses are at a minimum, and can
typically be neglected at higher output currents where the copper losses dominate.
Core loss information is usually available
from the magnetic vendor.
Vout • (vin(max) - Vout)
Vin(max) • Fs • Kr • Iout(max)
where:
Fs = switching frequency
Kr = ratio of the ac inductor ripple current
to the maximum output current
The copper loss in the inductor can be calculated using the following equation:
The peak to peak inductor ripple current is:
where IL(RMS) is the RMS inductor current that
can be calculated as follows:
Ipp =
pl(cu) = i2l(rms) • rwinding
vout • (vin(max) - vout)
vin(max) • fs • L
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APPLICATION INFORMATION
il(rms) =
iout(max) x
∆Vout = Peak to Peak Output Voltage Ripple
Ipk-pk = Peak to Peak Inductor Ripple Current
√
1+1 •
3
{i
Ipp
out(max)
The total output ripple is a combination of
the ESR and the output capacitance value
and can be calculated as follows:
2
}
Output Capacitor Selection
∆Vout =
The required ESR (Equivalent Series Resistance) and capacitance drive the selection of the type and quantity of the output
capacitors. The ESR must be small enough
that both the resistive voltage deviation due
to a step change in the load current and
the output ripple voltage do not exceed
the tolerance limits expected on the output
voltage. During an output load transient,
the output capacitor must supply all the additional current demanded by the load until
the SP6136 adjusts the inductor current to
the new value.
.
√
(Ipp•Resr)2 +
{ CI
• (1-D)
out • Fs
pp
}
2
where:
Fs = Switching Frequency
D = Duty Cycle
Cout = output capacitance value
Input Capacitor Selection
The input capacitor should be selected for
ripple current rating, capacitance and voltage
rating. The input capacitor must meet the
ripple current requirement imposed by the
switching current. In continuous conduction
mode, the source current of the high-side
MOSFET is approximately a square wave
of duty cycle VOUT/VIN. Most of this current
is supplied by the input bypass capacitors.
The RMS value of input capacitor current is
determined at the maximum output current
and under the assumption that the peak to peak
inductor ripple current is low, it is given by:
Therefore, the capacitance must be large
enough so that the output voltage is held up
while the inductor current ramps up or down
to the value corresponding to the new load
current. Additionally, the ESR in the output
capacitor causes a step in the output voltage
equal to the current. Because of the fast transient response and inherent 100% and 0%
duty cycle capability provided by the SP6136
when exposed to output load transients, the
output capacitor is typically chosen for ESR,
not for capacitance value.
.
√
icin(rms) = iout(max) x D • (1-D)
The output capacitor’s ESR, combined with
the inductor ripple current, is typically the
main contributor to output voltage ripple.
The maximum allowable ESR required to
maintain a specified output voltage ripple
can be calculated by:
Schottky Diode Selection
When paralleled with the bottom MOSFET,
an optional Schottky diode can improve
efficiency and reduce noise. Without this
Schottky diode, the body diode of the bottom MOSFET conducts the current during
the non-overlap time when both MOSFETs
are turned off. Unfortunately, the body di-
RESR < ∆Vout
Ipk-pk
where:
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APPLICATION INFORMATION
ode has high forward voltage and reverse
recovery problems. The reverse recovery of
the body diode causes additional switching
noise when the diode turns off. The Schottky
diode alleviates these sources of noise and
additionally improves efficiency thanks to its
low forward voltage. The reverse voltage
across the diode is equal to input voltage,
and the diode must be able to handle the
peak current equal to the maximum load
current.
The goal of loop compensation is to manipulate loop frequency response such that its
gain crosses over 0db at a slope of -20db/
dec. The first step of compensation design
is to pick the loop crossover frequency. High
crossover frequency is desirable for fast
transient response, but often jeopardizes
the system stability. Crossover frequency
should be higher than the ESR zero but
less than 1/5 of the switching frequency.
The ESR zero is contributed by the ESR
associated with the output capacitors and
can be determined by:
The power dissipation of the Schottky diode
is determined by:
PDIODE = 2 • VF • IOUT • TNOL • FS
ƒz(esr) = 1
where:
TNOL = non-overlap time between GH and GL.
VF = forward voltage of the Schottky diode.
The next step is to calculate the complex
conjugate poles contributed by the LC output
filter,
Loop Compensation Design
The open loop gain of the whole system can
be divided into the gain of the error amplifier, PWM modulator, buck converter output
stage, and feedback resistor divider. In order to cross over at the selected frequency
fco, the gain of the error amplifier has to
compensate for the attenuation caused by
the rest of the loop at this frequency.
Type III Voltage Loop
Compensation
GAMP (s) Gain Block
VREF
(Volts)
+
_
2π • Cout • Resr
1
ƒP(LC) =
√
2π • L • Cout
When the output capacitors are of a Ceramic
Type, the SP6136 Evaluation Board requires
a Type III compensation circuit to give a phase
boost of 180° in order to counteract the effects
of an under damped resonance of the output
filter at the double pole frequency.
PWM Stage
GPWM Gain
Block
Output Stage
GOUT (s) Gain
Block
(SRz2Cz2+1)(SR1Cz3+1)
VIN
(SRESRCOUT+ 1)
SR1Cz2(SRz3Cz3+1)(SRz2Cp1+1)
VRAMP_PP
[S2LCOUT+S(RESR+RDC) COUT+1]
VOUT
(Volts)
Notes: RESR = Output Capacitor Equivalent Series Resistance.
RDC = Output Inductor DC Resistance.
VRAMP_PP = SP6132 Internal RAMP Amplitude Peak to Peak Voltage.
Condition: Cz2 >> Cp1 & R1 >> Rz3
Output Load Resistance >> RESR & RDC
Voltage Feedback
GFBK Gain Block
R2
VFBK
(Volts)
(R1 + R2)
or
VREF
VOUT
Figure 5: SP6136 Voltage Mode
Definitions:
Control Loop with Loop Dynamic
Resr = Output Capacitor Equivalent Series Resistance
Rdc = Output Inductor DC Resistance
Vramp _ pp = SP6136 internal RAMP Amplitude Peak to Peak Voltage
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APPLICATION INFORMATION
Gain
(dB)
Error Amplifier Gain
Bandwidth Product
Condition:
C22 >> CP1, R1 >> RZ3
1/6.28 (RZ3) (CZ3)
1/6.28 (RZ2) (CP1)
1/6.28 (R1) (CZ2)
1/6.28 (R1) (CZ3)
1/6.28(R22) (CZ2)
20 Log (RZ2/R1)
Frequency
(Hz)
Figure 6: Bode Plot of Type III Error Amplifier Compensation
Note: Loop Compensation component calculations discussed in this Datasheet can
be quickly iterated with the Type III Loop Compensation Calculator on the web at:
www.sipex.com/files/Application-Notes/TypeIIICalculator.xls
INDUCTORS - SURFACE MOUNT
Inductor Specification
Inductance
(uH)
Manufacturer
2.2
InterTechnical
Part No.
SC7232-2R2M
Series R
Isat
Size
m
(A)
LxW(mm) Ht.(mm)
10.4
13.00
7.2x6.6
Inductor Type
3.20
Manufacturer
Website
Shielded Ferrite Core www.inter-technical.com
CAPACITORS - SURFACE MOUNT
Capacitance
Manufacturer
(uF)
22
TDK
TDK
100
Capacitor Specification
Part No.
ESR
(max)
C3225X5R1C226M
C3225X5R0J107M
Ripple Current
Size
Voltage
(A) @ 45°C LxW(mm) Ht.(mm)
Capacitor
Manufacturer
(V)
Type
Website
0.005
4.00
3X2
2.00
16.0
X5R Ceramic
www.TDK.com
0.005
4.00
3X2
2.00
6.3
X5R Ceramic
www.TDK.com
Voltage
Foot Print
Manufacturer
MOSFETS - SURFACE MOUNT
MOSFET Specification
MOSFET
N-Ch
N-Ch
Manufacturer
VISHAY
VISHAY
Part No.
Si4354DY
Si4886DY
RDS(on)
ID Current
(max)
(A)
nC (Typ)
Qg
nC (Max)
(V)
18.50
13.5
9.0
11.0
7.0
14.5
10.5
20.0
30.0
SO-8
www.vishay.com
30.0
SO-8
www.vishay.com
Website
Table 1. Input and Output Stage Components Selection Charts
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APPLICATION INFORMATION
Figure 7: SP6136 output ripple is 32mV at Iout=7A
Figure 8: SP6136 Step load response 0-5A, top trace is Vout (100mV/div), bottom
trace Iload (2A/div)
Figure 9: SP6136 startup at full load, Ch1: Vin, Ch2: Vout, Ch3:PWRGD, Ch4: SS
Oct 31-06 Rev L
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© 2006 Sipex Corporation
APPLICATION INFORMATION
SP6136 Efficiency versus Iout
@ Vin=12V, Vout=3.3V
Efficiency (%)
96
94
92
90
88
.0
2.0
3.0
4.0
5.0
6.0
7.0
Iout (A)
SP6136 Load Regulation
@ Vin=12V
3.350
Vout (V)
3.348
3.346
3.344
3.342
3.340
.0
2.0
3.0
4.0
5.0
6.0
7.0
Iout (A)
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© 2006 Sipex Corporation
Package: 3mmX3MM 16 Pin QFN
Oct 31-06 Rev L
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© 2006 Sipex Corporation
ORDERING INFORMATION
Part Number
Temperature Range
Package
SP6136ER1............................................ ....-40°C to +85°C...................... 3mm X 3mm 16 Pin QFN
SP6136ER1/TR...................................... ....-40°C to +85°C...................... 3mm X 3mm 16 Pin QFN
Available in lead free packaging. To order add "-L" suffix to part number.
Example: SP6136ER1/TR = standard; SP6136ER1-L/TR = lead free
/TR = Tape and Reel
Pack quantity is 3000 for QFN.
Sipex Corporation
Headquarters and
Sales Office
233 South Hillview Drive
Milpitas, CA 95035
TEL: (408) 934-7500
FAX: (408) 935-7600
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume
any liability arising out of the application or use of any product or circuit described herein; neither does it convey
any license under its patent rights nor the rights of others.
Oct 31-06 Rev L
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© 2006 Sipex Corporation
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