SP6205EM5-2-8

® Solved by SP6203/6205 SP6203/6205 TM Low Noise, 300mA and 500mA CMOS LDO Regulators Low Noise, 300mA and 500mA CMOS LDO Regulators ■ Very Low Dropout Voltage: 0.6 PMOS Pass Device ■ Accurate Output Voltage: 2% over Temperature ■ Guaranteed 500mA Output Current: SP6205 ■ Ultra Low Noise Output: 2µVRMS with 0nF Bypass ■ Unconditionally Stable with 2.2µF Ceramic ■ Low Quiescent Current: 5µA ■ Very Low Ground Current: 350µA at 500 mA ■ Power-Saving Shutdown Mode: < µA ■ Fast Turn-On and Turn-Off: 60µS ■ Fast Transient Response ■ Current Limit and Thermal Shutdown Protection ■ Very Good Load/Line Regulation: 0.07/0.0% ■ Excellent PSRR: 67dB < kHz ■ Industry Standard SOT-23-5 and Small  pin 2X3 DFN Package ■ Fixed Output Voltages: 2.5V, 2.7V, 2.V, 2.5V, 3.0V and 3.3V ■ Adjustable Output Available FEATURES FiXED VOUT BYP GND EN  2 3  ADJUSTABLE  VOUT 7 6 NC NC VIN SP6203 SP6205 8 Pin DFN ADJ  NC GND EN 2 3  SP6203 SP6205 8 Pin DFN  7 6 5 VOUT NC NC VIN 5 Now Available in Lead Free Packaging APPLiCATiONS ■ Cellular / GSM Phones ■ Laptop / Palmtop Computers ■ Battery-Powered Systems ■ Pagers ■ Medical Devices ■ MP3/CD Players ■ Digital Still Cameras DESCRiPTiON The SP6203/6205 are ultra low noise CMOS LDOs with very low dropout and ground current. The noise performance is achieved by means of an external bypass capacitor without sacrificing turn-on and turn-off speed critical to portable applications. Extremely stable and easy to use, these devices offer excellent PSRR and Line/Load regulation. Target applications include battery-powered equipment such as portable and wireless products. Regulators' ground current increases only slightly in dropout. Fast turn-on/turn-off enable control and an internal 30 pull down on output allows quick discharge of output even under no load conditions. Both LDOs are protected with current limit and thermal shutdown. Both LDOs are available in fixed & adjustable output voltage versions and come in an industry standard SOT-23 5-pin and small 2X3 pin DFN packages. For SC-70 00mA CMOS LDO, SP623 is available. TYPiCAL APPLiCATiON CiRCUiT VIN CIN 2.2µF 2 1 5 VOUT COUT 2.2µF Ceramic CIN 2.2µF VIN 1 5 VOUT COUT 2.2µF Ceramic SP6203 SP6205 5-Pin FIXED 4 BYP 2 SP6203 SP6205 5-Pin ADJUSTABLE 4 ADJ EN 3 EN 3 Date: 2//05 Date: Apr2-07 SP6203/SP6205 Low Noise, 300 and 500mA CMOS LDO Regulators SP6203/6205 © 2007 © Copyright 2005 Sipex Corporation   ABSOLUTE MAXiMUM RATiNGS Supply Input Voltage (VIN)..........................................................-2V to 6V Output Voltage (VOUT).....................................................-0.6V to VIN +V Enable Input Voltage (VEN)........................................................-2V to 6V Power Dissipation (PD)......................................Internally Limited, Note  Lead Temperature (soldering 5s)...........................................+260°C Storage Temperature.....................................................-65°C to +50°C Junction Temperature..........................................................+50°C These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. OPERATiNG RATiNGS Input Voltage (V IN )...........................................+2.7V to +5.5V E nable Input Voltage (V EN)...........................................0 to 5.5V Junction Temperature (TJ)...........................................-0°C to +25°C Thermal Resistance, SOT-23-5 ( JA)...........................................Note  Thermal Resistance, SOT-23-6 ( JA)...........................................Note  Remark: The device is not guaranteed to function outside its operating rating. Unless otherwise specified: VIN=VOUT + 0.5V to 6V, COUT = 2.2µF ceramic, CIN = 2.2µF, IOUT =00µA, -0°C < T < 25°C. The denotes the specifications which apply over full operating temperature range -0°C to +25°C, unless otherwise specified. PARAMETER Input Voltage Output Voltage Accuracy Output Voltage Temperature Coefficient, Note2 Reference Voltage Line Regulation Load Regulation, Note 3 Dropout Voltage for VOUT > 3.0V, Note  MiN -2 50 .225 .25 0.0 0.07 0.3 0.06 60 20 0 300 5 0 75 235 350 0.0 0.50 0.5 70 2 67 50 630 2 50 0.05 25 60 00 5 30 .6 .275 0.3 0.3 0.5 TYP MAX 6 +2 UNiTS V % ppm/°C V %/V % CONDiTiONS Variation from specified VOUT VOUT/ T Adjustable version only VOUT (VIN below 6V) IOUT = 0.mA to 300mA (SP6203) IOUT = 0.mA to 500mA (SP6205) IOUT = 0.mA IOUT = 00mA IOUT = 200mA IOUT = 300mA (SP6203) IOUT = 500mA (SP6205) IOUT = 0.mA (IQUIESCENT) IOUT = 00mA IOUT = 200mA IOUT = 300mA (SP6203) IOUT = 500mA (SP6205) VEN < 0.V (shutdown) VOUT = ZeroV (SP6203) VOUT = ZeroV (SP6205) Regulator Turns off Regulator turns on again at 5°C f kHz CBYP = 0nF, IOUT = 0.mA CBYP = 0nF, IOUT =300mA CBYP = 0nF, IOUT = 0.mA CBYP = 0nF, IOUT = 300mA VOUT/ PD VIN V, Note 0 IOUT = 30mA VIN V, Note 0 IOUT = 30mA IOUT = 0.mA, VIN V, Note 0 IOUT = 300mA, VIN V, Note 0 No Load Regulator Shutdown Regulator Enabled ELECTRiCAL SPECiFiCATiONS Ground Pin Current, Note 5 300 500 00 330 0  0. . mV µA µA A °C °C dB µVRMS %/W µs µs µs Shutdown Supply Current Current Limit Thermal Shutdown Junction Temperature Thermal Shutdown Hysteresis Power Supply Rejection Ratio Output Noise Voltage, Note 6 0.33 0.55 75 50 20 250 25 0. Thermal Regulation, Note 7 Wake-Up Time (TWU), Note  (from shutdown mode) Turn-On Time (TON), Note  (from shutdown mode) Turn-Off Time (TOFF), Output Discharge Resistance Enable Input Logic Low Voltage Enable Input Logic High Voltage Date: Apr2-07 Date: 2//05 V V SP6203/SP6205 Low Noise, 300 and 500mA CMOS LDO Regulators SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators 2 2 © 2007 Sipex Corporation © Copyright 2005 Sipex Corporation ELECTRiCAL SPECiFiCATiONS NOTES Note 1: Maximum power dissipation can be calculated using the formula: PD = (TJ(max) - TA) / JA, where TJ(max) is the junction temperature, TA is the ambient temperature and JA is the junction-to-ambient thermal resistance. JC is 6°C/W for this package. Exceeding the maximum allowable power dissipation will result in excessive die temperature and the regulator will go into thermal shutdown mode. JA is 191°C/W for SOT-23-5, and is 59°C/W for the -pin DFN. A part mounted on a PC board will deliver improved thermal performance based upon copper surface area. Note 2: Output voltage temperature coefficient is defined as the worst case voltage change divided by the total temperature range. Note 3: Regulation is measured at constant junction temperature using low duty cycle pulse testing. Changes in output voltage due to heating effects are covered by the thermal regulation specification. Note 4: Dropout-voltage is defined as the input to output differential at which the output voltage drops 2% below its nominal value measured at V differential. Note 5: Ground pin current is the regulator quiescent current. The total current drawn from the supply is the sum of the load current plus the ground pin current. Note 6: Output noise voltage is defined within a certain bandwidth, namely 0Hz < BW < 00kHz. An external bypass cap (0nF) from reference output (BYP pin) to ground significantly reduces noise at output. Note 7: Thermal regulation is defined as the change in output voltage at a time “t” after a change in power dissipation is applied, excluding load and line regulation effects. Specifications are for a 300mA load pulse at VIN = 6V for t = ms. Note 8: The wake-up time (TWU) is defined as the time it takes for the output to start rising after enable is brought high. Note 9: The total turn-on time is called the settling time (TS), which is defined as the condition when both the output and the bypass node are within 2% of their fully enabled values when released from shutdown. Note 10: For output voltage versions requiring VIN to be lower than V, timing (TON & TOFF) increases slightly. FUNCTIONAL DIAGRAM VIN EN bandgap 1.25V reference VOUT VIN EN bandgap 1.25V reference VOUT R1 BYP current limit & thermal shutdown GND Cbyp (optional) ADJ current limit & thermal shutdown GND R2 Low Noise Fixed Regulator - 5 Pin Low Noise Adjustable Regulator - 5 Pin Date: Apr2-07 Date: 2//05 SP6203/SP6205 Low Noise, 300 and 500mA CMOS LDO Regulators SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators 3 3 © 2007 Sipex Corporation © Copyright 2005 Sipex Corporation PiN DESCRiPTiON 5 PiN OPTiON PIN NUMBER  2 3  (Fixed) NAME VIN GND EN BYP FUNCTION Power Supply Input Ground Terminal Enable/Shutdown (Logic high = enable, logic low = shutdown) Reference bypass input for ultra-quiet operation. Connecting a 0nF cap on this pin reduces output noise. Adjustable (Input): Adjustable regulator feedback input. Connect to a resistive voltagedivider network. Regulator Output Voltage  (adj.) ADJ 5 VOUT PiNOUT 5 PiN SOT-23 EN GND VIN 2 1 3 EN GND VIN 3 2 1 SIPEX 4 BYP 5 VOUT 4 SIPEX 5 VOUT ADJ Fixed Voltage Regulator Adjustable Voltage Regulator Date: 2//05 Date: Apr2-07 SP6203/SP6205 Low Noise, 300 and 500mA CMOS LDO Regulators SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators © 2005 Sipex Corporation © Copyright 2007 Sipex Corporation   PiN DESCRiPTiON 8 PiN OPTiON  PIN DFN PIN NUMBER (fixed) (Adj) PIN CONFIGURATION NAME VOUT ADJ FUNCTION Regulator Output Voltage. Connect to Pin  VOUT. Adjustable (Input): Adjustable regulator feedback input. Connect to a resistive voltagedivider network. Reference bypass input for ultra-quiet operation. Connecting a 0nF cap on this pin reduces output noise. No Connect Ground Enable/Shutdown (Logic high = enable, logic low = shutdown) Power Supply Input No Connect No Connect Regulator Output VoltageA PiNOUT 8 PiN DFN 2(fixed) BYP 2(Adj) 3  5 6 7  NC GND EN VIN NC NC VOUT FiXED VOUT BYP GND EN  2 3  ADJUSTABLE  VOUT 7 6 NC NC VIN SP6203 SP6205 8 Pin DFN ADJ  NC GND EN 2 3  SP6203 SP6205 8 Pin DFN  7 6 5 VOUT NC NC VIN 5 Date: 2//05 Date: Apr2-07 SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators SP6203/SP6205 Low Noise, 300 and 500mA CMOS LDO Regulators 5 5 © Copyright 2005 Sipex Corporation © 2007 Sipex Corporation TYPiCAL PERFORMANCE CHARACTERiSTiCS VOUT VOUT IO (200mA/DIV) VEN Current Limit Turn on Time, RLOAD = 50 (60mA) VOUT VOUT VEN VEN Turn off Time, RLOAD = 6 (500mA) Turn off Time, RLOAD = 30K (0.1mA) VOUT (AC) VOUT (AC) ViN iOUT Load Regulation, IO = 100µA ~ 500mA Line Regulation, Line Step from 4V to 6V, IO = 1mA Date: Apr2-07 Date: 2//05 SP6203/6205 SP6203/SP6205 Low Noise, 300 and 500mA CMOS LDO Regulators © Copyright 2005 Sipex Corporation © 2007 6 6 TYPiCAL PERFORMANCE CHARACTERiSTiCS: Continued VIN VEN VOUT VOUT VIN = 3.5V, IO = 500mA BYP Start Up Waveform, VIN = 3.5V, IO = 500mA Start Up Waveform, Slow VIN , No Load VIN VIN VOUT VOUT BYP BYP Start Up Waveform, Slow VIN , 500mA Output Load Start Up Waveform, Slow VIN , COUT=1000µF, IO=0mA VIN VIN VOUT VOUT BYP BYP Start Up Waveform, Slow VIN, COUT=1000µF, IO=500mA Fast VIN , No Load Date: Apr2-07 Date: 2//05 SP6203/6205 SP6203/SP6205 Low Noise, 300 and 500mA CMOS LDO Regulators © Copyright 2005 Sipex Corporation © 2007 7 7 TYPiCAL PERFORMANCE CHARACTERiSTiCS: Continued VIN VOUT BYP Fast VIN , 500mA Output Load Fast VIN = 1000µF Output Load VIN VOUT BYP Fast VIN , COUT=1000µF, IO=500mA Output Noise (uVrms), Cbyp = 10nF 50 Noise (uVrms) Output Noise (uVrms), Cbyp = open 000 Noise (uVrms) 0 30 20 0 0 0.  0 00 000 Output current (mA) 00 600 00 200 0 0.  0 00 000 Output current (mA) Date: 2//05 Date: Apr2-07 SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators SP6203/SP6205Low Noise, 300 and 500mA CMOS LDO Regulators © Copyright 2005 Sipex Corporation © 2007 Sipex Corporation   THEORY OF OPERATiON General Overview Output Capacitor The SP6203/6205 is intended for applications where very low dropout voltage, low supply current and low output noise are critical, even with high load conditions (500mA maximum). Unlike bipolar regulators, the SP6203/6205 (CMOS LDO) supply current increases only slightly with load current. The SP6203/6205 contains an internal bandgap reference which is fed into the inverting input of the LDO-amplifier. The output voltage is then set by means of a resistor divider and compared to the bandgap reference voltage. The error LDO-amplifier drives the gate of a P-channel MOSFET pass device that has a RDS(ON) of 0.6 at 500mA producing a 300mV drop at the output. Furthermore, the SP6203/6205 has its own current limit circuitry (500mA/850mA) to ensure that the output current will not damage the device during output short, overload or start-up. Also, the SP6203/6205 includes thermal shutdown circuitry to turn off the device when the junction temperature exceeds 170°C and it remains off until the temperature drops by 12°C. Enable/Shutdown Operation An output capacitor is required between VOUT and GND to prevent oscillation. A 2.2µF output capacitor is recommended. Larger values make the chip more stable which means an improvement of the regulator’s transient response. Also, when operating from other sources than batteries, supply-noise rejection can be improved by increasing the value of the input and output capacitors and using passive filtering techniques. For a lower output current, a smaller output capacitance can be chosen. Finally, the output capacitor should have an effective series resistance (ESR) of 0.5 or less. Therefore, the use of good quality ceramic or tantalum capacitors is advised. Bypass Capacitor The SP6203/6205 is turned off by pulling the VEN pin below 0.4V and turned on by pulling it above 1.6V. If this enable/shutdown feature is not required, it should be tied directly to the input supply voltage to keep the regulator output on at all time. While in shutdown, VOUT quickly falls to zero (turn-off time is dependent on load conditions and output capacitance on VOUT) and power consumption drops nearly to zero. input Capacitor A bypass pin (BYP) is provided to decouple the bandgap reference. A 10nF external capacitor connected from BYP to GND reduces noise present on the internal reference, which in turn significantly reduces output noise and also improves power supply rejection. Note that the minimum value of COUT must be increased to maintain stability when the bypass capacitor is used because CBYP reduces the regulator phase margin. If output noise is not a concern, this input may be left unconnected. Larger capacitor values may be used to further improve power supply rejection, but result in a longer time period (slower turn on) to settle output voltage when power is initially applied. No Load Stability A small capacitor of 2.2µF is required from VIN to GND if a battery is used as the power source. Any good quality electrolytic, ceramic or tantalum capacitor may be used at the input. The SP6203/6205 will remain stable and in regulation with no external load (other than the internal voltage driver) unlike many other voltage regulators. This is especially important in CMOS RAM battery back-up applications. Date: Apr2-07 Date: 2//05 SP6203/SP6205 Low Noise, 300 and 500mA CMOS LDO Regulators SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators   © 2005 Sipex Corporation © Copyright2007 Sipex Corporation THEORY OF OPERATiON: Continued Turn On Time The turn on response is split up in two separate response categories: the wake up time (TWU) and the settlling time (TS). The wake up time is defined as the time it takes for the output to rise to 2% of its total value after being released from shutdown (EN > 0.4V). The settling time is defined as the condition where the output reaches 98% of its total value after being released from shutdown. The latter is also called the turn on time and is dependent on the output capacitor, a little bit on load and, if present, on a bypass capacitor. TJ(max) is the maximum junction temperature of the die and is 125°C. TA is the ambient temperature. JA is the junction-to-ambient thermal resistance for the regulator and is layout dependent. The SOT-23-5 package has a JA of approximately 256°C/W for minimum PCB copper footprint area. This results in a maximum power dissipation of: PD(max) = [(125°C - 25°C)/(191°C/W)] = 523mW The actual power dissipation of the regulator circuit can be determined using one simple equation: PD = (VIN - VOUT) * IOUT + VIN * IGND VENABLE VOUT 2% t(wu) t(s) = T(on) % Turn Off Time The turn off time is defined as the condition where the output voltage drops about 66% ( ) of its total value. 5 to 7 is the constant where the output voltage drops nearly to zero. There will always be a small voltage drop in shutdown because of the switch unless we short-circuit it. The turn off time of the output voltage is dependent on load conditions, output capacitance on VOUT (time constant = RLCL) and also on the difference in voltage between input and output. Thermal Considerations To prevent the device from entering thermal shutdown. maximum power dissipation can not be exceeded. Substituting PD(max) for PD and solving for the operating conditions that are critical to the application will give the maximum operating conditions for the regulator circuit. For example, if we are operating the SP6203 3.0V at room temperature, with a minimum footprint layout and and output current of 300mA, the maximum input voltage can be determined, based on the equation below. Ground pin current can be taken from the electrical specifications table (0.23mA at 300mA). 390mW = (VIN-3.0V) * 300mA + VIN *0.23mA After calculations, we find that the maximum input voltage of a 3.0V application at 300mA of output current in a SOT-23-5 package is 4.7V. So if the intend is to operate a 5V output version from a 6V supply at 300mA load and at a 25°C ambient temperature, then the actual total power dissipation will be: PD=([6V-5V]*[300mA])+(6V*0.23mA)=301.4mW This is well below the 523mW package maximum. Therefore, the regulator can be used. The SP6203/6205 is designed to provide 300/ 500 mA of continuous current in a tiny package. Maximum power dissipation can be calculated based on the output current and the voltage drop across the part. To determine the maximum power dissipation of the package, use the junction-to-ambient thermal resistance of the device and the following basic equation: PD = (TJ(max) - TA) / JA Date: 2//05 Date: Apr2-07 SP6203/SP6205 Low Noise, 300 and 500mA CMOS LDO Regulators SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators © 2005 Sipex Corporation © Copyright 2007 Sipex Corporation 0 0 THEORY OF OPERATiON: Continued Note that the regulator cannot always be used at its maximum current rating. For example, in a 5V input to 3.0V output application at an ambient temperature of 25°C and operating at the full 500mA (IGND = 0.355mA) load, the regulator is limited to a much lower load current, determined by the following equation: 523mW = ( [5V-3V]*[ Iload(max)]) +(5V*0.350mA) After calculation, we find that in such an application (SP6205) the regulator is limited to 260.6mA. Doing the same calculations for the 300mA LDO (SP6203) will limit the regulator’s output current to 260.9mA. Also, taking advantage of the very low dropout voltage characteristics of the SP6203/6205, power dissipation can be reduced by using the lowest possible input voltage to minimize the input-to-output drop. Adjustable Regulator Applications Layout Considerations The primary path of heat conduction out of the package is via the package leads. Therefore, careful considerations have to be taken into account: 1) Attaching the part to a larger copper footprint will enable better heat transfer from the device, especially on PCB’s where there are internal ground and power planes. 2) Place the input, output and bypass capacitors close to the device for optimal transient response and device behavior. 3) Connect all ground connections directly to the ground plane. In case there’s no ground plane, connect to a common local ground point before connecting to board ground. Such layouts will provide a much better thermal conductivity (lower JA) for, a higher maximum allowable power dissipation limit. The SP6203/6205 can be adjusted to a specific output voltage by using two external resistors (see functional diagram). The resistors set the output voltage based on the following equation: VOUT = VREF *(R1/R2 + 1) Resistor values are not critical because ADJ (adjust) has a high input impedance, but for best performance use resistors of 470K or less. A bypass capacitor from ADJ to VOUT provides improved noise performance. Dual-Supply Operation When used in dual supply systems where the regulator load is returned to a negative supply, the output voltage must be diode clamped to ground. Date: Apr2-07 Date: 2//05 SP6203/SP6205 Low Noise, 300 and 500mA CMOS LDO Regulators SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators   © 2007 Sipex Corporation © Copyright 2005 Sipex Corporation PACKAGE: 5Pin SOT-23 Date: Apr2-07 SP6203/SP6205 Low Noise, 300 and 500mA CMOS LDO Regulators © 2007 Sipex Corporation 2 PACKAGE: 8Pin DFN Date: Apr2-07 SP6203/SP6205 Low Noise, 300 and 500mA CMOS LDO Regulators © 2007 Sipex Corporation 3 ORDERiNG iNFORMATiON Part Number SP6203EM5-- SP6203EM5--/TR SP6203EM5-2-5 SP6203EM5-2-5/TR SP6203EM5-2-7 SP6203EM5-2-7/TR SP6203EM5-2- SP6203EM5-2-/TR SP6203EM5-2-5 SP6203EM5-2-5/TR SP6203EM5-3-0 SP6203EM5-3-0/TR SP6203EM5-3-3 SP6203EM5-3-3/TR SP6203EM5 SP6203EM5/TR SP6203ER-- SP6203ER--/TR SP6203ER-2-5 SP6203ER-2-5/TR SP6203ER-2-7 SP6203ER-2-7/TR SP6203ER-2- SP6203ER-2-/TR SP6203ER-2-5 SP6203ER-2-5/TR SP6203ER-3-0 SP6203ER-3-0/TR SP6203ER-3-3 SP6203ER-3-3/TR SP6203ER SP6203ER/TR Solved by Top Marking N2WW N2WW L2WW L2WW G2WW G2WW Q3WW Q3WW H2WW H2WW M2WW M2WW J2WW J2WW Q2WW Q2WW Temperature Voltage Package Range Option Type -40˚C to +125˚C -40˚C to +125˚C -40˚C to +125˚C -40˚C to +125˚C -40˚C to +125˚C -40˚C to +125˚C -40˚C to +125˚C -40˚C to +125˚C -40˚C to +125˚C -40˚C to +125˚C -40˚C to +125˚C -40˚C to +125˚C -40˚C to +125˚C -40˚C to +125˚C -40˚C to +125˚C -40˚C to +125˚C .V .V 2.5V 2.5V 2.7V 2.7V 2.V 2.V 2.5V 2.5V 3.0V 3.0V 3.3V 3.3V ADJ ADJ .V .V 2.5V 2.5V 2.7V 2.7V 2.V 2.V 2.5V 2.5V 3.0V 3.0V 3.3V 3.3V ADJ ADJ 5 Pin SOT-23 5 Pin SOT-23 5 Pin SOT-23 5 Pin SOT-23 5 Pin SOT-23 5 Pin SOT-23 5 Pin SOT-23 5 Pin SOT-23 5 Pin SOT-23 5 Pin SOT-23 5 Pin SOT-23 5 Pin SOT-23 5 Pin SOT-23 5 Pin SOT-23 5 Pin SOT-23 5 Pin SOT-23  Pin DFN  Pin DFN  Pin DFN  Pin DFN  Pin DFN  Pin DFN  Pin DFN  Pin DFN  Pin DFN  Pin DFN  Pin DFN  Pin DFN  Pin DFN  Pin DFN  Pin DFN  Pin DFN 6203YWW -40˚C to +125˚C 6203YWW -40˚C to +125˚C 620325YWW -40˚C to +125˚C 620325YWW -40˚C to +125˚C 620327YWW -40˚C to +125˚C 620327YWW -40˚C to +125˚C 62032YWW -40˚C to +125˚C 62032YWW -40˚C to +125˚C 62035YWW -40˚C to +125˚C 62035YWW -40˚C to +125˚C 620330YWW -40˚C to +125˚C 620330YWW -40˚C to +125˚C 620333YWW -40˚C to +125˚C 620333YWW -40˚C to +125˚C 6203ERYWW -40˚C to +125˚C 6203ERYWW -40˚C to +125˚C TM Date: Apr2-07 SP6203/SP6205 Low Noise, 300 and 500mA CMOS LDO Regulators © 2007 Sipex Corporation  ORDERiNG iNFORMATiON Part Number SP6205EM5-- SP6205EM5--/TR SP6205EM5-2-5 SP6205EM5-2-5/TR SP6205EM5-2-7 SP6205EM5-2-7/TR SP6205EM5-2- SP6205EM5-2-/TR SP6205EM5-2-5 SP6205EM5-2-5/TR SP6205EM5-3-0 SP6205EM5-3-0/TR SP6205EM5-3-3 SP6205EM5-3-3/TR SP6205EM5 SP6205EM5 /TR SP6205ER-- SP6205ER--/TR SP6205ER-2-5 SP6205ER-2-5/TR SP6205ER-2-7 SP6205ER-2-7/TR SP6205ER-2- SP6205ER-2-/TR SP6205ER-2-5 SP6205ER-2-5/TR SP6205ER-3-0 SP6205ER-3-0/TR SP6205ER-3-3 SP6205ER-3-3/TR SP6205ER SP6205ER /TR Solved by Top Marking X2WW X2WW V2WW V2WW R2WW R2WW E3WW E3WW S2WW S2WW W2WW W2WW T2WW T2WW A3WW A3WW 6205YWW 6205YWW 620525YWW 620525YWW 620527YWW 620527YWW 62052YWW 62052YWW 62055YWW 62055YWW 620530YWW 620530YWW 620533YWW 620533YWW 6205ERYWW 6205ERYWW Temperature Voltage Range Option -40˚C to +125˚C -40˚C to +125˚C -40˚C to +125˚C -40˚C to +125˚C -40˚C to +125˚C -40˚C to +125˚C -40˚C to +125˚C -40˚C to +125˚C -40˚C to +125˚C -40˚C to +125˚C -40˚C to +125˚C -40˚C to +125˚C -40˚C to +125˚C -40˚C to +125˚C -40˚C to +125˚C -40˚C to +125˚C -40˚C to +125˚C -40˚C to +125˚C -40˚C to +125˚C -40˚C to +125˚C -40˚C to +125˚C -40˚C to +125˚C -40˚C to +125˚C -40˚C to +125˚C -40˚C to +125˚C -40˚C to +125˚C -40˚C to +125˚C -40˚C to +125˚C -40˚C to +125˚C -40˚C to +125˚C -40˚C to +125˚C -40˚C to +125˚C .V .V 2.5V 2.5V 2.7V 2.7V 2.V 2.V 2.5V 2.5V 3.0V 3.0V 3.3V 3.3V ADJ ADJ .V .V 2.5V 2.5V 2.7V 2.7V 2.V 2.V 2.5V 2.5V 3.0V 3.0V 3.3V 3.3V ADJ ADJ Package Type 5 Pin SOT-23 5 Pin SOT-23 5 Pin SOT-23 5 Pin SOT-23 5 Pin SOT-23 5 Pin SOT-23 5 Pin SOT-23 5 Pin SOT-23 5 Pin SOT-23 5 Pin SOT-23 5 Pin SOT-23 5 Pin SOT-23 5 Pin SOT-23 5 Pin SOT-23 5 Pin SOT-23 5 Pin SOT-23  Pin DFN  Pin DFN  Pin DFN  Pin DFN  Pin DFN  Pin DFN  Pin DFN  Pin DFN  Pin DFN  Pin DFN  Pin DFN  Pin DFN  Pin DFN  Pin DFN  Pin DFN  Pin DFN TM Date: Apr2-07 SP6203/SP6205 Low Noise, 300 and 500mA CMOS LDO Regulators © 2007 Sipex Corporation 5 For further assistance: Application note and calculator file for Thermal considerations with Linear Regulators: ANP 2 ANP 3 LDO Thermal Considerations for Linear Regulators LDO Linear Regulator Heat Calculator [PDF] [Excel] Email: WWW Support page: Sipex Application Notes: Sipexsupport@sipex.com http://www.sipex.com/content.aspx?p=support http://www.sipex.com/applicationNotes.aspx Solved by Sipex Corporation TM Headquarters and Sales Office 233 South Hillview Drive Milpitas, CA 5035 TEL: (0) 3-7500 FAX: (0) 35-7600 Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Date: Apr2-07 SP6203/SP6205 Low Noise, 300 and 500mA CMOS LDO Regulators © 2007 Sipex Corporation 6