®
SP6651A
High Efficiency 800mA Synchronous Buck Regulator
Ideal for portable designs powered with Li Ion battery
FEATURES
■ DFN Package (3mm x 3mm)
■ Ultra-low 20µA Quiescent Current
■ 98% Efficiency Possible
■ 800mA Output Current
■ 2.7V to 5.5V Input Voltage Range
■ Output Adjustable Down to 1.0V
■ No External FET’s Required
■ 1.25A Inductor Peak Current Limit
■ 100% Duty Ratio Low Dropout Operation
■ 80µA Light Load Quiescent Current
in Dropout
■ Over Temperature Protection
■ Logic Shutdown Control
■ Programmable UVLO and Adaptive
Battery Low Output
PV IN
1
V IN
2
BLON
3
D1
4
7 VOUT
D0
5
6 FB
10 LX
9 PGND
SP6651A
8 GND
10 Pin DFN
Now Available in Lead Free Packaging
APPLICATIONS
■ PDA's
■ DSC's
■ MP3 Players
■ USB Devices
■ Point of Use Power
DESCRIPTION
The SP6651A is a 800mA synchronous buck regulator which is ideal for portable applications that
use a Li-Ion or 3 cell alkaline/NiCD/NiMH input. The SP6651A’s proprietary control loop, 20µA
light load quiescent current, and 0.3Ω power switches provide excellent efficiency across a wide
range of output currents. As the input battery supply decreases towards the output voltage the
SP6651A seamlessly transitions into 100% duty ratio operation further extending useful battery
life. The SP6651A is protected against overload and short circuit conditions with a precise
inductor peak current limit. Other features include programmable under voltage lockout and low
battery detection, externally programmed output voltage down to 1.0V, logic level shutdown
control, and 140°C over temperature shutdown.
TYPICAL APPLICATION SCHEMATIC
2.7V to 5.5V Input
L1
10µH
VI
CIN
22µF
10Ω
RVIN
CVIN
LX
1µF
VO
COUT
22µF
PGND
VIN
1M
BLON
SP6651A
PVIN
VOUT
800mA
BLON
GND
D1
D1
VOUT
D0
D0
FB
CF
RF
22pF
RI
200K
Date: 5/25/04
SP6651A High Efficiency 800mA Synchronous Buck Regulator
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© Copyright 2004 Sipex Corporation
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation of the device at
these ratings or any other above those indicated in the operation
sections of the specifications below is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may
affect reliability.
PVIN,VIN .............................................................................................. 6V
All other pins .............................................................. -0.3V to VIN+0.3V
PVIN, PGND, LX current ........................................................................ 2A
Storage Temperature .................................................. -65 °C to 150 °C
Operating Temperature ................................................. -40°C to +85°C
Lead Temperature (Soldering, 10 sec) ....................................... 300 °C
Thermal Resistance øJA:
10-Pin MSOP....................................................................128°C/W
10-Pin DFN ........................................................................68°C/W
ELECTRICAL CHARACTERISTICS
VIN=UVIN=VSDN=3.6V, VOUT=VFB, IO = 0mA, TAMB = -40°C to +85°C, typical values at 27°C unless otherwise noted.
PARAMETER
Input Voltage Operating
Range
Minimum Output Voltage
FB Set Voltage, Vr
Overall Accuracy
(-40°C to 85°C)
(0°C to 70°C)
On-Time Constant - KON
Min, TON=KON/(VIN-VOUT)
Off-Time Constant - KOFF
Min, TOFF=KOFF/VOUT
Off-Time Blanking
PMOS Switch Resistance
NMOS Switch Resistance
Inductor Current Limit
LX Leakage Current
Power Efficiency
Minimum Guaranteed Load
Current
VIN Quiescent Current
VIN Shutdown Current
VOUT Quiescent Current
VOUT Shutdown Current
UVLO
Undervoltage Lockout
Threshold, VIN falling
UVLO hysteresis
Battlo Trip Voltage, VIN falling
Battlo Trip Voltage Hysteresis
BLON Low Output Voltage
BLON Leakage Current
Over-Temperature
Rising Trip Point
Over-Temperature Hysteresis
D1,D0 Leakage Current
D1,D0 Input Threshold Voltage
FB Leakage Current
Date: 5/25/04
MIN
UVLO
TYP
MAX
5.5
UNITS
V
0.800
0.816
V
V
1.5
2.25
±5
±4
3.0
V*µs
Close Loop, LI = 10µH,COUT = 22µF
1.6
2.4
3.2
V*µs
Inductor current limit tripped, VFB=0.5V
Measured at VOUT = 2V
0.6
0.6
1.50
3
ns
Ω
Ω
A
µA
%
1.0
0.784
1.0
800
2.55
2.70
2.85
265
100
0.3
0.3
1.25
0.01
96
92
900
20
1
2
1
2.70
2.85
3.00
40
300
9
%
30
500
5
500
2.85
3.00
3.15
335
140
0.60
25°C, IO=200mA Close Loop. LI = 10µH,
COUT = 22µF
Measured at VIN=5.5V, no load and
VIN=3.6V, 200mA load, Close Loop
IPMOS = 200mA
INMOS = 200mA
VFB=0.5V
D0=D1=0
VOUT=2.5V, IO=200mA
VOUT=3.3V, IO=800mA
mA
0.4
1
14
1
0.90
1.25
1
CONDITIONS
Result of IQ measurement at VIN=PVIN=5.5V
500
1.8
100
µA
nA
µA
nA
V
mV
mV
mV
V
µA
°C
°C
nA
V
V
nA
VOUT=3.3V, VIN=3.6V and VIN= 5.5V
D1=D0=0V
VOUT = 3.3V
D1=D0=0V
D1=0V, D0=VIN
D1=VIN, D0=0V
D1=VIN, D0=VIN
Measured as VIN-VOUT
VIN=3.3V, ISINK=1mA
VBLON=3.6V
High to Low Transition
Low to High Transition
FB=1V
SP6651A High Efficiency 800mA Synchronous Buck Regulator
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© Copyright 2004 Sipex Corporation
PIN DESCRIPTION
PIN NUMBER
PIN NAME
1
PVIN
DESCRIPTION
2
VIN
3
BLON
4
D1
Digital mode control input. See table I for definition.
5
D0
Digital mode control input. See table I for definition.
6
FB
External feedback network input connection. Connect a resistor from
FB to ground and FB to VOUT to set the output voltage. This pin
regulates to the internal bandgap reference voltage of 0.8V.
7
VOUT
Output voltage sense pin. Used by the timing circuit to set minimum on
and off times.
8
GND
Internal ground pin. Control circuitry returns current to this pin.
9
PGND
Power ground pin. Synchronous rectifier current returns through this pin.
10
LX
Inductor switching node. Inductor tied between this pin and the output
capacitor to create regulated output voltage.
Input voltage power pin. Inductor charging current passes through this pin.
Internal supply voltage. Control circuitry powered from this pin.
Open drain battery low output. (VIN-VO) less than 300mV pulls this
node to ground. (VIN-VO) above threshold, this node is open.
D1
D0
0
0
Shutdown. All internal circuitry is disabled and the power switches are opened.
0
1
Device enabled, falling UVLO threshold =2.70V
1
0
Device enabled, falling UVLO threshold =2.85V
1
1
Device enabled, falling UVLO threshold =3.00V
Table 1. Operating Mode Definition
FUNCTIONAL DIAGRAM
PVIN
VOUT
Vin
DRVON
VOLOW
TONOVER
MIN Ton
Internal Supply
TONOVER
Min Ton
Min Ton = KON/(VIN -VOUT)
M
Vos
VOLOW
REF +
-REF' +
-
VRAMP
FB
C
R
Q
S
+
ILIM/M
DRIVER
_
OVR_I
1
DRVON
-
C
Q
- FB'
+
OVR_I
RST
LX
DRVON
+
REF
D0
Ref
Block
One-Shot
=100ns
UVLO
TSD
ILIM/M
C
Zero_X
PGND
BLANK
D1
GND
-
TOFF =
KOFF/VOUT
300mV
OVR_I
VOUT
DRVON
-
+
VIN
BLON
+
-
C
BLANK
UVLO
BLANK = Tblank(=100ns) or Toff = Koff/Vout
Date: 5/25/04
SP6651A High Efficiency 800mA Synchronous Buck Regulator
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© Copyright 2004 Sipex Corporation
TYPICAL PERFORMANCE CHARACTERISTICS
100
100
95
95
90
90
Efficiency (%)
Efficiency (%)
Refer to the typical application schematic, TAMB= +27°C
85
80
75
Vi=3.6V
Vi=3.9V
Vi=4.2V
Vi=5.0V
70
65
60
0.
1.0
10.0
100.0
85
80
75
70
Vi=3.6V
Vi=3.9V
Vi=4.2V
Vi=5.0V
65
60
0.1
1000.0
1.0
10.0
ILoad (mA)
1000.0
Figure 2. Efficiency vs Load, VOUT = 1.5V
Figure 1. Efficiency vs Load, VOUT = 3.3V
3.40
1.55
Vi=3.6V
Vi=3.9V
Vi=4.2V
Vi=5.0V
3.35
Vi=3.6V
Vi=3.9V
Vi=4.2V
Vi=5.0V
1.53
1.51
Vout (V)
Vout (V)
100.0
ILoad (mA)
3.30
3.25
1.49
1.47
1.45
3.20
0
200
400
600
ILoad (mA)
800
0
1000
200
400
600
50
500
Tamb = 85°C
Tamb = 25°C
Tamb = -40°C
Tamb = 85°C
Tamb = 25°C
Tamb = -40°C
40
300
Iin (µA)
Iin (uA)
400
30
20
200
10
100
3.3
3.6
Vin (V)
3.9
0
3.0
4.2
Figure 5. No Load Battery Current, VOUT=3.3V
Date: 5/25/04
1000
Figure 4. Line/Load Rejection, VOUT = 1.5V
Figure 3. Line/Load Rejection, VOUT = 3.3V
0
3.0
800
ILoad (mA)
3.3
3.6
Vin (V)
3.9
4.2
Figure 6. No Load Battery Current, VOUT=1.5V
SP6651A High Efficiency 800mA Synchronous Buck Regulator
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© Copyright 2004 Sipex Corporation
TYPICAL PERFORMANCE CHARACTERISTICS: Continued
3.5
3.5
3.0
3.0
2.5
2.5
Kon (V*usec)
Kon (V*usec)
Refer to the typical application schematic, TAMB= +27°C
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0.0
3.6
0.5
3.9
4.2
4.5
4.8
5.1
0.0
3.0
5.4
Vin (V)
3.5
3.5
3.0
3.0
2.5
2.5
2.0
1.5
0.5
0.5
4.2
4.5
4.8
5.1
3.0
5.4
3.3
3.6
3.9
4.2
4.5
4.8
5.1
5.4
Figure 10. KOFF vs VIN, VOUT=1.5V
700.0
600.0
600.0
500.0
500.0
Frequency (KHz)
700.0
400.0
300.0
200.0
400.0
300.0
200.0
Vout = 3.3V
Measured
Vout = 3.3V
Calculated
100.0
Vout = 1.5V
Measured
Vout = 1.5V
Calculated
100.0
0.0
4.0
4.5
0.0
5.0
3.4
Vin (V)
3.8
4.2
4.6
5.0
Vin (V)
Figure 11. Ripple Frequency vs. VIN, IOUT=600mA,
VOUT=3.3V
Date: 5/25/04
5.1
Vin (V)
Figure 9. KOFF vs VIN, VOUT=3.3V
3.5
4.8
0.0
5.4
Vin (V)
Frequency (KHz)
4.2 4.5
Vin (V)
1.5
1.0
3.9
3.9
2.0
1.0
0.0
3.6
3.6
Figure 8. KON vs VIN, VOUT=1.5V
Koff (V*usec)
Koff (V*usec)
Figure 7. KON vs VIN, VOUT=3.3V
3.3
Figure 12. Ripple Frequency vs. VIN, IOUT=600mA,
VOUT=1.5V
SP6651A High Efficiency 800mA Synchronous Buck Regulator
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© Copyright 2004 Sipex Corporation
TYPICAL PERFORMANCE CHARACTERISTICS: Continued
Refer to the typical application schematic, TAMB= +27°C
CH.1=VIN
2.5V/div
CH.1=VIN
2.5V/div
CH.2=VOUT
2.0V/div
CH.2=VOUT
5.0V/div
CH.4=IIN
0.5A/div
CH.4=IIN
0.5A/div
Figure 14. VIN Start up, IOUT=0.6A, VOUT=1.5V
Figure 13. VIN Start up, IOUT=0.6A, VOUT=3.3V
CH.2=VOUT
50mV/div. AC
CH.2=VOUT
50mV/div. AC
CH.4=IIN
0.5A/div
CH.4=IOUT
0.5A/div
Figure 15. Load Step, IOUT=0.4A to 0.8A, VOUT=3.3V
Figure 16. Load Step, IOUT=0.4A to 0.8A, VOUT=1.5V
CH.1=VSHDN
10V/div.
CH.1=VSHDN
10V/div.
CH.2=VOUT
1V/div. AC
CH.2=VOUT
2V/div. AC
CH.4=ILx
0.5A/div
CH.4=ILx
0.5A/div
Figure 17. Start up from SHDN, IOUT=0.6A, VOUT=3.3V
Date: 5/25/04
Figure 18. Start up from SHDN, IOUT=0.6A, VOUT=1.5V
SP6651A High Efficiency 800mA Synchronous Buck Regulator
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© Copyright 2004 Sipex Corporation
THEORY OF OPERATION
The SP6651A is a high efficiency synchronous
buck regulator with an input voltage range of
+2.7V to +5.5Vand an output that is adjustable
between +1.0V and VIN. The SP6651A features
a unique on-time control loop that runs in discontinuous conduction mode (DCM) or continuous conduction mode (CCM) using synchronous rectification. Other features include
over-temperature shutdown, over-current protection, digitally controlled enable and undervoltage lockout, a battery low indicator, and an
external feedback pin.
RAMP: CCM OPERATION
DRVON
I(L1)
REF, FB
VOS
FB’
The SP6651A operates with a light load quiescent current of 20µA using a 0.3Ω PMOS main
switch and a 0.3Ω NMOS synchronous switch.
It operates with excellent efficiency across the
entire load range, making it an ideal solution for
battery powered applications and low current
step-down conversions. The part smoothly transitions into a 100% duty cycle under heavy load/
low input voltage conditions.
REF’
RAMP: DCM OPERATION
DRVON
I(L1)
On-Time Control - Charge Phase
FB’
The SP6651A uses a precision comparator and
a minimum on-time to regulate the output voltage and control the inductor current under normal load conditions. As the feedback pin drops
below the regulation point, the loop comparator
output goes high and closes the main switch.
The minimum on-timer is triggered, setting a
logic high for the duration defined by:
TON =
REF’
ramp voltage (VRAMP in the functional diagram)
is added to FB and this creates the FB's signal.
This FB signal is applied to the negative terminal of the loop comparator. To the positive
terminal of the loop comparator is applied the
REF voltage of 0.8V plus an offset voltage Vos
to compensate for the DC level of VRAMP applied to the negative terminal. The result is an
internal ramp with enough negative going offset
(approximately 50mV) to trip the loop comparator whenever FB falls below regulation.
KON
VIN - VOUT
where:
KON = 2.25V*µsec constant
VIN = VIN pin voltage
VOUT = VOUT pin voltage
To accommodate the use of ceramic and other
low ESR capacitors, an open loop ramp is added
to the feedback signal to mimic the inductor
current ripple. The following waveforms describe the ideal ramp operation in both CCM and
DCM operation.
The output of the loop comparator, a rising
VOLOW, causes a SET if BLANK = 0 and
OVR_I = 0. This starts inductor charging
(DRVON = 1) and starts the minimum on-timer.
The minimum on-timer times out and indicates
DRVON can be reset if the voltage loop is
satisfied. If VOUT is still below the regulation
In either CCM or DCM, the negative going
Date: 5/25/04
REF, FB
VOS
SP6651A High Efficiency 800mA Synchronous Buck Regulator
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© Copyright 2004 Sipex Corporation
THEORY OF OPERATION : Continued
point RESET is held low until VOUT is above
regulation. Once RESET occurs TON minimum
is reset, and the TOFF one-shot is triggered to
blank the loop comparator from starting a new
charge cycle for a minimum period. This blanking period occurs during the noisy LX transition
to discharge, where spurious comparator states
may occur. For TOFF > TBLANK the loop is in a
discharge or wait state until the loop comparator
starts the next charge cycle by DRVON going
high.
where:
If an over current occurs during charge the loop
is interrupted and DRVON is RESET. The offtime one-shot pulse width is widened to TOFF =
KOFF / VOUT, which holds the loop in discharge
for that time. At the end of the off-time the loop
is released and controlled by VOLOW. In this
manner maximum inductor current is controlled
on a cycle-by-cycle basis. An assertion of UVLO
(undervoltage lockout) or TSD (thermal shutdown) holds the loop in no-charge until the fault
has ended.
For most applications, the inductor current ripple
controlled by the SP6651A is constant regardless of input and output voltage. Because the
output voltage ripple is equal to:
L = Inductor value
IOUT = Load current
RCH = PMOS on resistance, 0.3Ω typ.
If the IOUT * RCH term is negligible compared
with (VIN - VOUT), the above equation simplifies
to:
ILR ≈
where:
RESR = ESR of the output capacitor
the output ripple of the SP6651A regulator is
independent of the input and output voltages.
For battery powered applications, where the
battery voltage changes significantly, the
SP6651A provides constant output voltage ripple
through-out the battery lifetime. This greatly
simplifies the LC filter design.
The discharge phase follows with the high side
PMOS switch opening and the low side NMOS
switch closing to provide a discharge path for
the inductor current. The decreasing inductor
current and the load current cause the output
voltage to drop. Under normal load conditions
when the inductor current is below the programmed limit, the off-time will continue until
the output voltage falls below the regulation
threshold, which initiates a new charge cycle via
the loop comparator.
The maximum loop frequency in CCM is defined by the equation:
FLP ≈
L
Date: 5/25/04
*
(VIN - VOUT) * (VOUT + IOUT * RDC)
KON * [VIN + IOUT * (RDC - RCH)]
where:
FLP = CCM loop frequency
RDC = NMOS on resistance, 0.3Ω typ.
The inductor current “floats” in continuous conduction mode. During this mode the inductor
peak current is below the programmed limit and
the valley current is above zero. This is to satisfy
load currents that are greater than half the minimum current ripple. The current ripple, ILR, is
defined by the equation:
KON
L
VOUT (ripple) = ILR * RESR
On-Time Control - Discharge Phase
ILR ≈
KON
Ignoring conduction losses simplifies the loop
frequency to:
FLP ≈
1
KON
*
VOUT
VIN
* (VIN - VOUT)
AND’ing the loop comparator and the on-timer
reduces the switching frequency for load currents below half the inductor ripple current. This
increases light load efficiency. The minimum
on-time insures that the inductor current ripple
VIN - VOUT - IOUT * RCH
VIN - VOUT
SP6651A High Efficiency 800mA Synchronous Buck Regulator
8
© Copyright 2004 Sipex Corporation
THEORY OF OPERATION: Continued
drop of the PMOS passing the inductor current
with a second voltage drop representing the
maximum allowable inductor current. As the
two voltages become equal, the over-current
comparator triggers a minimum off-time one
shot. The off-time one shot forces the loop into
the discharge phase for a minimum TOFF time
causing the inductor current to decrease. At the
end of the off-time, loop control is handed back
to the AND’d on-time signal. If the output
voltage is still low, charging begins until the
output is in regulation or the current limit has
been reached again. During startup and overload conditions, the converter behaves like a
current source at the programmed limit minus
half the current ripple. The minimum TOFF is
controlled by the equation:
is a minimum of KON/L, more than the load
current demands. The converter goes in to a
standard pulse frequency modulation (PFM)
mode where the switching frequency is proportional to the load current.
Low Dropout and Load Transient Operation
AND’ing the loop comparator also increases the
duty ratio past the ideal D= VOUT /VIN up to and
including 100%. Under a light to heavy load
transient, the loop comparator will hold the
main switch on longer than the minimum on
timer until the output is brought back into regulation.
Also, as the input voltage supply drops down
close to the output voltage, the main MOSFET
resistance loss will dictate a much higher duty
ratio to regulate the output. Eventually as the
input voltage drops low enough, the output
voltage will follow, causing the loop comparator to hold the converter at 100% duty cycle.
TOFF (MIN) =
VOUT
Under-Voltage Lockout
This mode is critical in extending battery life
when the output voltage is at or above the
minimum usable input voltage. The dropout
voltage is the minimum (VIN -VOUT) below
which the output regulation cannot be maintained. The dropout voltage of SP6651A is equal
to IL* (0.3Ω+ RL1) where 0.3Ω is the typical
RDS(ON) of the P-Channel MOSFET and RL is
the DC resistance of the inductor.
The SP6651A is equipped with a programmable
under-voltage lockout to protect the input battery source from excessive currents when substantially discharged. When the input supply is
below the UVLO threshold both power switches
are open to prevent inductor current from flowing. The three levels of falling input voltage
UVLO threshold are shown in Table 1, with a
typical hysteresis of 120mV to prevent chattering due to the impedance of the input source.
During UVLO, BLON is forced low.
The SP6651A has been designed to operate in
dropout with a light load Iq of only 80µA. The
on-time control circuit seamlessly operates the
converter between CCM, DCM, and low dropout modes without the need for compensation.
The converter’s transient response is quick since
there is no compensated error amplifier in the loop.
Under-Current Detection
The synchronous rectifier is comprised of an
inductor discharge switch, a voltage comparator, and a driver latch. During the off-time,
positive inductor current flows into the PGND
pin 9 through the low side NMOS switch to LX
pin 10, through the inductor and the output
capacitor, and back to pin 9. The comparator
monitors the voltage drop across the discharge
NMOS. As the inductor current approaches zero,
the channel voltage sign goes from negative to
positive, causing the comparator to trigger the
Inductor Over-Current Protection
To reduce the light load dropout Iq, the SP6651A
over-current system is only enabled when IL1 >
400mA. The inductor over-current protection
circuitry is programmed to limit the peak inductor current to 1.25A. This is done during the ontime by comparing the source to drain voltage
Date: 5/25/04
KOFF
SP6651A High Efficiency 800mA Synchronous Buck Regulator
9
© Copyright 2004 Sipex Corporation
THEORY OF OPERATION: Continued
driver latch and open the switch to prevent
inductor current reversal. This circuit along
with the on-timer puts the converter into PFM
mode and improves light load efficiency when
the load current is less than half the inductor
ripple current defined by KON/L.
circuitry to re-establish itself. Power conversion
begins with the assertion of the internal reference ready signal which occurs approximately
150µs after the enable signal is received.
Battery Low Indicator
The BLON function is a differential measurement of (VIN -VOUT) which causes the open
drain NMOS on pin 3 to sink current to ground
when (VIN -VOUT) < 300mV. Tying a resistor
from pin 3 to VIN or VOUT creates a logic level
battery low indicator. A low bandwidth comparator and 3% hysteresis filter the input voltage
ripple to prevent noisy transitions at the thresh
old. BLON is forced Low when in UVLO.
Thermal Shutdown
The converter will open both power switches if
the die junction temperature rises above 140°C.
The die must cool down below 126°C before the
regulator is re-enabled. This feature protects the
SP6651A and surrounding circuitry from excessive power dissipation due to fault conditions.
Shutdown/Enable Control
External Feedback Pin
The D0, D1 pins 4,5 of the device are logic level
control pins that according to Table 1 shut down
the converter when both are a logic low, or
enables the converter when either are a logic
high. When the converter is shut down, the
power switches are opened and all circuit biasing is extinguished leaving only junction leakage currents on supply pins 1 and 2. After pins
4 or 5 are brought high to enable the converter,
there is a turn on delay to allow the regulator
The FB pin 6 is compared to an internal reference voltage of 0.8V to regulate the SP6651A
output. The output voltage can be externally
programmed within the range +1.0V to +5.0V
by tying a resistor from FB to ground and FB to
VOUT (pin7). See the applications section for
resistor selection information.
APPLICATION INFORMATION
and would be fairly constant for different input and
output voltages, simplifying the selection of components for the SP6651A power circuit. Other
inductor values could be selected, as shown in
Table 2 Components Selection. Using a larger
value than 10µH in an attempt to reduce output
voltage ripple would reduce inductor current ripple
and may not produce as stable an output ripple.
For larger inductors with the SP6651A, which
has a peak inductor current of 1.25A, most
15µH or 22µH inductors would have to be larger
physical sizes, limiting their use in small portable applications. Smaller values like 6.8µH
would more easily meet the 1.25A limit and
come in small case sizes, and the increased
Inductor Selection
The SP6651A uses a specially adapted minimum on-time control of regulation utilizing a
precision comparator and bandgap reference.
This adaptive minimum on-time control has the
advantage of setting a constant current ripple
for a given inductor size. From the operations
section it has been shown:
K
Inductor Current Ripple, ILR ≈ ON
L
For the typical SP6651A application circuit with
inductor size of 10µH, and KON of 2V*µsec, the
SP6651A current ripple would be about 200mA,
Date: 5/25/04
SP6651A High Efficiency 800mA Synchronous Buck Regulator
10
© Copyright 2004 Sipex Corporation
APPLICATION INFORMATION: Continued
inductor current ripple of almost 300mA would
produce very stable regulation and fast load
transient response at the expense of slightly
reduced efficiency.
For the 22µF POSCAP with 0.04Ω ESR, and a
10µH inductor yielding 200mA inductor current
ripple ILR, the VOUT ripple would be 8mVpp.
Since 8mV is a very small signal level, the actual
value would probably be larger due to noise and
layout issues, but this illustrates that the SP6651A
output ripple can be very low indeed. To improve
stability, a small ceramic capacitor, CF = 22pF
should be paralleled with the feedback voltage
divider RF, as shown on the typical application
schematic on page 1. Another function of the
output capacitance is to hold up the output voltage
during the load transients and prevent excessive
overshoot and undershoot. The typical performance characteristics curves show very good load
step transient response for the SP6651A with the
recommended output capacitance of 22µF ceramic.
Other inductor parameters are important: the inductor current rating and the DC resistance. When
the current through the inductor reaches the level
of ISAT, the inductance drops to 70% of the
nominal value. This non-linear change can cause
stability problems or excessive fluctuation in inductor current ripple. To avoid this, the inductor
should be selected with saturation current at least
equal to the maximum output current of the converter plus half the inductor current ripple. To
provide the best performance in dynamic conditions such as start-up and load transients, inductors
should be chosen with saturation current close to
the SP6651A inductor current limit of 1.25A.
The input capacitor will reduce the peak current
drawn from the battery, improve efficiency and
significantly reduce high frequency noises induced by a switching power supply. The typical
input capacitor for the SP6651A is 22µF ceramic,
POSCAP or Aluminum Polymer. These capacitors will provide good high frequency bypassing
and their low ESR will reduce resistive losses for
higher efficiency. An RC filter is recommended
for the VIN pin 2 to effectively reduce the noise for
the ICs analog supply rail which powers sensitive
circuits. This time constant needs to be at least 5
times greater than the switching period, which is
calculated as 1/FLP during the CCM mode. The
typical application schematic uses the values of
RVIN = 10Ω and CVIN = 1µF to meet these requirements.
DC resistance, another important inductor characteristic, directly affects the efficiency of the converter, so inductors with minimum DC resistance
should be chosen for high efficiency designs.
Recommended inductors with low DC resistance
are listed in table 2. Preferred inductors for on
board power supplies with the SP6651A are magnetically shielded types to minimize radiated magnetic field emissions.
Capacitor Selection
The SP6651A has been designed to work with
very low ESR output capacitors (listed in Table 2
Component Selection) which for the typical application circuit are 22µF ceramic, POSCAP or Aluminum Polymer. These capacitors combine small
size, low ESR and good value. To regulate the
output with low ESR capacitors of 0.01Ω or less,
an internal ramp voltage VRAMP has been added to
the FB signal to reliably trip the loop comparator
(as described in the Operations section).
Output ripple for a buck regulator is determined
mostly by output capacitor ESR, which for the
SP6651A with a constant inductor current ripple
can be expressed as:
VOUT (ripple) = ILR * RESR
Date: 5/25/04
SP6651A High Efficiency 800mA Synchronous Buck Regulator
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© Copyright 2004 Sipex Corporation
APPLICATION INFORMATION: Continued
INDUCTORS SURFACE MOUNT
Inductor Specification
Inductance
(µH)
Manufacturer/Part No.
Series R Ω
ISAT (A)
Size
LxW(mm) Ht. (mm)
Inductor Type
Manufacturer
Website
10
Sumida CDRH5D28-100
0.048
1.30
5.7 x 5.5
3.0
Shielded Ferrite Core
sumida.com
10
TDK RLF5018T-100MR94
0.056
0.94
5.6 x 5.2
2.0
Shielded Ferrite Core
tdk.com
10
Coilcraft DO1608C-103
0.160
1.10
6.6 x 4.5
2.9
Unshielded Ferrite Core coilcraft.com
10
Coilcraft LPO6013-103
0.300
0.70
6.0 x 5.4
1.3
Unshielded Ferrite Core coilcraft.com
6.8
Sumida CDRH5D28-6R8
0.081
1.12
4.7 x 4.5
3.0
Shielded Ferrite Core
sumida.com
6.8
TDK RLF5018T-6R8M1R1
0.47
1.10
5.6 x 5.2
2.0
Shielded Ferrite Core
tdk.com
6.8
Coilcraft DO1608C-682
0.130
1.20
6.6 x 4.5
2.9
Unshielded Ferrite Core coilcraft.com
6.8
Coilcraft LPO6013-103
0.200
0.60
6.0 x 5.4
1.3
Unshielded Ferrite Core coilcraft.com
CAPACITORS - SURFACE MOUNT
Capacitor Specification
Capacitance
(µF)
Manufacturer/Part No.
ESR RippleCurrent
Size
Ω (max) (A) @ 45°C LxW(mm) Ht. (mm)
Voltage
(V)
Capacitor Type
Manufacturer
Website
22
TDK C3216X5R0J226M
0.002
3.00
3.2 x 1.6
1.6
6.3
X5R Ceramic
tdk.com
22
SANYO 6APA22M
0.040
1.90
7.3 x 4.3
2.0
6.3
POSCAP
sanyovideo.com
47
TDK C3225X5R0J46M
0.002
4.00
3.2 x 1.6
1.6
6.3
X5R Ceramic
tdk.com
47
SANYO 6TPA47M
0.040
1.90
6.0 x 3.2
2.8
6.3
POSCAP
sanyovideo.com
Note: Components highlighted in bold are those used on the SP6651A Evaluation Board.
Table 2 Component Selection
current ripple, (for the typical 10µH inductor
application on 100mA is half the 200mA inductor current ripple), the output ripple frequency
will be fairly constant. From the operations
section, this maximum loop frequency in continuous conduction mode is:
Output Voltage Program
The output voltage is programmed by the external
divider, as shown in the typical application circuit
on page 1. First pick a value for RI that is no larger
than 300K. Too large a value of RI will reduce the
AC voltage seen by the loop comparator since the
internal FB pin capacitance can form a low pass
filter with RF in parallel with RI. The formula for
RF with a given RI and output voltage is:
RF = (
FLP ≈
1
*
KON
VOUT
*
(VIN - VOUT)
VIN
Data for loop frequency, as measured from
output voltage ripple frequency, can be found in
the typical performance curves.
VOUT
- 1 ) • RI
0.8V
Output Voltage Ripple Frequency
Layout Considerations
An important consideration in a power supply
application is the frequency value of the output
ripple. Given the control technique of the
SP6651A (as described in the operations section), the frequency of the output ripple will
vary when in light to moderate load in the
discontinuous or PFM mode. For moderate to
heavy loads greater than about 100mA inductor
Proper layout of the power and control circuits is
necessary in a switching power supply to obtain
good output regulation with stability and a minimum of output noise. The SP6651A application
circuit can be made very small and reside close to
the IC for best performance and solution size, as
long as some layout techniques are taken into
consideration. To avoid excessive interference
Date: 5/25/04
SP6651A High Efficiency 800mA Synchronous Buck Regulator
12
© Copyright 2004 Sipex Corporation
APPLICATION INFORMATION: Continued
between the SP6651A high frequency converter
and the other active components on the board,
some rules should be followed. Refer to the typical
application schematic on page 1 and the sample
PCB layout shown in the following figures to
illustrate how to layout a SP6651A power supply.
SP6651A pin 9 GND is connected to pin 10
PGND.
Power loops on the input and output of the converter should be laid out with the shortest and
widest traces possible. The longer and narrower
the trace, the higher the resistance and inductance
it will have. The length of traces in series with the
capacitors increases its ESR and ESL and reduces
their effectiveness at high frequencies. Therefore,
put the 1µF bypass capacitor as close to the VIN and
GND pins of the converter as possible, the 22µF
CIN close to the PVIN pin and the 22µF output
capacitor as close to the inductor as possible. The
external voltage feedback network RF, RI and
feedforward capacitor CF should be placed very
close to the FB pin. Any noise traces like the LX
pin should be kept away from the voltage feedback
network and separated from it by using power
ground copper to minimize EMI.
Avoid injecting noise into the sensitive part of
circuit via the ground plane. Input and output
capacitors conduct high frequency current through
the ground plane. Separate the control and power
grounds and connect them together at a single
point. Power ground plane is shown in the figure
titled PCB top sample layout and connects the
ground of the COUT capacitor to the ground of the
CIN capacitor and then to the PGND pin 10. The
control ground plane connects from pin 9 GND to
ground of the CVIN capacitor and the RI ground
return of the feedback resistor. These two separate
control and power ground planes come together in
the figure titled PCB top sample layout where
Figure 19. SP6651A PCB Component Sample Layout
Figure 20. SP6651A PCB Top Sample Layout
Figure 21. SP6651A PCB Bottom Sample Layout
Date: 5/25/04
SP6651A High Efficiency 800mA Synchronous Buck Regulator
13
© Copyright 2004 Sipex Corporation
PACKAGE: 10 PIN MSOP
D
e1
Ø1
E/2
R1
R
E1
E
L2
Ø1
Seating Plane
L
Gauge Plane
Ø
00
L1
1
2
e
Pin #1 indentifier must be indicated within this shaded area (D/2 * E1/2)
10-PIN MSOP
JEDEC MO-187
(BA) Variation
A
Dimensions in (mm)
MIN
-
0.00
A1
1.10
-
0.75
b
0.17
-
0.27
c
0.08
-
0.23
0.85
B
0.15
A2
D
B
NOM MAX
-
0.95
(b)
WITH PLATING
3.00 BSC
E
4.90 BSC
E1
3.00 BSC
e
0.50 BSC
e1
c
2.00 BSC
L
0.4
0.60
0.80
L1
0.95 REF
L2
0.25 BSC
N
BASE METAL
Section B-B
10
R
0.07
-
-
R1
0.07
-
-
Ø
0º
Ø1
5º
-
A2
A
8º
b
15º
A1
10-PIN MSOP
1
Date: 5/25/04
SP6651A High Efficiency 800mA Synchronous Buck Regulator
14
© Copyright 2004 Sipex Corporation
PACKAGE: 10 PIN DFN
Bottom View
Top View
D
e
b
D/2
1
2
E/2
E2
E
K
L
D2
Pin 1 identifier to be located within this shaded area.
Terminal #1 Index Area (D/2 * E/2)
10 Pin DFN
DIMENSIONS
in
(mm)
(JEDEC MO-229,
VEED-5 VARIATION)
SYMBOL
A
A1
A3
b
D
D2
e
E
E2
K
L
Date: 5/25/04
MIN NOM MAX
0.80
0
0.90
1.00
0.02 0.05
0.20 REF
A
0.18 0.25 0.30
3.00 BSC
2.20
2.70
0.50 PITCH
3.00 BSC
1.40
1.75
0.20
0.30 0.40 0.50
A1
A3
Side View
10 PIN DFN
SP6651A High Efficiency 800mA Synchronous Buck Regulator
15
© Copyright 2004 Sipex Corporation
ORDERING INFORMATION
Part Number
Top Mark
Operating Temperature Range
Package Type
SP6651AEU..............6651AEU....................... -40°C to +85°C ................................................... 10 Pin MSOP
SP6651AEU/TR........6651AEU ............ ........... -40°C to +85°C .................................................. 10 Pin MSOP
SP6651AER.............6651AER......................... -40°C to +85°C ..................................................... 10 Pin DFN
SP6651AER/TR.......6651AER......................... -40°C to +85°C ..................................................... 10 Pin DFN
Available in lead free packaging. To order add "-L" suffix to part number.
Example: SP6651AEU/TR = standard; SP6651AEU-L/TR = lead free
/TR = Tape and Reel
Pack quantity is 2500 for MSOP and 3,000 for DFN.
Corporation
ANALOG EXCELLENCE
Sipex Corporation
Headquarters and
Sales Office
233 South Hillview Drive
Milpitas, CA 95035
TEL: (408) 934-7500
FAX: (408) 935-7600
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the
application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
Date: 5/25/04
SP6651A High Efficiency 800mA Synchronous Buck Regulator
16
© Copyright 2004 Sipex Corporation
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