SP6831EK

® SP6830/6831 Low Power Voltage Inverters With Shutdown FEATURES s 99.9% Voltage Conversion Efficiency s +1.15V to +5.3V Input Voltage Range s Inverts Input Supply Voltage s 70µA Supply Current for the SP6830 s 200µA Supply Current for the SP6831 s 35kHz Operating Frequency for the SP6830 s 120kHz Operating Frequency for the SP6831 s 95% over most of its loadcurrent range) with a low quiescent current. THEORY OF OPERATION The SP6830/6831 devices should theoretically produce an inverted input voltage. In real world applications, there are small voltage drops at the output that reduce efficiency. The circuit of an ideal voltage inverter can be found in Figure 18. The voltage inverters require two external capacitors to store the charge. A description of the two phases follows: Phase 1 In the first phase of the clock cycle, switches S2 and S4 are opened and S1 and S3 closed. This connects the flying capacitor, C1, from VIN to ground. C1 charges up to the input voltage applied at VIN. Phase 2 In the second phase of the clock cycle, switches S1 and S3 are opened and S2 and S4 are closed. This connects the flying capacitor, C1, in parallel with the output capacitor, C2. The charge stored in C1 is now transferred to C2. Simultaneously, the negative side of C2 is connected to VOUT and the positive side is connected to ground. With the voltage across C2 smaller than the voltage across C1, the charge flows from C1 to C2 until the voltage at the VOUT equals -VIN. VOUT = -VIN VIN S1 C1 S3 S2 C2 VOUT S4 Figure 18. Circuit for an Ideal Voltage Inverter Charge-Pump Output The output of the SP6830/6831 devices is not regulated and therefore is dependent on the output resistance and the amount of load current. As the load current increases, losses may slightly increase at the output and the voltage may become slightly more positive. The loss at the negative output, VLOSS, equals the current draw, IOUT, from VOUT times the negative converter's source resistance, RS: VLOSS = IOUT x RS. The actual inverted output voltage at VOUT will equal the inverted voltage difference of VIN and VLOSS: VOUT = -(VIN - VLOSS). Efficiency Theoretically, the total power loss of a switched capacitor voltage converter can be summed up as follows: ∑PLOSS = PINT + PCAP + PCONV, where PLOSS is the total power loss, PINT is the total internal loss in the IC including any losses in the MOSFET switches, PCAP is the resistive loss of the charge pump capacitors, and PCONV is the total Rev. 9-22-00 SP6830/6831 Low Power Voltage Inverters With Shutdown © Copyright 2000 Sipex Corporation 9 conversion loss during charge transfer between the flying and output capacitors. These are the three theoretical factors that may effect the power efficiency of the SP6830/6831 devices in designs. Any internal losses come from the IC's on board circuitry. Losses in the IC can be induced by the input voltage, the frequency of the oscillator, and the ambient temperature. The most influential internal loss in the IC may be found in the poweron resistance of the internal MOSFET switches. Any of the losses with the charge pump capacitors will be induced by the capacitor's ESR. The affects of the ESR losses and the output resistance can be found in the following equation: IOUT2 x ROUT = PCAP + PCONV and ROUT ≈ 4 x (2 x RSWITCHES + ESRC1) + 1 ESRC2 + fOSC x C1 , where IOUT it the output current, ROUT is the circuit's output resistance, RSWITCHES is the internal resistance of the MOSFET switches, ESRC1 and ESRC2 are the ESR of their respective capacitors, and fOSC is the oscillator frequency. This term with fOSC is derived from an ideal switchedcapacitor circuit as seen in Figure 19. Any losses due to the conversion process will happen during the charge transfer between the flying capacitor, C1, and the output capacitor, C2, when there is a voltage difference between them. PCONV can be determined by the following equation: PCONV = fOSC x [ 1/2 x C1 x (VIN2 - VOUT2) + 1 where POUT = VOUT x IOUT and PIN = VIN x IIN where POUT is the power output, VOUT is the output voltage, IOUT is the output current, PIN is the power from the supply driving the SP6830/ 6831 devices, VIN is the supply input voltage, and IIN is the supply input current. Ideal Efficiency The ideal efficiency is not the true power efficiency because it does not involve the input power which includes the input current losses in the charge pump. The ideal efficiency can be determined with the following equation: Efficiency (ideal) = POUT x 100% , POUT(IDEAL) where POUT(IDEAL) = -VIN x -VIN , RL f V+ VOUT C1 C2 RL /2 x C2 x (VRIPPLE2 - 2VOUTVRIPPLE) ]. V+ Requivalent VOUT Actual Efficiency To determine the actual efficiency of the SP6830/ 6831 device operation, a designer can use the following equation: Requivalent = 1 f x C1 C2 RL Efficiency (actual) = POUT x 100% , PIN Figure 19. Equivalent Circuit for an Ideal Switched Capacitor Rev. 9-22-00 SP6830/6831 Low Power Voltage Inverters With Shutdown © Copyright 2000 Sipex Corporation 10 and POUT is the the power output. Both efficiencies are provided to designers for comparison. APPLICATION INFORMATION For the following applications, C1 = C2 = C3 = 3.3µF for the SP6830 and C1 = C2 = C3 = 1.0µF for the SP6831. Capacitor Selection Low ESR capacitors are needed to obtain low output resistance. Refer to Table 1 for some suggested low ESR capacitors. The output resistance of the SP6830/6831 devices is a function of the ESR of C1 and C2. This output resistance can be determined by the equation previously provided in the Efficiency section: ROUT ≈ 4 x (2 x RSWITCHES + ESRC1) + 1 ESRC2 + fOSC x C1 , where ROUT is the circuit's output resistance, RSWITCHES is the internal resistance of the MOSFET switches, ESRC1 and ESRC2 are the ESR of their respective capacitors, and fOSC is the oscillator frequency. This term with fOSC is derived from an ideal switched-capacitor circuit as seen in Figure 19. Minimizing the ESR of C1 and C2 will minimize the total output resistance and will improve the efficiency. Flying Capacitor Decreasing flying capacitor, C1, values will increase the output resistance of the SP6830/ 6831 devices while increasing C1 will reduce the output resistance. There is a point where increasing C1 will have a negligible effect on the output resistance due to the the domination of the output resistance by the internal MOSFET switch resistance and the total capacitor ESR. Output Capacitor Increasing output capacitor, C2, values will decrease the output ripple voltage. Reducing the ESR of C2 will reduce both output ripple voltage and output resistance. If higher output ripple can be tolerated in designs, smaller capacitance values for C2 should be used with light loads. The following equation can be used to calculate the peak-to-peak ripple voltage: VRIPPLE = 2 x IOUT x ESRC2 + IOUT fOSC x C2 . Input Bypass Capacitor The bypass capacitor at the input voltage will reduce AC impedance and the impact of any of the SP6830/6831 device's switching noise. It is recommended that for heavy loads a bypass capacitor approximately equal to the flying capacitor, C1, be used. For light loads, the value of the bypass capacitor can be reduced. SIPEX PART NUMBER SP6830 SP6830 SP6830 SP6831 SP6831 SP6831 MANUFACTURER/ TELEPHONE # KEMET / 864-963-6300 SPRAGUE / 207-324-4140 TDK / 847-803-6100 AVX / 843-448-9411 KEMET/ 864-963-6300 TDK / 847-803-6100 PART NUMBER T494B335*020 595D335X0035 C3216X5R1A335K 0805ZC105K C0805C105KRAC C2012X5R1A105K CAPACITANCE / VOLTAGE 3.3µF / 20V 3.3µF / 35V 3.3µF / 10V 1µF / 10V 1µF / 10V 1µF / 10V MAX ESR @ 100kHz 1.5Ω 2.0Ω 0.04Ω 0.04Ω 0.05Ω 0.05Ω CAPACITOR SIZE/TYPE Case B / Tantalum Case C / Tantalum 1206 / X5R 0805 / X7R 0805 / X7R 0805 / X5R Table 1. Suggested Low ESR Surface Mount Capacitors Rev. 9-22-00 SP6830/6831 Low Power Voltage Inverters With Shutdown © Copyright 2000 Sipex Corporation 11 +VIN IN 2 C1+ 2 C1+ IN 2 C1+ IN RTOT 6 4 C1 GND SP6830 SP6831 “1” 1 OUT 6 4 C1 GND SP6830 SP6831 “2” 1 OUT 6 4 C1 GND SP6830 SP6831 “n” 1 OUT C1- 3 C1- 3 C1- 3 SHDN 5 SHDN 5 SHDN 5 VOUT Shutdown Control Input VOUT = -VIN RTOT = ROUT where VOUT = output voltage, n VIN = input voltage, RTOT = total resistance of the devices connected in parallel, ROUT = the output resistance of a single device, and n = the total number of devices connected in parallel. C2 x n Figure 20. SP6830/6831 Devices Connected in Parallel to Reduce Total Output Resistance +VIN IN 2 C1+ 2 C1+ SHDN 5 GND IN 2 SHDN 5 C1+ GND IN SHDN 5 6 4 C1 GND SP6830 SP6831 “1” 5 4 SP6830 SP6831 “2” 3 4 C1 1 OUT C1 1 OUT SP6830 SP6831 “n” C1- 3 C1- 3 C1- 5 1 OUT VOUT C2 C2 C2 VOUT = -n x VIN where VOUT = output voltage, VIN = input voltage, and n = the total number of cascaded devices connected. Figure 21. SP6830/6831 Devices Cascaded to Increase Output Voltage Rev. 9-22-00 SP6830/6831 Low Power Voltage Inverters With Shutdown © Copyright 2000 Sipex Corporation 12 When loading the SP6830/6831 devices from IN to OUT, the input current remains constant (disregarding any spikes due to internal switching). Implementing a 0.1µF bypass capacitor should be sufficient. When loading the SP6830/6831 devices from OUT to GND, the current from the supply will switch from twice that of IOUT and zero amperes. Designers should implement a large bypass capacitor (C3 = C1) if the supply has a high AC impedance. Voltage Inverter A designer can find the most common application for the SP6830/6831 devices in Figure 17 as a voltage inverter. The only external components needed are 3 capacitors: the flying capacitor, C1, the output capacitor, C2, and the bypass capacitor, C3 (if necessary). This circuit is used to obtain the Typical Performance Characteristics found in Figures 2 to 16 (unless otherwise noted). Connecting in Parallel A designer can parallel a number of SP6830/ 6831 devices to reduce the output resistance for specific designs. All devices will need their own flying capacitor, C1, but a single output capacitor will serve all of the devices connected in parallel by increasing the capacitance of C2 by a factor of n where n equals the total number of devices connected. This connection can be found in Figure 20. Cascading Devices A designer can cascade SP6830/6831 devices to produce a larger inverted voltage output. Refer to Figure 21 for this circuit connection. With two cascaded devices, the unloaded output voltage is decreased by the output resistance of the first device multiplied by the quiescent current of the second device connected. The total output resistance is greatly increased when more than two devices are cascaded. Driving Excessive Loads The output should never be pulled above ground. A designer should implement a Schottky diode (1N5817) from OUT to GND when driving heavy loads where a higher supply is sourcing current into OUT. Refer to Figure 22 for this circuit connection. GND 4 SP6830 SP6831 1 OUT 1N5817 Figure 22. Protection for Heavy Loads Combining a Doubler and Inverter Circuit A designer can connect a SP6830/6831 device in a combination doubler/inverter circuit as seen in Figure 23. The doubler uses C3 and C4 while the inverter uses capacitors C1 and C2. Loading either output decreases both output voltages to GND because both the doubler and the inverter circuits use the charge pump. Designers should not allow the total current output from the doubler and the inverter to exceed 40mA. Implementing Shutdown The SP6830/6831 devices are enabled when the SHDN input pin is driven HIGH and disabled when driven LOW. This input must be tied to VIN or GND to minimize any noise effects due to the internal switching of these devices. The SHDN input cannot be driven 0.5V above VIN without the possibility of introducing significant current flows. Layout and Grounding Designers should make an effort to minimize noise by paying special attention to the circuit layout with the SP6830/6831 devices. External components should be connected in close proximity to the device and a ground plane should be implemented. This will keep electrical traces short minimizing parasitic inductance and capacitance. Rev. 9-22-00 SP6830/6831 Low Power Voltage Inverters With Shutdown © Copyright 2000 Sipex Corporation 13 C3 +VIN D1 IN 2 D1 = D2 = 1N4148 D2 VOUT1 C4 C1+ GND C1 C1Shutdown Control Input SHDN 6 4 SP6830 SP6831 3 5 1 OUT VOUT2 C2 VOUT1 = (2 x VIN) - VFD1 - VFD2 VOUT2 = -VIN where VOUT1 = positive doubled output voltage, VIN = input voltage, VFD1 = forward bias voltage across D1, VFD2 = forward bias voltage across D2, and VOUT2 = inverted output voltage. Figure 23. SP6830/6831 Device Connected in a Doubler/Inverter Combination Circuit Rev. 9-22-00 SP6830/6831 Low Power Voltage Inverters With Shutdown © Copyright 2000 Sipex Corporation 14 PACKAGE: SOT23-6 b C L e E e1 D C L A A2 A C L a 0.20 DATUM 'A' C A1 A .10 E1 L 2 SYMBOL A A1 A2 b C D E E1 L e e1 a MIN 0.90 0.00 0.90 0.25 0.09 2.80 2.60 1.50 0.35 0.95ref 1.90ref 0 O MAX 1.45 0.15 1.30 0.50 0.20 3.10 3.00 1.75 0.55 10 O Rev. 9-22-00 SP6830/6831 Low Power Voltage Inverters With Shutdown © Copyright 2000 Sipex Corporation 15 ORDERING INFORMATION Model Temperature Range Package Type SP6830EK . ............................................ -40˚C to +85˚C ............................................... SOT23-6 SP6830EK/TR ......................................... -40˚C to +85˚C ............................................... SOT23-6 SP6831EK . ............................................ -40˚C to +85˚C ............................................... SOT23-6 SP6831EK/TR ......................................... -40˚C to +85˚C ............................................... SOT23-6 Please consult the factory for pricing and availability on a Tape-On-Reel option. Corporation SIGNAL PROCESSING EXCELLENCE Sipex Corporation Headquarters and Sales Office 22 Linnell Circle Billerica, MA 01821 TEL: (978) 667-8700 FAX: (978) 670-9001 e-mail: sales@sipex.com Sales Office 233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600 Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described hereing; neither does it convey any license under its patent rights nor the rights of others. Rev. 9-22-00 SP6830/6831 Low Power Voltage Inverters With Shutdown © Copyright 2000 Sipex Corporation 16