SP6832

® SP6832 High Speed, High Efficiency Voltage Inverter s 99.9% Voltage Conversion Efficiency s +1.15V to +5.3V Input Voltage Range s +1.15 VIN Guaranteed Start-up s Inverts Input Supply Voltage s 700µA Quiescent Current s 25mA Output Current s 500kHz Operating Frequency s Ideal for +3.6V Lithium Ion Battery Applications s Reverse Battery Protection s 5-pin SOT23 Package s 19Ω Output Resistance s 0.1 or 0.33 µF Capacitors DESCRIPTION The SP6832 device is a CMOS Charge Pump Voltage Inverter that can be implemented in designs requiring a negative voltage from a positive source as low as 1.15V. The SP6832 device is ideal for both battery-powered and board level voltage conversion applications with a typical operating current of 700mA at a 5V supply. The SP6832 can output 25mA with a voltage drop of 500mV. These devices combine a low quiescent current with high efficiency of 85-90% over most of its load range. Applications include cell phones, PDAs, medical instruments and other portable equipment. The SP6832 is available in a space-saving 5-pin SOT23 Package. VOUT 1 VIN 2 C1- 3 SP6832 5 C1+ 4 GND SP6832DS/04 SP6832 High Speed, High Efficiency Voltage Inverter © Copyright 2000 Sipex Corporation 1 ABSOLUTE MAXIMUM RATINGS These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. VIN.....................................................................................-0.3V to +5.6V VOUT...................................................................................-5.6V to +0.3V V OUT Short Circuit to GND.................................................Indefinite IOUT...................................................................................................50mA Storage Temperature.....................................................-65˚C to +150˚C Power Dissipation per Package 5-pin SOT (derate 4.35mW/oC above +70oC).............................400mW Lead Temperature (Soldering)....................................................300oC ESD Rating...............................................2kV Human Body Model SPECIFICATIONS FOR THE SP6832 VIN = +5.0V, C1 = C2 = C3 = 0.33µF and TAMB = 25oC unless otherwise noted. The circuit found in Figure 14 was used to obtain the following typical performance characteristics (unless otherwise noted). PARAMETER Minimum Voltage Supply Voltage Supply Currrent Output Resistance Oscillator Frequency Voltage Conversion Efficiency Power Efficiency (Ideal) Power Efficiency (Actual) 300 95 MIN. 1.4 0.7 19 500 99.9 97 87 TYP. 0.86 MAX. 1.15 5.3 1.4 45 750 UNITS V mA Ω kHz % % % RL = ∞ IOUT = 5mA, Note 3 IOUT = 5mA, Note 4 CONDITIONS RL=10kΩ, TAMB=+25° C, Note 1 RL=10kΩ, TAMB=-40° C to +85° C TAMB = -40oC to +85oC, RL = ∞ IOUT = 5mA to 25mA, Note 2 NOTE 1: VOUT = -VIN +200mV NOTE 2: Capacitors are approximately 20% of the output impedance where ESR = NOTE 3: Power Efficiency (Ideal) = NOTE 4: Power Efficiency (Actual) = 1 fOSC x C VOUT x IOUT -VIN x (-VIN/RL) VOUT x IOUT VIN x IIN SP6832DS/04 SP6832 High Speed, High Efficiency Voltage Inverter © Copyright 2000 Sipex Corporation 2 PINOUT PIN ASSIGNMENTS Pin 1— VOUT — Inverting charge pump output. VOUT 1 VIN 2 C1- 3 SP6832 5 C1+ Pin 2 — VIN — Input to the positive power supply. Pin 3 — C1- — Negative terminal to the charge pump capacitor. Pin 4 — GND — Ground reference. Pin 5 — C1+ — Positive terminal to the charge pump capacitor. 4 GND TYPICAL PERFORMANCE CHARACTERISTICS VIN = +5.0V, C1 = C2 = C3 = 0.33µF and TAMB = 25oC unless otherwise noted. The circuit found in Figure 14 was used to obtain the following typical performance characteristics (unless otherwise noted). 50 45 40 35 30 25 20 15 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 (V) 30 25 ROUT (Ω) 20 15 10 5 0 -60 -40 -20 0 20 40 60 80 100 temperature OC Figure 1. Output Resistance vs. Supply Voltage with a 5mA load ROUT (Ω) Figure 2. Output Resistance vs. Temperature with a 25mA load SP6832DS/04 SP6832 High Speed, High Efficiency Voltage Inverter © Copyright 2000 Sipex Corporation 3 TYPICAL PERFORMANCE CHARACTERISTICS VIN = +5.0V, C1 = C2 = C3 = 0.33µF and TAMB = 25oC unless otherwise noted. The circuit found in Figure 14 was used to obtain the following typical performance characteristics (unless otherwise noted). 700 600 700 600 fpump (kHz) VIN (V) VIN = 5V, VOUT = -3.7V fpump (kHz) 500 400 300 200 100 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 500 400 300 200 100 0 -60 -40 -20 0 20 40 60 80 100 temperature OC Figure 3. Charge Pump Frequency vs. Supply Voltage Figure 4. Charge Pump Frequency vs. Temperature 80 70 60 50 40 30 20 10 0 0 700 Vripple (mV p-p) 600 500 400 300 200 100 0 0 VIN = 5V, VOUT = -3.7V IOUT (mA) VIN = 4.2, VOUT = -3.2 VIN = 4.2, VOUT = -3.2 VIN = 2V, VOUT = -1.5V VIN = 2V, VOUT = -1.5V 0.1 0.2 0.3 Capacitance (µF) 0.1 0.2 0.3 Capacitance (µF) Figure 5. Output Current vs. Capacitance Figure 6. Output Voltage Ripple vs. Capacitance SP6832DS/04 SP6832 High Speed, High Efficiency Voltage Inverter © Copyright 2000 Sipex Corporation 4 TYPICAL PERFORMANCE CHARACTERISTICS VIN = +5.0V, C1 = C2 = C3 = 0.33µF and TAMB = 25oC unless otherwise noted. The circuit found in Figure 14 was used to obtain the following typical performance characteristics (unless otherwise noted). 1,000 900 800 700 600 500 400 300 200 100 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VIN (V) 0 -1 -2 VIN = 2V VOUT (V) VIN = 3V VIN (µA) -3 -4 -5 -6 0 10 20 30 40 50 IOUT (mA) VIN = 5V Figure 7. Supply Current vs. Supply Voltage Figure 8. Output Voltage vs. Output Current with 0.1µF Capacitors 100 90 80 70 60 50 40 30 20 10 0 100 VIN = 5V VIN = 3V VIN = 2V 90 80 70 60 50 40 30 20 10 0 0 5 10 15 IOUT (mA) VIN = 5V Power efficiency (%) VIN = 3V Veff (%) VIN = 2V 0 5 15 10 IOUT (mA) 20 25 20 25 Figure 9. Power Efficiency vs. Output Current with 0.1µF Capacitors Figure 10. Voltage Efficiency vs. Output Current with 0.1µF Capacitors SP6832DS/04 SP6832 High Speed, High Efficiency Voltage Inverter © Copyright 2000 Sipex Corporation 5 TYPICAL PERFORMANCE CHARACTERISTICS VIN = +5.0V, C1 = C2 = C3 = 0.33µF and TAMB = 25oC unless otherwise noted. The circuit found in Figure 14 was used to obtain the following typical performance characteristics (unless otherwise noted). 100 90 80 70 60 50 40 30 20 10 0 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VIN (V) 120 100 Veff (%) 80 60 40 20 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VIN (V) Peff (%) Figure 11. Power Efficiency vs. Supply Voltage with a 5mA load Figure 12. Voltage efficiency vs. Supply Voltage without a Load with 0.1µF Capacitors VIN = 3.3V VOUT = -3.2V ILOAD = 5mA Figure 13. Output Noise and Ripple SP6832DS/04 SP6832 High Speed, High Efficiency Voltage Inverter © Copyright 2000 Sipex Corporation 6 VOUT 1 VIN RL C2 2 C1SP6832 4 5 C1+ + C3 3 GND C1 Figure 14. SP6832 in its Typical Operating Circuit as a Negative Voltage Converter; this Circuit Was Used to Obtain the Typical Performance Characteristics Found in Figures 1 Through 13 (unless otherwise noted) VOUT VIN C2 RL C1- 1 2 3 SP6832 5 C1+ 4 GND C3 C1 Figure 15. SP6832 Connected as a Voltage Inverter with the load from VOUT to VIN SP6832DS/04 SP6832 High Speed, High Efficiency Voltage Inverter © Copyright 2000 Sipex Corporation 7 DESCRIPTION The SP6832 is a CMOS Charge Pump Voltage Converter that can be used to invert a +1.15V to +5.3V input voltage. These devices are ideal for designs involving battery-powered and/or board level voltage conversion applications. The typical operating frequency of the SP6832 is 500kHz. The SP6832 has a typical operating current of 800µA. The device can output 25mA with a voltage drop of 500mV. The devices are ideal for designs using +3.3V or +3.6V lithium ion batteries such as cell phones, PDAs, medical instruments, and other portable equipment. The SP6832 combines a high efficiency with a low quiescent current. THEORY OF OPERATION The SP6832 should theoretically produce an inverted input voltage. In real world applications, there are small voltage drops at the output that reduce efficiency. The circuit of an ideal voltage inverter can be found in Figure 16. The voltage inverters require two external capacitors to store the charge. A description of the two phases follows: Phase 1 In the first phase of the clock cycle, switches S1 and S3 are opened and S2 and S4 are closed. This connects the flying capacitor, C1, from VIN to ground. C1 charges up to the input voltage applied at VIN. Phase 2 In the second phase of the clock cycle, switches S1 and S3 are opened and S2 and S4 are closed. This connects the flying capacitor, C1, in parallel with the output capacitor, C2. The charge stored in C1 is now transferred to C2. Simultaneously, the negative side of C2 is connected to VOUT and the positive side is connected to ground. With the voltage across C2 smaller than the voltage across C1, the charge flows from C1 to C2 until the voltage at the VOUT equals -VIN. VOUT = -VIN VIN S1 C1 S3 S2 C2 VOUT S4 Figure 16. Circuit for an Ideal Voltage Inverter Charge-Pump Output The output of the SP6832 is not regulated and therefore is dependent on the output resistance and the amount of load current. As the load current increases, losses may slightly increase at the output and the voltage may become slightly more positive. The loss at the negative output, VLOSS, equals the current draw, IOUT, from VOUT times the negative converter's source resistance, RS: VLOSS = IOUT x RS. The actual inverted output voltage at VOUT will equal the inverted voltage difference of VIN and VLOSS: VOUT = -(VIN - VLOSS). Efficiency Theoretically, the total power loss of a switched capacitor voltage converter can be summed up as follows: ∑PLOSS = PINT + PCAP + PCONV, where PLOSS is the total power loss, PINT is the total internal loss in the IC including any losses in the MOSFET switches, PCAP is the resistive loss of SP6832DS/04 SP6832 High Speed, High Efficiency Voltage Inverter © Copyright 2000 Sipex Corporation 8 the charge pump capacitors, and PCONV is the total conversion loss during charge transfer between the flying and output capacitors. These are the three theoretical factors that may effect the power efficiency of the SP6832 in designs. Internal losses come from the power dissipated in the IC's internal circuitry. Losses in the charge pump capacitors will be induced by the capacitors' ESR. The effects of the ESR losses and the output resistance can be found in the following equation: IOUT2 x ROUT = PCAP + PCONV and ROUT ≈ 4 x (2 x RSWITCHES + ESRC1) + 1 ESRC2 + fOSC x C1 , where IOUT is the output current, ROUT is the circuit's output resistance, RSWITCHES is the internal resistance of the MOSFET switches, ESRC1 and ESRC2 are the ESR of their respective capacitors, and fOSC is the oscillator frequency. This term with fOSC is derived from an ideal switchedcapacitor circuit as seen in Figure 17. Conversion losses will happen during the charge transfer between the flying capacitor, C1, and the output capacitor, C2, when there is a voltage difference between them. PCONV can be determined by the following equation: PCONV = fOSC x [ 1/2 x C1 x (VIN2 - VOUT2) + 1 where POUT = VOUT x IOUT and PIN = VIN x IIN where POUT is the power output, VOUT is the output voltage, IOUT is the output current, PIN is the power from the supply driving the SP6832, VIN is the supply input voltage, and IIN is the supply input current. Ideal Efficiency The ideal efficiency is not the true power efficiency because it is not calculated relative to the input power which includes the input current losses in the charge pump. The ideal efficiency can be determined with the following equation: Efficiency (IDEAL) = POUT x 100% , POUT (IDEAL) where POUT (IDEAL) = -VIN x -VIN RL , and POUT is the measured power output. Both efficiencies are provided to designers for comparison. f V+ VOUT RL /2 x C2 x (VRIPPLE2 - 2 x VOUT x VRIPPLE) ]. C1 C2 Actual Efficiency To determine the actual efficiency of the SP6832 device operation, a designer can use the following equation: Requivalent P Efficiency (ACTUAL) = OUT x 100% , PIN V+ VOUT RL Requivalent = 1 f x C1 C2 Figure 17. Equivalent Circuit for an Ideal Switched Capacitor SP6832DS/04 SP6832 High Speed, High Efficiency Voltage Inverter © Copyright 2000 Sipex Corporation 9 APPLICATION INFORMATION For the following applications, C1 = C2 = 0.1µF Capacitor Selection Low ESR capacitors are needed to obtain low output resistance. Refer to Table 1 for some suggested low ESR capacitors. The output resistance of the SP6832 is a function of the ESR of C1 and C2. This output resistance can be determined by the equation previously provided in the Efficiency section: ROUT ≈ 4 x (2 x RSWITCHES + ESRC1) + 1 ESRC2 + fOSC x C1 , where ROUT is the circuit output resistance, RSWITCHES is the internal resistance of the MOSFET switches, ESRC1 and ESRC2 are the ESR of their respective capacitors, and fOSC is the oscillator frequency. This term with fOSC is derived from an ideal switched-capacitor circuit as seen in Figure 21. Minimizing the ESR of C1 and C2 will minimize the total output resistance and will improve the efficiency. Flying Capacitor Decreasing flying capacitor, C1, values will increase the output resistance of the SP6832 while increasing C1 will reduce the output resistance. There is a point where increasing C1 will have a negligible effect on the output resistance due to the domination of the output resistance by the internal MOSFET switch resistance and the total capacitor ESR. Output Capacitor Increasing output capacitor, C2, values will decrease the output ripple voltage. Reducing the ESR of C2 will reduce both output ripple voltage and output resistance. If higher output ripple can be tolerated in designs, smaller capacitance values for C2 should be used with light loads. The following equation can be used to calculate the peak-to-peak ripple voltage: VRIPPLE = 2 x IOUT x ESRC2 + IOUT fOSC x C2 . Input Bypass Capacitor The bypass capacitor at the input pin will reduce AC impedance and the impact of any of the SP6832 devices' switching noise. It is recommended that for heavy loads a bypass capacitor approximately equal to the flying capacitor, C1, be used. For light loads, the value of the bypass capacitor can be reduced. When loading the SP6832 devices from IN to OUT, the input current remains constant (disregarding any spikes due to internal switching). Implementing a 0.1 µF bypass capacitor should be sufficient. When loading the SP6832 devices from OUT to GND, the current from the supply will flow into the input for half of the cycle and will be zero for the other half of the cycle. Designers should implement a large bypass capacitor if the supply has a high AC impedance. Negative Voltage Converter The typical operating circuit for the SP6832 devices is a negative voltage converter. Refer to Figure 14. This circuit is used to obtain the Typical Performance Characteristics found in Figures 1 to 13 (unless otherwise noted). Voltage Inverter with the Load from VOUT to VIN A designer can find the most common application for the SP6832 devices in Figure 15 as a voltage inverter. The only external components needed are 3 capacitors: the flying capacitor, C1, the output capacitor, C2, and the bypass capacitor, C3 (if necessary). Driving Excessive Loads The output should never be pulled above ground. A designer should implement a Schottky diode (1N5817) from OUT to GND when driving heavy loads where a higher supply is sourcing current into OUT. Refer to Figure 18 for this circuit connection. SP6832DS/04 SP6832 High Speed, High Efficiency Voltage Inverter © Copyright 2000 Sipex Corporation 10 GND SP6832 4 1 OUT 1N5817 Figure 18. Protection for Heavy Loads C3 +VIN D1 = D2 = 1N4148 D1 IN 2 D2 VOUT1 C4 C1+ GND C1 C1- 5 4 SP6832 3 1 OUT VOUT2 C2 VOUT1 = (2 x VIN) - VFD1 - VFD2 VOUT2 = -VIN where VOUT1 = positive doubled output voltage, VIN = input voltage, VFD1 = forward bias voltage across D1, VFD2 = forward bias voltage across D2, and VOUT2 = inverted output voltage. Figure 19. SP6832 Device Connected in a Doubler/Inverter Combination Circuit SP6832DS/04 SP6832 High Speed, High Efficiency Voltage Inverter © Copyright 2000 Sipex Corporation 11 +VIN ON IN 2 C1+ GND C1 C1- OFF Shutdown Logic 5 4 SP6832 CIN 0.1µF 3 1 OUT VOUT C2 Figure 20. SP6832 Device with Shutdown Control Combining a Doubler and Inverter Circuit A designer can connect a SP6832 device in a combination doubler/inverter circuit as seen in Figure 19. The doubler uses capacitors C3 and C4 while the inverter uses C1 and C2. Loading either output decreases both output voltages to GND because both the doubler and the inverter circuits use the charge pump. Designers should not allow the total current output from the doubler and the inverter to exceed 40mA. Implementing Shutdown If shutdown control of the SP6832 devices is necessary, the circuit found in Figure 20 can be implemented. The 0.1µF capacitor at IN absorbs transient input currents. The output resistance of the devices can be determined by the following equation: ROUT = 20 + 2 x RBUFFER , where ROUT is the output resistance and RBUFFER is the output resistance of the buffer driving IN. RBUFFER can be reduced by connecting multiple buffers in parallel at IN. The polarity of the SHUTDOWN signal can be changed by using a noninverting buffer to drive IN. Connecting in Parallel A designer can parallel a number of SP6832 devices to reduce the output resistance for specific designs. All devices will need their own flying capacitor, C1, but a single output capacitor will serve all of the devices connected in parallel by increasing the capacitance of C2 by a factor of n where n equals the total number of devices connected. This connection can be found in Figure 21. Cascading Devices A designer can cascade SP6832 devices to produce a larger inverted voltage output. Refer to Figure 22 for this circuit connection. With two cascaded devices, the unloaded output voltage is decreased by the output resistance of the first device multiplied by the quiescent current of the second device connected. The total output resistance is greatly increased when more than two devices are cascaded. Layout and Grounding Designers should make an effort to minimize noise by paying special attention to the circuit layout with the S P6832 d evices. External components should be connected in close proximity to the device and a ground plane should be implemented. This will keep electrical traces short minimizing parasitic inductance and capacitance. © Copyright 2000 Sipex Corporation SP6832DS/04 SP6832 High Speed, High Efficiency Voltage Inverter 12 +VIN IN 2 C1+ C1+ 2 IN 2 C1+ IN RL 5 4 SP6832 C1 “1” 1 OUT 5 4 SP6832 C1 “2” 1 OUT GND 5 4 C1 GND GND SP6832 “n” OUT C1- 3 C1- 3 C1- 3 1 VOUT VOUT = -VIN R RTOT = OUT n where VOUT = output voltage, VIN = input voltage, RTOT = total resistance of the devices connected in parallel, ROUT = the output resistance of a single device, and n = the total number of devices connected in parallel. C2 x n Figure 21. SP6832 Devices Connected in Parallel to Reduce Total Output Resistance +VIN IN 2 C1+ 2 C1+ GND C1+ GND IN 2 IN 5 4 SP6832 C1 “1” 5 OUT 5 4 SP6832 C1 “2” 1 OUT 3 4 SP6832 “n” C1 GND C1- 3 C1- 3 C1- 5 1 OUT VOUT C2 VOUT = -n x VIN where VOUT = output voltage, VIN = input voltage, and n = the total number of devices connected. C2 C2 Figure 22. SP6832 Devices Cascaded to Increase Output Voltage MANUFACTURER/ TELEPHONE # TDK/ 847-803-6100 PART NUMBER C1005X5R0J104K C1608X5R0J334K LMK105BJ104KV LMK107BJ334KA CAPACITANCE / VOLTAGE 0.1µF / 6.3V 0.33µF / 6.3V 0.1µF / 10V 0.33µF / 10V ESR @ 500kHz 0.08Ω 0.04Ω 0.1Ω 0.05Ω CAPACITOR SIZE/TYPE 0402/X5R 0603/X5R 0402/X5R 0603/X7R TDK/ 847-803-6100 TAIYO/YUDEN 847-925-0888 TAIYO/YUDEN 847-925-0888 Table 1. Suggested Low ESR SM Ceramic Capacitors SP6832DS/04 SP6832 High Speed, High Efficiency Voltage Inverter © Copyright 2000 Sipex Corporation 13 PACKAGE: SOT23-5 b C L e E e1 D C L A A2 A C L a 0.20 DATUM 'A' C A1 A .10 E1 L 2 SYMBOL A A1 A2 b C D E E1 L e e1 a MIN 0.90 0.00 0.90 0.25 0.09 2.80 2.60 1.50 0.35 0.95ref 1.90ref 0 O MAX 1.45 0.15 1.30 0.50 0.20 3.10 3.00 1.75 0.55 10 O SP6832DS/04 SP6832 High Speed, High Efficiency Voltage Inverter © Copyright 2000 Sipex Corporation 14 ORDERING INFORMATION Model Temperature Range Package Type SP6832EK . ............................................ -40˚C to +85˚C ............................................... SOT23-5 SP6832EK/TR ......................................... -40˚C to +85˚C ............................................... SOT23-5 Please consult the factory for pricing and availability on a Tape-On-Reel option. Corporation SIGNAL PROCESSING EXCELLENCE Sipex Corporation Headquarters and Sales Office 22 Linnell Circle Billerica, MA 01821 TEL: (978) 667-8700 FAX: (978) 670-9001 e-mail: sales@sipex.com Sales Office 233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600 Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. SP6832DS/04 SP6832 High Speed, High Efficiency Voltage Inverter © Copyright 2000 Sipex Corporation 15