®
SP691A/693A/800L/800M
Low Power Microprocessor Supervisory
with Battery Switch-Over
FEATURES
TOP VIEW
■ Precision 4.65V/4.40V Voltage Monitoring
■ 200ms Or Adjustable Reset Time
■ 100ms, 1.6s Or Adjustable Watchdog Time
■ 60µA Maximum Operating Supply Current
■ 2.0µA Maximum Battery Backup Current
■ 0.1µA Maximum Battery Standby Current
■ Power Switching
250mA Output in Vcc Mode (0.6Ω)
25mA Output in Battery Mode (5Ω)
■ On-Board Gating of Chip-Enable Signals
Memory Write-Cycle Completion
6ns CE Gate Propagation Delay
■ Voltage Monitor for Power-Fail or Low Battery
■ Backup-Battery Monitor
■ RESET Valid to Vcc=1V
■ 1% Accuracy Guaranteed (SP800L/800M)
■ Pin Compatible Upgrade to MAX691A/693A/
800L/800M
VBATT
1
16 RESET
VOUT
2
15 RESET
14 WDO
Vcc
3
GND
4
BATT ON
5
LOWLINE
6
11 WDI
OSCIN
7
10
PFO
OSCSEL
8
9
PFI
13 CEIN
Corporation
12 CEOUT
DIP/SO
Now Available in Lead Free Packaging
DESCRIPTION
The SP691A/693A/800L/800M is a microprocessor (µP) supervisory circuit that integrates
a myriad of components involved in discrete solutions to monitor power-supply and
battery-control functions in µP and digital systems. The SP691A/693A/800L/800M offers
complete µP monitoring and watchdog functions. The SP691A/693A/800L/800M is ideal for
a low-cost battery management solution and is well suited for portable, battery-powered
applications with its supply current of 35µA. The 6ns chip-enable propagation delay,
the 25mA current output in battery-backup mode, and the 250mA current output in
standard operation also makes the SP691A/693A/800L/800M suitable for larger scale,
high-performance equipment.
Part Number
RESET Threshold
RESET Accuracy
PFI Accuracy
Backup-Battery Switch
SP691A
4.65V
+125mV
+4%
YES
SP693A
4.40V
+125mV
+4%
YES
SP800L
4.65V
+50mV
+1%
YES
SP800M
4.40V
+50mV
+1%
YES
Date: 4/18/05
SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over © Copyright 2005 Sipex Corporation
1
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation
of the device at these ratings or any other above those
indicated in the operation sections of the specifications
below is not implied. Exposure to absolute maximum
rating conditions for extended periods of time may
affect reliability.
Enhanced ESD Specifications........................+4kV Human Body Model
Power Dissipation Per Package
16-pin PDIP (derate 14.3mW/OC above +70OC).......................1150mW
16-pin Narrow SOIC (derate 13.6mW/OC above 70OC)............1090mW
16-pin Wide SOIC (derate 11.2mW/OC above 70OC).................900mW
Storage Temperature....................................................-65OC to +150OC
Lead Temperature (soldering,10 sec).........................................+300OC
Terminal Voltages (with respect to GND)
VCC.......................................................................................-0.3V to +6V
VBATT.....................................................................................-0.3V to +6V
All Other Inputs........................................................-0.3V to (VCC +0.3V)
Input Currents
VCC Peak...........................................................................................1.0A
VCC Continuous.............................................................................250mA
VBATT Peak....................................................................................250mA
VBATT Continuous............................................................................25mA
GND, BATT ON............................................................................100mA
All Other Inputs..............................................................................25mA
ELECTRICAL CHARACTERISTICS
VCC = +4.75V to +5.5V for the SP691A/800L, VCC = +4.5V to +5.5V for the SP693A/800M, VBATT = +2.8V, and TAMB = TMIN to TMAX unless otherwise
noted. Typical values apply at TAMB=+25OC.
PARAMETERS
Operating Voltage Range,
VCC or VBATT, NOTE 1
Output Voltage, VOUT
in Normal Operating Mode
MIN.
VCC-0.05
VCC-0.3
VCC-0.2
VBATT-0.3
VBATT-0.25
VBATT-0.15
Supply Current in Normal
Operating Mode, IVcc
Supply Current in BatteryBackup Mode, IBATT, NOTE 2
Battery Switchover Threshold
5.5
VCC-0.015
VCC-0.15
VCC-0.09
0.6
0.9
VBATT-to-VOUT On-Resistance
VBATT Standby Current, IBATT,
NOTE 3
MAX.
0
VCC-to-VOUT On-Resistance
VOUT in Battery-Backup Mode
TYP.
1.2
2.0
VBATT-0.1
VBATT-0.07
VBATT-0.05
Date: 4/18/05
V
V
VCC=4.5V, IOUT=25mA
VCC=4.5V, IOUT=250mA
VCC=3.0V, VBATT=2.8V, IOUT=100mA
Ω
VCC=4.5V
VCC=3.0V
V
VBATT=4.5V, IOUT=20mA
VBATT=2.8V, IOUT=10mA
VBATT=2.0V, IOUT=5mA
5
7
10
15
25
30
Ω
VBATT=4.5V
VBATT=2.8V
VBATT=2.0V
35
60
µA
VCC>(VBATT-1V), excluding IOUT
0.001
2.0
µA
VCC(VBATT+0.2V), excluding IOUT
-0.1
VBATT+0.03
V
VBATT-0.03
Battery Switchover Hysteresis
UNITS CONDITIONS
60
mV
power-up
power-down
Peak to Peak
SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over © Copyright 2005 Sipex Corporation
2
ELECTRICAL CHARACTERISTICS
VCC = +4.75V to +5.5V for the SP691A/800L, VCC = +4.5V to +5.5V for the SP693A/800M, VBATT = +2.8V, and TAMB = TMIN to TMAX unless otherwise
noted. Typical values apply at TAMB=+25OC.
PARAMETERS
MIN.
BATT ON Output Low
Voltage
BATT ON Output Short
Circuit Current
1
TY P .
MA X .
0.1
0 .7
0.4
1.5
60
15
100
UNITS CONDITIONS
V
mA
µA
ISINK=3.2mA
ISINK=25mA
sink current
source current
RESET, LOWLINE, AND WATCHDOG TIMER
Reset Threshold Voltage
4.50
4.25
4.60
4.35
4.65
4.40
4.65
4.40
4.75
4.50
4.70
4.45
V
SP691A
SP693A
SP800L
SP800M
Reset Threshold Hysteresis
15
mV
center-to-peak
VCC to RESET Delay
80
µs
power down
LOWLINE to RESET Delay
800
ns
power down
ms
power-up
Reset Active Timeout Period
for the Internal Oscillator
140
Reset Active Timeout Period
for the External Clock,
N O TE 4
Watchdog Timeout Period for
the Internal Oscillator
280
clock
power-up
cycles
2048
1 .0
70
Watchdog Timeout Period for
the External Clock, NOTE 4
Minimum Watchdog Input
Pulse Width
200
1 .6
100
2.25
140
4096
1024
long period
short period
clock long period
cycles short period
100
RESET Output Voltage
sec
ms
ns
VIL=0.8V,VIH=0.75xVCC
ISINK=50µA, VCC=1V, VCC falling
ISINK=3.2mA, VCC=4.25V
ISOURCE=1.6mA, VCC=5V
0.004
0.1
0 .3
0.4
V
RESET Output Short-Circuit
Current
7
20
mA
RESET Output Voltage Low,
NOTE 5
0.1
0.4
V
ISINK=3.2mA
LOWLINE Output Voltage
0 .1
0.4
V
ISINK=3.2mA, VCC=4.25V
ISOURCE=1µA, VCC=5V
15
100
µA
output source current
0 .1
0.4
V
ISINK=3.2mA
ISOURCE=500µA, VCC=5V
3
10
mA
output source current
3 .5
3.5
LOWLINE Output Short
Circuit Current
WDO Output Voltage
3.5
WDO Output Short-Circuit
Current
Date: 4/18/05
output source current
SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over © Copyright 2005 Sipex Corporation
3
ELECTRICAL CHARACTERISTICS
VCC = +4.75V to +5.5V for the SP691A/800L, VCC = +4.5V to +5.5V for the SP693A/800M, VBATT = +2.8V, and TAMB = TMIN to TMAX unless otherwise
noted. Typical values apply at TAMB=+25OC.
PARAMETERS
WDI Threshold Voltage,
NOTE 6
WDI Input Current
MIN.
TYP.
M AX .
0.75xVCC
0.8
-50
-10
20
50
1.237
1.200
1.25
1.263
1.300
1.225
1.25
1.275
+0.01
+25
0.1
0.4
UNITS
V
µA
CONDITIONS
VIH
VIL
WDI=0V
WDI=VOUT
POWER-FAIL COMPARATOR
PFI Input Threshold
PFI Leakage Current
PFO Output Voltage
3.5
PFO Short Circuit Current
60
1
PFI-to-PFO Delay
15
100
25
60
V
SP691A/693A, VCC=5V
SP800L/800M, VCC=5V
nA
V
ISINK=3.2mA
ISOURCE=1µA, VCC=5V
mA
output sink current
µA
output source current
µs
VOD=15mV
VOD=15mV
CHIP-ENABLE GATING
CEIN Leakage Current
CEIN to CEOUT Resistance,
NOTE 7
CEOUT Short-Circuit Current
(RESET Active)
0.1
CEIN to CEOUT Propagation
Delay, NOTE 8
CEOUT Output Voltage High
3.5
(RESET Active)
2.7
RESET to CEOUT Delay
+0.005
+1
µA
disable mode
65
150
Ω
enable mode
0.75
2.0
mA
disable mode, CEOUT=0V
6
10
ns
50Ω source impedance driver, CLOAD=50pF
V
12
VCC=5V, IOUT= 100µA
VCC=0V, VBATT=2.8V, IOUT=1µA
µs
power-down
µA
OSCSEL=0V
INTERNAL OSCILLATOR
OSCIN Leakage Current
0.10
+5.0
OSCIN Input Pull-Up Current
10
100
µA
OSCSEL=VOUT or floating, OSCIN=0V
OSCSEL Input Pull-Up Current
10
100
µA
OSCSEL=0V
OSCIN Frequency Range
200
kHz
OSCSEL=0V
OSCIN External Oscillator
Threshold Voltage
OSCIN Frequency with
External Capacitor
Date: 4/18/05
VOUT-0.3
VOUT-0.6
3.65
2.0
2
V
kHz
VIH
VIL
OSCSEL=0V, COSC=47pF
SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over © Copyright 2005 Sipex Corporation
4
ELECTRICAL CHARACTERISTICS
VCC = +4.75V to +5.5V for the SP691A/800L, VCC = +4.5V to +5.5V for the SP693A/800M, VBATT = +2.8V, and TAMB = TMIN to TMAX unless otherwise
noted. Typical values apply at TAMB=+25OC.
NOTE 1: Either VCC or VBATT can go to 0V, if the other is greater than 2.0V.
NOTE 2: The supply current drawn by the SP691A/693A/800L/800M from the battery (excluding IOUT) typically
goes to 5µA when (VBATT - 1V) < VCC < VBATT. In most applications, this is a brief period as VCC falls through this region.
NOTE 3: "+" = battery-discharging current, "-" = battery-charging current.
NOTE 4: Although presented as typical values, the number of clock cycles for the reset and watchdog timeout
periods are fixed and do not vary with process or temperature.
NOTE 5: RESET is an open-drain output and sinks current only.
NOTE 6: WDI is internally connected to a voltage divider between VOUT and GND. If unconnected, WDI is driven
to 1.6V (typ), disabling the watchdog function.
NOTE 7: The chip-enable resistance is tested with VCC = +4.75V for the SP691A/800L and VCC = +4.5V for the
SP693A/800M. CEIN = CEOUT = VCC/2.
NOTE 8: The chip-enable propagation delay is measured from the 50% point at CEIN to the 50% point at CEOUT.
TYPICAL PERFORMANCE CHARACTERISTICS
o
(TAMB = 25 C, unless otherwise noted)
2.5
VCC = 5V
VBATT = 2.8V
43
VBATT Current (µA)
VCC Current (µA)
40
37
34
31
1.5
1.0
0.5
0.0
28
25
-60
-0.5
-30
0
30
60
90
Temperature (oC)
120
-60
Figure 1. VCC Supply Current vs. Temperature (Normal
Operating Mode)
30
60
90
Temperature (oC)
120
150
VCC = 0V
12
VCC = 4.75V
VBATT = 2.8V
CE IN = VCC/2
10
60.0
55.0
50.0
8
6
4
VBATT = 2V
VBATT = 2.8V
VBATT = 4.5V
2
45.0
40.0
-80 -60 -40 -20
0
0 20 40 60 80 100 120 140
Temperature (oC)
-60
-30
0
30
60
90
Temperature (oC)
120
150
Figure 4. VBATT to VOUT On-Resistance vs. Temperature
Figure 3. Chip-Enable On-Resistance vs. Temperature
Date: 4/18/05
0
14
Resistance (Ω)
CE-IN Resistance (Ω)
65.0
-30
Figure 2. Battery Supply Current vs. Temperature
(Battery-Backup Mode)
75.0
70.0
VCC = 1.6V
VBATT = 2.8V
2.0
SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over © Copyright 2005 Sipex Corporation
5
TYPICAL PERFORMANCE CHARACTERISTICS
1.256
0.7
0.5
0.3
-60
0
30
60
90
Temperature (oC)
120
1.240
-60
30
60
90
Temperature (oC)
120
150
Sourcing VCC = 5V
Sinking VCC = 4.25V
350
300
VCC Rising
VCC Falling
4.65
4.64
4.63
250
200
150
4.62
100
4.61
50
-30
0
30
60
90
Temperature (oC)
120
0
-60
150
Figure 7. Reset Threshold vs. Temperature
-30
0
30
60
90
Temperature (oC)
120
150
Figure 8. RESET Output Resistance vs. Temperature
0.240
1.E-04
VBATT Current (A), Log Scale
VCC = 5V
VBATT = 2.8V
0.230
0.220
0.210
0.200
0.190
1.E-05
VBATT = 2.8V
1.E-06
1.E-07
1.E-08
1.E-09
1.E-10
1.E-11
1.E-12
1.E-13
1.E-14
-30
0
30
60
90
Temperature (oC)
120
0
150
1
2
3
4
5
VCC (V)
Figure 9. Reset Delay vs. Temperature
Date: 4/18/05
0
400
VBATT = 0V
4.66
0.180
-60
-30
Figure 6. PFI Threshold vs. Temperature
4.67
4.60
-60
Reset Timeout Period (s)
1.244
150
Resistance (Ω)
Reset Threshold (V)
4.68
1.248
1.236
-30
Figure 5. VCC to VOUT On-Resistance vs. Temperature
4.69
VCC = 5V
VBATT = 0V
1.252
PFI Threshold (V)
Resistance (Ω)
0.9
VCC = 4.5V
VBATT = 2.8V
Figure 10. Battery Current vs. Input Supply Voltage
SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over © Copyright 2005 Sipex Corporation
6
TYPICAL PERFORMANCE CHARACTERISTICS
100
30
Long Watchdog Timeout Period
Reset Active Timeout Period
Short Watchdog Timeout Period
Propagation Delay (µs)
Watchdog and Reset
Timeout Period (s)
1000
10
1
0.1
10
VCC = 5V
VBATT = 2.8V
20
15
10
5
0
100
1000
OSCIN Capacitor (pF)
10000
0
Figure 11. Watchdog and Reset Timeout Period vs.
OSCIN Timing Capacitor (COSC)
50
100
150 200
Cload (pF)
250
300
350
Figure 12. Chip-Enable Propagation Delay vs. CEOUT
Load Capacitance
1000
Voltage Drop (mV)
1000
Voltage Drop (mV)
VCC = 5V
VBATT = 2.8V
50Ω driver
25
100
VCC = 4.5V
VBATT = 0V
Slope = 0.6Ω
10
100
VCC = 4.5V
VBATT = 0V
Slope = 5Ω
10
1
1
1
10
100
1
1000
10
Figure 13. VCC to VOUT vs. Output Current (Normal
Operating Mode)
VCC Reset
Threshold
100
1000
IOUT (mA)
IOUT (mA)
Figure 14. VBATT to VOUT vs. Output Current (BatteryBackup Mode)
+5V
0V
80µs
HI
RESET
LOW
1.1µs
LOWLINE
HI
LOW
16µs
HI
CEOUT
LOW
Figure 15. VCC to LOWLINE and CEOUT Delay
Date: 4/18/05
SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over © Copyright 2005 Sipex Corporation
7
PINOUT
Pin 7 — OSCIN — External Oscillator Input.
When OSCSEL is unconnected or driven
HIGH, a 10µA pull-up connects from VOUT
to this input pin, the internal oscillator sets
the reset and watchdog timeout periods, and
this input pin selects between fast and slow
watchdog timeout periods. When OSCSEL is
driven LOW, the reset and watchdog timeout
periods may be set either by a capacitor from
this input pin to ground or by an external
clock at this pin (refer to Figure 21).
TOP VIEW
VBATT
1
16 RESET
VOUT
2
15 RESET
14 WDO
Vcc
3
GND
4
BATT ON
5
LOWLINE
6
11 WDI
OSCIN
7
10
PFO
OSCSEL
8
9
PFI
13 CEIN
Corporation
12 CEOUT
DIP/SO
Pin 8 — OSCSEL — Oscillator Select. When
OSCSEL is unconnected or driven HIGH, the
internal oscillator sets the reset delay and
watchdog timeout period. When OSCSEL is
driven LOW, the external oscillator input
pin, OSCIN, is enabled (refer to Table 1).
This input pin has a 10µA internal pull-up.
PIN ASSIGNMENTS
Pin 1 — VBATT — Battery-Backup Input. Connect to the external battery supply or supercharging capacitor and charging circuit. If a
backup battery is not provided, connect this
pin to ground.
Pin 9 — PFI — Power-Fail Input. This is the
noninverting input to the power-fail
comparator. When PFI is less than 1.25V,
PFO goes low. Connect PFI to GND or
VOUT when not used.
Pin 2 —VOUT — Output Supply Voltage. VOUT
connects to VCC when VCC is greater than
VBATT and VCC is above the reset threshold.
When VCC falls below VBATT and VCC is
below the reset threshold, VOUT connects to
VBATT. Connect a 0.1µF capacitor from VOUT
to GND.
Pin 10 — PFO — Power-Fail Output. This is
the output of the power-fail comparator.
PFO goes low when PFI is less than 1.25V.
This is an uncommitted comparator, and
has no effect on any other internal circuitry.
Pin 3 — VCC — +5V Input Supply Voltage.
Pin 4 — GND — Ground reference for all
signals.
Pin 11 — WDI — Watchdog Input. This is a
three-level input pin. If WDI remains either
HIGH or LOW for longer than the watchdog
timeout period, WDO goes LOW and RESET
is asserted for the reset timeout period. WDO
remains LOW until the next transition at this
input pin. Leaving this input pin unconnected
disables the watchdog function. This input
pin connects to an internal voltage divider
between VOUT and ground, which sets it to
mid-supply when left unconnected.
Pin 5 — BATT ON — Battery On Output. Goes
high when VOUT switches to VBATT. Goes low
when VOUT switches to VCC. Connect the
base of a PNP through a current-limiting
resistor to BATT ON for VOUT current
requirements greater than 250mA.
Pin 6 — LOWLINE — Low Line Output. This
output pin goes LOW when VCC falls below
the reset threshold voltage. This output pin
returns to its HIGH output as soon as VCC
rises above the reset threshold voltage.
Date: 4/18/05
SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over © Copyright 2005 Sipex Corporation
8
Pin 15 — RESET — Active LOW Reset Output.
This output pin goes LOW whenever VCC
falls below the reset threshold. This output
pin will remain low typically for 200ms after
VCC crosses the reset threshold voltage on
power-up.
Pin 12 — CEOUT — Chip-Enable Output. This
output pin goes LOW only when CEIN is
LOW and VCC is above the reset threshold
voltage. If CEIN is LOW when RESET is
asserted, this output pin will stay low for
16µs or until CEIN goes HIGH, whichever
occurs first.
Pin 16 — RESET — Active HIGH Reset
Output. This output pin is open drain and
the inverse of RESET.
Pin 13 — CEIN — Chip-Enable Input. This is the
input pin to the chip-enable gating circuit.
If this input pin is not used, connect it to
ground or VOUT.
Pin 14 — WDO — Watchdog Output. If WDI
remains HIGH or LOW longer than the
watchdog timeout period, this output pin
goes LOW and RESET is asserted for the
reset timeout period. This output pin returns
HIGH on the next transition at WDI.
This output pin remains HIGH if WDI is
unconnected.
PFI
WDI
OSCSEL
OSCIN
9
10
1.25V
Watchdog
Transition
Detector
11
Watchdog
Timer
8
Reset /
Watchdog
Timebase
7
14
15
Reset
Generator
16
6
5
CEIN
RESET
LOWLINE
3
2
VBATT
WDO
RESET
CEOUT
Control
4.65V or
4.40V*
VCC
PFO
4
1
VOUT
BATT ON
GND
13
* 4.65V for the SP691A/800L
4.40V for the SP693A/800M
12
CEOUT
Figure 16. Internal Block Diagram of the SP691A/693A/800L/800M
Date: 4/18/05
SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over © Copyright 2005 Sipex Corporation
9
Unregulated DC
R1
PFI
Regulated +5V
R2
VCC
VCC
RESET
µP
A0-A15
RESET
NMI
PFO
I/O LINE
WDI
Backup
Supply
BUS
CMOS
RAM1
to
RAMn
Address
Decode
WDO
LOWLINE
alarm
system
status
indicator
VBATT
BATT ON
CEIN
VCC
VOUT
CEOUT
GND
0.1µF
Figure 17. Typical Application Circuit of the SP691A/693A/800L/800M
FEATURES
THEORY OF OPERATION
The SP691A/693A/800L/800M devices are
microprocessor (µP) supervisory circuits that
monitor the power supplied to digital circuits
such as microprocessors, microcontrollers, or
memory. The SP691A/693A/800L/800M series
is an ideal solution for portable, batterypowered equipment that require power supply
monitoring. The SP691A/693A/800L/800M
watchdog functions will continuously oversee
the operational status of a system. Implementing
the SP691A/693A/800L/800M series will
reduce the number of components and overall
complexity in a design that requires power
supply monitoring circuitry. The operational
features and benefits of this series are described
in more detail below.
The SP691A/693A/800L/800M series is a
complete µP supervisor IC and provides the
following main functions:
1) µP reset ➡ Reset output is asserted during
power fluxiations such as power-up,
power-down, and brown out conditions, and
is guaranteed to be in the correct state for
VCC down to 1V, even with no battery in
the circuit.
2) µP reset ➡ Reset output is pulsed if the
optional watchdog timer has not been
toggled within a specified time.
3) Power Fail Comparator ➡ Provides for
power-fail warning and low-battery
detection, or monitors another power
supply.
Date: 4/18/05
SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over © Copyright 2005 Sipex Corporation
10
4) Watchdog function ➡ Monitors µP activity
where the watchdog output goes to a logic
LOW state if the watchdog input is not
toggled for greater than the timeout period.
5) Internal switch ➡ Switches over from VCC
to VBATT if the VCC falls below the reset
threshold.
RESET
15
TO µP RESET
10kΩ
Corporation
RESET and RESET Outputs
The SP691A/693A/800L/800M devices'
RESET and RESET outputs ensure that the µP
powers up in a known state, and prevents
code-execution errors during power-down or
brownout conditions.
Figure 18. External Pull-down Resistor Ensures
RESET is Valid with VCC Down to Ground.
10kΩ and the output saturation voltage is below
0.4V while sinking 40µA. When using a 10kΩ
external pull-down resistor, the high state for
the RESET output with Vcc = 4.75V is 4.5V
typical. For battery voltages less than or equal
to 2V connected to VBATT, RESET and RESET
remains valid for VCC from 0V to 5.5V.
The RESET output is active low, and typically
sinks 3.2mA at 0.1V saturation voltage in its
active state. When deasserted, RESET sources
1.6mA at typically VOUT – 0.5V. RESET output
is open drain, active high, and typically sinks
3.2mA with a saturation voltage of 0.1V. When
no backup battery is used, RESET output is
guaranteed to be valid down to VCC = 1V, and
an external 10kΩ pull-down resistor on RESET
ensures that RESET will be valid with VCC
down to GND as shown on Figure 18. As VCC
goes below 1V, the gate drive to the RESET
output switch reduces accordingly, increasing
the RDS(ON) and the saturation voltage. The
10kΩ pull-down resistor ensures the parallel
combination of switch plus resistor is around
RESET and RESET are asserted when VCC falls
below the reset threshold and remain asserted
for the Reset Timeout Period (200ms nominal)
after VCC rises above the reset threshold voltage
on power-up. Refer to Figure 19. The devices'
battery-switchover comparator does not affect
reset assertion. However, both reset outputs are
asserted in battery-backup mode since VCC must
be below the reset threshold to enter this mode.
Vcc
RESET
THRESHOLD
CE IN
CE OUT
12µ
100µs
100µs
RESET
RESET
Figure 19. Reset and Chip-Enable Timing
Date: 4/18/05
SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over © Copyright 2005 Sipex Corporation
11
WDI
WDO
t2
t3
RESET
t1
t1
t1 = RESET Timeout Period
t2 = Normal Watchdog Timeout Period
t3 = Watchdog Timeout Period Immediately After RESET
Figure 20. Watchdog Timeout Period and Reset Active Time
Watchdog Function
The watchdog monitors µP activity via the
Watchdog Input (WDI). If the µP becomes
inactive, RESET and RESET are asserted.
To use the watchdog function, connect WDI to
a bus line or µP I/O line. If WDI remains high
or low for longer than the watchdog timeout period (1.6s nominal). WDO, RESET, and RESET
are asserted, indicating a software fault or idle
conditions. Refer to RESET and RESET
Outputs and Watchdog Output sections.
7
8
OSCIN
OSCSEL
X No Connect
X No Connect
1.6sec Normal Watchdog Timeout
Internal Oscillator
7
Watchdog Input
A change of logic state (minimum 100ns
duration) at WDI during the watchdog period
will reset the watchdog timer. The watchdog
default timout is 1.6sec.
8
OSCIN
OSCSEL
X No Connect
100ms Normal Watchdog Timeout
Internal Oscillator
CIN
To disable the watchdog function, leave WDI
floating. An internal resistor network (100kΩ
equivalent impedance at WDI) biases WDI to
approximately 1.6V. Internal comparators
detect this level and disable the watchdog timer.
When Vcc is below the reset threshold, the
watchdog function is disabled and WDI is
disconnected from its internal resistor network,
thus becoming high impedance.
7
8
OSCSEL
Normal Watchdog Timeout = 600 x CIN [ms]
47pF
External Oscillator
Watchdog Output
WDO remains high if there is activity (transition
or pulse) at WDI during the watchdog-timeout
period. The watchdog function is disabled and
WDO is a logic high when VCC is less than the
reset threshold or when WDI is an open circuit.
In watchdog mode, if no transition occurs at
WDI during the watchdog-timeout period,
Date: 4/18/05
OSCIN
7
8
OSCIN
OSCSEL
Normal Watchdog Timeout = 1024 Clock Periods
External Clock
Figure 21. Selecting Timeout Periods
SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over © Copyright 2005 Sipex Corporation
12
Watchdog Timeout Period
OSCSEL
OSCIN
Reset Timeout Period
Normal
Immediately After Reset
LOW
External Clock Input
1024 clocks
4096 clocks
2048 clocks
LOW
External Capacitor
(600/47pF x C) ms
(2.4 /47 pf x C) sec
(1200/47pF x C) ms
Floating
LOW
100 ms
1.6 s
200 ms
Floating
Floating
1.6 s
1.6 s
200 ms
Table 1. Reset Pulse Width and Watchdog Timeout Selections
The 10ns maximum CE propagation from CEIN
to CE OUT enables the SP691A/693A/800L/
800M devices to be used with most µPs.
RESET and RESET are asserted for the reset
timeout period (200ms nominal). WDO goes
to logic low and remains low until the next
transition at WDI. Refer to Figure 20. If WDI
is held high or low indefinitely, RESET and
RESET will generate 200ms pulses every 1.6s.
WDO has a 2 x TTL output characteristic.
Chip-Enable Input
CEIN is in high impedance (disabled mode)
while RESET and/or RESET are asserted.
Selecting an Alternative Watchdog
Timeout Period
The OSC SEL and OSC IN inputs control the
watchdog are reset timeout periods. Floating
OSCSEL and OSCIN or tying them both to VOUT
selects the nominal 1.6s watchdog timeout
period and 200ms reset timout period.
Connecting OSCIN to ground and floating or
connecting OSCSEL to VOUT selects a 100ms normal watchdog timeout period and a 1.6s timeout
period immediately after reset. The reset timeout
period remains 200ms. Refer to Figure 20.
Select alternative timeout periods by connecting
OSCSEL to ground and connecting a capacitor
between OSCIN and ground, or by externally
driving OSCIN . A synopsis of this control can
be found in Figure 21 and Table 1.
During a power-down sequence where VCC falls
below the reset threshold, CEIN assumes a high
impedance state when the voltage at CEIN goes
high or 12µs after RESET is asserted,
whichever occurs first. Refer to Figure 19.
During a power-up sequence, CEIN remains high
impedance until RESET is deasserted.
In the high-impedance mode, the leakage
currents into CEIN are
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