SP703EP

® SP703/SP704 Low Power Microprocessor Supervisory with Battery Switch-Over s Precision Voltage Monitor: SP703 at 4.65V SP704 at 4.40V s Reset Time Delay - 200ms s Debounced TTL/CMOS Compatible Manual - Reset Input s Minimum component count s 60µA Maximum Operating Supply Current s 0.6µA Maximum Battery Backup Current s 0.1µA Maximum Battery Standby Current s Power Switching 250mA Output in VCC Mode (0.6Ω) 25mA Output in Battery Mode (5Ω) s Voltage Monitor for Power Fail or Low Battery Warning s Available in 8 pin SO and DIP packages s RESET asserted down to VCC = 1V s Pin Compatible Upgrades to MAX703/MAX704 DESCRIPTION The SP703/704 devices are microprocessor (µP) supervisory circuits that integrate a myriad of components involved in discrete solutions to monitor power-supply and battery-control functions in µP and digital systems. The series will significantly improve system reliability and operational efficiency when compared to discrete solutions. The features of the SP703/704 devices include a manual reset input, a µP reset and backup-battery switchover, and powerfailure warning. The series is ideal for applications in computers, controllers, intelligent instruments and automotive systems. All designs where it is critical to monitor the power supply to the µP and its related digital components will find the series to be an ideal solution. VBATT BATTERY SWITCHOVER CIRCUITRY VOUT VOUT VCC GND PFI 1 2 3 4 8 7 6 5 VBATT RESET MR PFO VCC RESET GENERATOR 1.25V RESET MR PFI PFO 1.25V PINOUT SP703/704DS/07 INTERNAL BLOCK DIAGRAM SP703/704 Low Power Microprocessor Supervisory © Copyright 2000 Sipex Corporation 1 ABSOLUTE MAXIMUM RATINGS These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability and cause permanent damage to the device. VCC........................................................-0.3V to 6.0V VBATT.....................................................-0.3V to 6.0V All Other Inputs......................................-0.3V to (VCC +0.3V) Input Current: VCC.........................................................250mA VBATT........................................................50mA GND........................................................20mA Output Current: VOUT.....Short-Circuit Protected for up to 10sec All Other Inputs.................................20mA Rate of Rise, VCC,VBATT..................100V/µs Continuous Power Dissipation.......500mW Storage Temperature.......-65°C to +160°C Lead Temperature(soldering,10sec).................+300°C ESD Rating.............................4kV Human Body Model SPECIFICATIONS Vcc=4.75v to 5.50V for SP703, VCC = 4.50V to 5.50V for SP704, VBATT=2.80V, TA=TMIN to TMAX, typical specified at 25OC, unless otherwise noted. PARAMETERS Operating Voltage Range, MIN. 0 TYP. MAX. 5.5 UNITS Volts CONDITIONS VCC or VBATT, NOTE 1 Supply Current, ISUPPLY, ISUPPLY in Battery Backup Mode, VCC = 0V, VBATT = 2.8V VBATT Standby Current, NOTE 2 VOUT Output VOUT in Battery-Backup Mode VCC < VBATT - 0.2V Battery Switch Threshold, VCC to VBATT Battery Switchover Hysteresis Reset Threshold 4.50 4.25 -0.1 VCC - 0.1 VBATT -0.15 VCC - 0.03 VCC - 0.15 VBATT - 0.04 VBATT - 0.20 20 -20 40 4.65 4.40 4.75 4.50 35 0.001 60 0.6 0.02 µA µA µA Volts VCC > VBATT + 0.2V IOUT = 50mA IOUT = 250mA IOUT = 5mA IOUT = 25mA Power-up Power-down Peak to Peak SP703 SP704 excluding IOUT Volts mV mV Volts SP703/704DS/07 SP703/704 Low Power Microprocessor Supervisory © Copyright 2000 Sipex Corporation 2 SPECIFICATIONS (continued) Vcc=4.75V to 5.50V for SP703, VCC = 4.5 0V to 5.50V for SP704, VBATT=2.80V, TA=TMIN to TMAX, typical specified at 25OC, unless otherwise noted. PARAMETERS Reset Threshold Hysteresis Reset Pulse Width, tRS RESET Output Voltage MIN. TYP. 40 MAX. UNITS mV CONDITIONS Peak to Peak 140 VCC - 1.5 200 280 ms ISOURCE = 800µA 0.1 0.004 MR Input Threshold LOW HIGH MR Minimum Pulse Width MR to RESET Delay MR Pull Up Current PFI Input Threshold PFI Input Current PFO Output Voltage 100 1.200 -25 VCC - 1.5 0.1 250 1.250 0.01 0.4 0.3 Volts ISINK = 3.2mA ISINK = 50µA, VCC = 1.0V 0.8 2.0 150 250 600 1.300 25 V ns ns µA Volts nA Volts ISOURCE = 800µA ISINK = 3.2mA MR=0V 0.4 NOTE 1: Either VCC or VBATT can go to 0V if the other is greater than 2.0V. NOTE 2: "-" equals the battery-charging current, "+" equals the battery-discharging current. SP703/704DS/07 SP703/704 Low Power Microprocessor Supervisory © Copyright 2000 Sipex Corporation 3 PINOUT INTERNAL BLOCK DIAGRAM VBATT BATTERY SWITCHOVER CIRCUITRY VOUT VOUT VCC GND PFI 1 2 3 4 8 7 6 5 VBATT RESET MR PFO MR VCC RESET GENERATOR 1.25V RESET PIN ASSIGNMENTS Pin 1 —VOUT — Output Supply Voltage. VOUT connects to VCC when VCC is greater than VBATT and VCC is above the reset threshold. When VCC falls below VBATT and VCC is below the reset threshold, VOUT connects to VBATT. Connect a 0.1µF capacitor from VOUT to GND. Pin 2 — VCC — +5V Supply Input Pin3 — GND — Ground reference for all signals Pin 4 — PFI — Power-Fail Input. This is the noninverting input to the power-fail comparator. When PFI is less than 1.25V, PFO goes low. Connect PFI to GND or VOUT when not used. Pin 5 — PFO — Power-Fail Output. Pin 6 — MR — Manual Reset Input. This input generates a reset pulse when pulled below 0.8V. This active LOW input is TTL/ CMOS compatible and can be shorted to ground with a switch. It has an internal 250µA (typical) pull-up current. Leave this pin floating when not used. Pin 7 — RESET (Active Low)– Reset Output. RESET Output goes low whenever VCC falls below the reset threshold or whenever MR is pulled below 0.8V for longer than 150nS. RESET remains low for 200ms after VCC crosses the reset threshold voltage on power-up or after being triggered by MR. PFI PFO 1.25V Pin 8 — VBATT — Backup-Battery Input. When VCC falls below the reset threshold, VBATT will be switched to VOUT if VBATT is 20mV greater than VCC. When VCC rises 20mV above VBATT, VOUT will be reconnected to VCC. The 40mV hysteresis prevents repeated switching if VCC falls slowly. SP703/704DS/07 SP703/704 Low Power Microprocessor Supervisory © Copyright 2000 Sipex Corporation 4 TYPICAL CHARACTERISTICS (25oC, unless otherwise noted) VCC Supply Current vs. Temperature (Normal Mode) 51 47 43 39 35 31 27 23 19 -60 -30 Battery Supply Current vs. Temperature (Backup Mode) 2.9 PFI Threshold vs. Temperature 1.256 VBATT Current (µA) VCC Current (µA) 2.4 1.9 1.4 0.9 0.4 PFI Threshold (V) VCC=5V VBATT=2.8V VCC=0V VBATT=2.8V 1.254 1.252 1.250 1.248 1.246 -60 -30 0 VCC=5V VBATT=0 NO LOAD ON PFO 0 30 60 90 120 150 -0.1 -60 -40 -20 0 20 40 60 80 100 120 140 30 60 90 120 150 Temperature Deg. C Temperature Deg. C Temperature Deg. C VBATT to VOUT ON Resistance vs. Temperature 15 0.9 VCC to VOUT On Resistance vs. Temperature Resistance (ohms) 0.8 0.7 0.6 0.5 0.4 0.3 Reset Threshold vs. Temperature 4.70 4.69 4.68 4.67 4.66 4.65 4.64 4.63 4.62 4.61 4.60 -60 Resistance (ohms) 10 VBATT=2.8V 5 VBATT=4.5V 0 -60 -30 0 30 60 90 120 150 -60 -30 0 30 60 90 120 150 Reset Threshold (V) VCC=0V VBATT=2V VCC=5V VBATT=0V SP703 VBATT=0V Power Down -30 0 30 60 90 120 150 Temperature Deg. C Temperature Deg. C Temperature Deg. C Reset Output Resistance vs. Temperature 600 Reset Delay vs. Temperature 212 Reset Delay (mS) Resistance (ohms) 210 208 206 204 202 200 -60 VBATT Current(µA) Log Scale VCC=5V,VBATT=2.8V 500 Soucing Current 400 300 200 100 0 -60 VCC=0V to 5V Step, VBATT=2.8V Battery Current vs. VCC Voltage IE+2 IE+1 IE+0 IE-1 IE-2 IE-3 IE-4 IE-5 IE-6 IE-7 IE-8 .0000 VBATT=2.8V VCC=0V,VBATT=2.8V Sink Current -30 0 30 60 90 120 150 -30 0 30 60 90 120 150 Temperature Deg. C Temperature Deg. C VCC (0.5V/div) 5.000 SP703/704DS/07 SP703/704 Low Power Microprocessor Supervisory © Copyright 2000 Sipex Corporation 5 1000 1000 VCC=4.5V VBATT=0V Slope=0.6Ω Voltage Drop(mV) 100 VBATT=4.5V VCC=0V Slope=5Ω Voltage Drop(mV) 100 10 10 1 1 10 100 1000 1 1 10 100 IOUT (mA) IOUT (mA) Figure 1. VCC to VOUT Vs. Output Current Figure 2. VBATT to VOUT Vs. Output Current VCC VCC 2V div 0V RESET VBATT = 0V TA = 25oC VBATT = 0V TA = +25 C VCC 2KΩ RESET RESET 330pF GND 1sec/div 0V Figure 3A. SP703 RESET Output Voltage vs. Supply Voltage Figure 3B. Circuit for the RESET Output Voltage vs. Supply Voltage SP703/704DS/07 SP703/704 Low Power Microprocessor Supervisory © Copyright 2000 Sipex Corporation 6 VCC +5V VCC TA = +25 C VCC +4V +5V RESET 10KΩ RESET 0V 30pF 2µs/div GND Figure 4B. Circuit for the RESET Response Time Figure 4A. SP703 RESET Response Time VCC = 5V VBATT = 0V +1.3V PFI +1.2V +5V VCC = +5V TA = +25 C PFI 5V PFO 1KΩ PFO 30pF 0V +1.25V 500ns/div Figure 5A. Power-Fail Comparator Response Time (FALL) Figure 5B. Circuit for the Power-Fail Comparator Response Time (FALL) SP703/704DS/07 SP703/704 Low Power Microprocessor Supervisory © Copyright 2000 Sipex Corporation 7 +1.3V PFI VCC = 5V VBATT = 0V +5V VCC = +5V TA = +25 C PFI PFO 30pF 1KΩ +1.2V 3V PFO 0V +1.25V 2µs/div Figure 6A. Power-Fail Comparator Response Time (RISE) Figure 6B. Circuit for the Power-Fail Comparator Response Time (RISE) +5V VCC 0V +5V RESET tRS 0V +5V VOUT 0V +5V 3.0V PFO 0V VBATT = PFI = 3.0V Figure 7. Timing Diagram SP703/704DS/07 SP703/704 Low Power Microprocessor Supervisory © Copyright 2000 Sipex Corporation 8 FEATURES The SP703/704 devices provide four key functions: 1. A battery backup switching for CMOS RAM, CMOS microprocessors, or other logic. 2. A reset output during power-up, power-down and brownout conditions. 3. A reset pulse if the manual reset has been pulled below 0.8V for at least 150ns. 4. A 1.25V threshold detector for power-fail warning, low battery detection, or to monitor a power supply other than +5V. The SP703/704 devices differ only in their supply voltage monitor level. The S P703 generates a reset when VCC drops below 4.65V while the SP704 generates a reset below 4.4V. The SP703/704 devices are ideally suited for applications in automotive systems, intelligent instruments, and battery-powered computers and controllers. All designs into an environment where it is critical to monitor the power supply to the µP and its related digital components will find the SP703/704 ideal. THEORY OF OPERATION Reset Output The microprocessor's (µP's) reset input starts the µP in a known state. When the µP is in an unknown state, it should be held in reset. The SP703/704 assert reset during power-up and prevent code execution errors during powerdown or brownout conditions. On power-up, once VCC reaches 1V, RESET is guaranteed to be a logic low. As VCC rises, RESET remains low. When VCC exceeds the reset threshold, RESET will remain low for 200ms, Figure 9. If a brownout condition occurs and VCC dips below the reset threshold, RESET is triggered. Each time RESET is triggered, it stays low for the reset pulse width interval. If a brownout condition interrupts a previously initiated reset pulse, the reset pulse continues for another 200ms. On power-down, once VCC goes below the threshold, RESET is guaranteed to be logic low until VCC drops below 1V. RESET is also triggered by a manual reset Regulated +5V Unregulated DC VCC µP RESET NMI RESET PFO MR GND BUS VCC 0.1µF R1 PFI R2 VBATT VOUT GND Pushbutton Switch VCC CMOS RAM GND 3.6V Lithium Battery Figure 8. Typical Operating Circuit SP703/704DS/07 SP703/704 Low Power Microprocessor Supervisory © Copyright 2000 Sipex Corporation 9 Power-Fail Comparator The Power-Fail Comparator can be used as an under-voltage detector to signal the failing of a power supply (it is completely separate from the rest of the circuitry and does not need to be dedicated to this function). The PFI input is compared to an internal 1.25V reference. If PFI is less than 1.25V, PFO goes low. The external voltage divider drives PFI to sense the unregulated DC input to the +5V regulator. The voltage-divider ratio can be chosen such that the voltage at PFI falls below 1.25V just before the +5V regulator drops out. PFO then triggers an interrupt which signals the µP to prepare for power-down. When VBATT connects to VOUT, the power-fail comparator is turned off and PFO is forced low to conserve backup-battery power. Backup-Battery Switchover In the event of a brownout or power failure, it may be necessary to preserve the contents of RAM. With a backup battery installed at VBATT, the RAM is assured to have power if VCC fails. As long as VCC exceeds the reset threshold, VOUT connects to VCC through a 0.6Ω PMOS power switch. Once VCC falls below the reset threshold, VCC or VBATT, whichever is higher, switches to VOUT. VBATT connects to VOUT through a 5Ω switch only when VCC is below the reset threshold and VBATT is greater than VCC. When VCC exceeds the reset threshold, it is connected to VOUT, regardless of the voltage applied to VBATT Figure 9. During this time, the diode (D1) between VBATT and VOUT will conduct current from VBATT to VOUT if VBATT is more than .6V above VOUT. When VBATT connects to VOUT, backup mode is activated and the internal circuitry will be powered from the battery Figure 10. When VCC is just below VBATT, in the backup mode the current drawn from VBATT will be typically 30µA. When VCC drops to more than 1V below VBATT, the internal switchover comparator shuts off and the supply current falls to less than 0.6µA. VBATT VCC SW1 D1 D2 SW2 VOUT D3 GND CONDITION VCC > Reset Threshold VCC < Reset Threshold and VCC > VBATT VCC < Reset Threshold and VCC < VBATT SW1 Open Open Closed SW2 Closed Closed Open Reset Threshold = 4.65V in SP703 Reset Threshold = 4.40V in SP704 Figure 9. BACKUP-BATTERY Switchover Block Diagram SP703/704DS/07 SP703/704 Low Power Microprocessor Supervisory © Copyright 2000 Sipex Corporation 10 SIGNAL VCC VOUT STATUS Disconnected from VOUT Connected to VBATT through an internal 8Ω PMOS switch Connected to VOUT. Current drawn from the battery is less than 0.6µA, as long as VCC < VBATT - 1V. Power-fail comparator is disabled. Logic low Logic low Manual Reset is disabled Figure 12. Backup Power Source Using High Capacity Capacitor with SP703 and a +5V ±5% Supply +5V VCC VBATT 0.1F GND VOUT SP703 CONNECT TO STATIC RAM CONNECT TO µP VBATT RESET PFI PFO RESET MR Figure 10. Input and Output Status in Battery-Backup Mode. To enter the Battery-Backup mode, VCC must be less than the Reset threshold and less than VBATT. If VCC is above the reset threshold and VBATT is 0.5V above VCC, current flows to VOUT and VCC from VBATT until the voltage at VBATT is less than 0.5V above VCC. Leakage current through the capacitor charging diode and the S P703/704 i nternal power diode eventually discharges the capacitor to VCC. Also, if VCC and VBATT start from 0.5V above the reset threshold and power is lost at VCC, the capacitor on VBATT discharges through VCC until VBATT reaches the reset threshold; the S P703/704 t hen switches to battery-backup mode. Using a High Capacity Capacitor as a Backup Power Source VBATT has the same operating voltage range as VCC, and the battery-switchover threshold voltages are typically +20mV centered at VBATT, allowing use of a capacitor and a simple charging circuit as a backup source (see Figure 12). PART NUMBER SP703 SP704 MAXIMUM BACKUP-BATTERY VOLTAGE [V] 4.80 4.55 0.1F 100KΩ VBATT +5V VCC VOUT SP704 CONNECT TO STATIC RAM CONNECT TO µP RESET GND Figure 11. Allowable BACKUP-BATTERY Voltages Figure 13. Backup Power Source Using High Capacity Capacitor with SP704 and a +5V ±10% Supply SP703/704DS/07 SP703/704 Low Power Microprocessor Supervisory © Copyright 2000 Sipex Corporation 11 +5V VIN VCC PFI R3 PFO *optional GND VTRIP = connect to µP 1.25 R2 R1 + R2 *C1 R2 R1 Operation Without a Backup Power Source If a backup power source is not used, ground VBATT and connect VOUT to VCC. Since there is no need to switch over to any backup power source, VOUT does not need to be switched. A direct connection to VCC eliminates any voltage drops across the switch which may push VOUT below VCC. Replacing the Backup Battery The backup battery can be removed while VCC remains valid, without danger of triggering RESET/RESET. As long as VCC stays above the reset threshold, battery-backup mode cannot be entered. Adding Hysteresis to the Power-Fail Comparator Hysteresis adds a noise margin to the power-fail comparator and prevents repeated triggering of PFO when VIN is close to its trip point. Figure 14 shows how to add hysteresis to the power-fail comparator. Select the ratio of R1 and R2 such that PFI sees 1.25V when VIN falls to its trip point (VTRIP). R3 adds the hysteresis. It will typically be an order of magnitude greater (about 10 times) than R1 or R2. The current through R1 and R2 should be at least 1µA to ensure that the 25nA (max) PFI input current does not shift the trip point. R3 should be larger than 10KΩ so it does not load down the PFO pin. Capacitor C1 adds additional noise rejection. Monitoring a Negative Voltage The power-fail comparator can be used to monitor a negative supply rail using the circuit of Figure 15. When the negative rail is valid, PFO is low. When the negative supply voltage drops, PFO goes high. This circuit's accuracy is affected by the PFI threshold tolerance, the VCC voltage, and the resistors, R1 and R2. 1.25 R2 = VL - 1.25 + 5.0 - 1.25 R3 R1 1.25 R2 || R3 R1 + R2 || R3 VH = PFO +5V 0V 0V VL VTRIP VH VIN Figure 14. Adding Hysteresis to the POWER-FAIL Comparator Allowable Backup Power-Source Batteries Lithium batteries work very well as backup batteries due to very low self-discharge rate and high energy density. Single lithium batteries with open-circuit voltages of 3.0V to 3.6V are ideal. Any battery with an open-circuit voltage less than the minimum reset threshold plus 0.3V can be connected directly to the VBATT input of this series with no additional circuitry; see Figure 8. However, batteries with open-circuit voltages that are greater than this value cannot be used for backup, as current is sourced into VOUT through the diode (D1 in Figure 9) when VCC is close to the reset threshold. SP703/704DS/07 SP703/704 Low Power Microprocessor Supervisory © Copyright 2000 Sipex Corporation 12 +5V VCC PFI R2 PFO VGND 5.0 - 1.25 = 1.25 - VTRIP R2 R1 PFO +5V 0V 0V R1 Buffered RESET connects to System Components +5V VCC +5V VCC µP RESET 4.7KΩ RESET GND GND Figure 16. Interfacing to Microprocessors with Bidirectional RESET I/O *VTRIP V- *VTRIP is a negative voltage Figure 15. Monitoring a Negative Voltage Interfacing to Microprocessors with Bidirectional Reset Pins Microprocessors with bidirectional reset pins, such as the Motorola 68HC11 series, can contend with this series' RESET output. If, for example, the RESET output is driven high and the µP wants to pull it low, indeterminate logic levels may result. To correct this, connect a 4.7KΩ resistor between the RESET output and the µP reset I/O, as in Figure 16. Buffer the RESET output to other system components. SP703/704DS/07 SP703/704 Low Power Microprocessor Supervisory © Copyright 2000 Sipex Corporation 13 PACKAGE: PLASTIC DUAL–IN–LINE (NARROW) E1 E D1 = 0.005" min. (0.127 min.) D A1 = 0.015" min. (0.381min.) A = 0.210" max. (5.334 max). A2 C Ø eA = 0.300 BSC (7.620 BSC) L e = 0.100 BSC (2.540 BSC) B1 B ALTERNATE END PINS (BOTH ENDS) DIMENSIONS (Inches) Minimum/Maximum (mm) A2 B B1 C D E E1 L Ø 8–PIN 0.115/0.195 (2.921/4.953) 0.014/0.022 (0.356/0.559) 0.045/0.070 (1.143/1.778) 0.008/0.014 (0.203/0.356) 0.355/0.400 (9.017/10.160) 0.300/0.325 (7.620/8.255) 0.240/0.280 (6.096/7.112) 0.115/0.150 (2.921/3.810) 0°/ 15° (0°/15°) SP703/704DS/07 SP703/704 Low Power Microprocessor Supervisory © Copyright 2000 Sipex Corporation 14 PACKAGE: PLASTIC SMALL OUTLINE (SOIC) (NARROW) E H h x 45° D A Ø e B A1 L DIMENSIONS (Inches) Minimum/Maximum (mm) A A1 B D E e H h L Ø 8–PIN 0.053/0.069 (1.346/1.748) 0.004/0.010 (0.102/0.249 0.014/0.019 (0.35/0.49) 0.189/0.197 (4.80/5.00) 0.150/0.157 (3.802/3.988) 0.050 BSC (1.270 BSC) 0.228/0.244 (5.801/6.198) 0.010/0.020 (0.254/0.498) 0.016/0.050 (0.406/1.270) 0°/8° (0°/8°) SP703/704DS/07 SP703/704 Low Power Microprocessor Supervisory © Copyright 2000 Sipex Corporation 15 ORDERING INFORMATION Model Temperature Range Package Types SP703CN..........................................................0°C to +70°C....................................................8-Pin NSOIC SP703CP........................................................0°C to +70°C.........................................................8-Pin PDIP SP703EN......................................................-40°C to +85°C.....................................................8-Pin NSOIC SP703EP.......................................................-40°C to +85°C....................................................... 8-Pin PDIP SP704CN........................................................0°C to +70°C......................................................8-Pin NSOIC SP704CP........................................................0°C to +70°C......................................................... 8-Pin PDIP SP704EN......................................................-40°C to +85°C................................................... ..8-Pin NSOIC SP704EP.......................................................-40°C to +85°C....................................................... 8-Pin PDIP Please consult the factory for pricing and availability on a Tape-On-Reel option. Corporation SIGNAL PROCESSING EXCELLENCE Sipex Corporation Headquarters and Sales Office 22 Linnell Circle Billerica, MA 01821 TEL: (978) 667-8700 FAX: (978) 670-9001 e-mail: sales@sipex.com Sales Office 233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600 Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described hereing; neither does it convey any license under its patent rights nor the rights of others. SP703/704DS/07 SP703/704 Low Power Microprocessor Supervisory © Copyright 2000 Sipex Corporation 16