Wide Input Voltage Range 3A,
300kHz, Buck Regulator
SP7650
Power Blox
TM
SP7650
DFN PACKAGE
7mmSP7650
x 4mm
DFN PACKAGE
7mm x 4mm
FEATURES
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
2.5V to 28V Step Down Achieved Using Dual Input
Output Voltage down to 0.8V
3A Output Capability
Built in Low RDSON Power Switches (40 m1 typ)
Highly Integrated Design, Minimal Components
300 kHz Fixed Frequency Operation
UVLO Detects Both VCC and VIN
Over Temperature Protection
Short Circuit Protection with Auto-Restart
Wide BW Amp Allows Type II or III Compensation
Programmable Soft Start
Fast Transient Response
High Efficiency: Greater than 95% Possible
Asynchronous Start-Up into a Pre-Charged Output
Small 7mm x 4mm DFN Package
U.S. Patent #6,922,041
LX 26
25 1
LX PGND
BOTTOM VIEW
24 2
LX PGND
PGND 3
LX 23
VCC
PGND
1
PGND
LX
2 26
BOTTOM
Heatsink
PadVIEW
1
LX
3 25PGND
Connect to Lx
Heatsink Pad 1
LX
Connect
to
Lx
24
Pin 27
4 GND
GND
22 4
LX
5 23VFB
VFB 5
GND 21
Heatsink Pad 2
COMP 6 Connect to GND
GND 20
Heatsink pad 2
Connect to GND
UVIN 7
GND 19
Pin 28
GND 8
BST 18
SS 9
NC 17
Heatsink Pad 3
VIN 10 Connect to VIN
LX 16
Heatsink pad 3
VIN 11
Connect to VIN
LX 15
VIN 12
Pin 29
LX 14
VIN 13
VCC
6 2 2COMP
GND
7 21UV
IN
GND
8 20GND
9
19 GND
SS
18 BST
10 VIN
17 NC
11 VIN
16 LX
12 VIN
15 LX
13 VIN
14 LX
Now Available in Lead Free Packaging
DESCRIPTION
The SP7650 is a synchronous step-down switching regulator optimized for high efficiency. The part is designed to be
especially attractive for dual supply, 12V or 24V distributed power systems stepped down with 5V used to power the
controller. This lower VCC voltage minimizes power dissipation in the part and is used to drive the top switch. The
SP7650 is designed to provide a fully integrated buck regulator solution using a fixed 300kHz frequency, PWM voltage
mode architecture. Protection features include UVLO, thermal shutdown and output short circuit protection. The
SP7650 is available in the space saving DFN package.
TYPICAL APPLICATION CIRCUIT
U1
SP7650
1
RZ2
CZ2
1,000pF
15k1,1%
CP1
4
6
ENABLE
CF1
3
5
22pF
100pF
2
7
8
9
CSS
47nF
10
11
12
13
VIN
12V
LX
PGND
LX
PGND
LX
GND
LX
VFB
VCC
COMP
GND
UVIN
GND
GND
GND
SS
BST
VIN
NC
VIN
LX
VIN
LX
VIN
LX
26
25
22uF
16V
RZ3
24
23
+5V VCC
22
21
20
19
18
17
16
15
14
CVCC
C3
47uF
6.3V
7.15k1,1%
CZ3
VOUT
3.3V
0-3A
R1
68.1k1,1%
150pF
2.2uF
DBST
SD101AWS
RSET
21.5k1,1%
(note 2)
CBST
6800pF
Notes:
1. U1 Bottom-Side Layout should
have three contacts isolated from
one another:
Vin, SWNODE and GND.
2. RSET=54.48/(Vout-0.8V)
Date:
Date: 2/16/06
11/15/06
L1
2.2uH, Irate=4.78A
fs=300Khz
C1
GND
PGND
(KOhm)
SP7650
Voltage
Range
3A, 300kHz,
Regulator
SP7650
WideWide
InputInput
Voltage
Range
3A, 300kHz,
BuckBuck
Regulator
1
Copyright2006
2006Sipex
SipexCorporation
Corporation
©©Copyright
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the
specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
VCC ................................................................................................... 7V
VIN ........................................................................................................................................... 30V
ILX ............................................................................................................................................... 5A
BST ............................................................................................... 35V
LX-BST ............................................................................. -0.3V to 7V
LX ....................................................................................... -1V to 30V
All other pins .......................................................... -0.3V to VCC+0.3V
Storage Temperature .................................................. -65°C to 150°C
Power Dissipation ...................................... Internally Limited via OTP
ESD Rating .......................................................................... 2kV HBM
Thermal Resistance VJC .................................................................................... 5°C/W
ELECTRICAL SPECIFICATIONS
Unless otherwise specified: -40°C < TAMB < 85°C, -40°C< Tj< 125°C, 4.5V < VCC < 5.5V, 3V< Vin< 28V, BST=LX + 5V, LX =
GND = 0.0V, UVIN = 3.0V, CVCC = 1µF, CCOMP = 0.1µF, CSS = 50nF, Typical measured at VCC = 5V. The z denotes the
specifications which apply over the full temperature range, unless otherwise specified.
PARAMETER
MIN.
TYP.
MAX.
UNITS
1.5
3
mA
4
6
mA
0.2
0.4
mA
4
4
6
mA
V CC UVLO Start Threshold
4.00
4.25
4.5
V
V CC UVLO Hysteresis
100
200
300
mV
UVIN Start Threshold
2.3
2.5
2.65
V
UVIN Hysteresis
200
300
400
mV
1
µA
CONDITIONS
QUIESCENT CURRENT
V CC Supply Current (No switching)
V CC Supply Current (switching)
BST Supply Current (No switching)
BST Supply Current (switching)
VFB = 0.9V
z
VFB = 0.9V
z
PROTECTION: UVLO
UVIN Input Current
z
UVIN = 3.0V
ERROR AMPLIFIER REFERENCE
Error Amplifier Reference
0.792
0.800
0.808
V
Error Amplifier Reference
Over Line and Temperature
0.788
0.800
0.812
V
2X Gain Config., Measure
VFB; VCC = 5 V, T = 25˚C
z
Error Amplifier Transconductance
6
mA/V
Error Amplifier Gain
60
dB
No Load
COMP Sink Current
150
µA
VFB = 0.9V, COMP = 0.9V
COMP Source Current
150
µA
VFB = 0.7V, COMP = 2.2V
V FB Input Bias Current
50
nA
VFB = 0.8V
Internal Pole
4
MHz
COMP Clamp
2.5
V
COMP Clamp Temp. Coefficient
-2
mV/˚C
Date:
Date:2/16/06
11/15/06
200
SP7650
Wide
Voltage
Range
3A, 300kHz,
Regulator
SP7650
Wide
InputInput
Voltage
Range
3A, 300kHz,
BuckBuck
Regulator
2
VFB = 0.7V, TA = 25˚C
© Copyright
Copyright 2006
2006 Sipex
Sipex Corporation
Corporation
©
ELECTRICAL SPECIFICATIONS
Unless otherwise specified: -40°C < TAMB < 85°C, -40°C< Tj< 125°C, 4.5V < VCC < 5.5V, 3V< Vin< 28V, BST=LX + 5V,
LX = GND = 0.0V, UVIN = 3.0V, CVCC = 1µF, CCOMP = 0.1µF, CSS = 50nF, Typical measured at VCC = 5V.
The z denotes the specifications which apply over the full temperature range, unless otherwise specified.
PARAMETER
MIN.
TYP.
MAX.
UNITS
CONDITIONS
CONTROL LOOP: PWM COMPARATOR, RAMP & LOOP DELAY PATH
Ramp Amplitude
0.92
1.1
RAMP Offset
1.1
RAMP offset Temp. Coefficient
-2
GH Minimum Pulse Width
90
Maximum Controllable Duty Ratio
92
Maximum Duty Ratio
100
Internal Oscillator Ratio
240
1.28
TA = 25˚C, RAMP COMP
until GH starts Switching
V
mV/˚C
180
97
300
V
360
ns
z
%
Maximum Duty Ratio Measured
just before pulsing begins
%
Valid for 20 cycles
kHz
z
TIMERS: SOFTSTART
SS Charge Current:
10
SS Discharge Current:
µA
1
mA
z
Fault Present, SS = 0.2V
V
z
Measured VREF (0.8V) - VFB
PROTECTION: SHORT CIRCUIT & THERMAL
Short Circuit Threshold Voltage
0.2
0.25
0.3
Hiccup Timeout
200
ms
Number of Allowable Clock Cycles
at 100% Duty Cycle
20
Cycles
Minimum GL Pulse After 20 Cycles
0.5
Cycles
Thermal Shutdown Temperature
145
˚C
Thermal Recovery Temperature
135
˚C
10
˚C
High Side Switch R DSON
40
mΩ
VCC = 5V ; IOUT = 3A; TAMB = 25˚C
Synchrous Lowside Switch R DSON
40
mΩ
VCC = 5V ; IOUT = 3A ; TAMB = 25˚C
Thermal Hysteresis
V FB = 0.5V
V FB = 0.7V
V FB = 0.7V
OUTPUT: POWER STAGE
Maximum Output Current
2/16/06
Date: 11/15/06
3
A
SP7650
Voltage
Range
3A, 300kHz,
Regulator
SP7650
WideWide
InputInput
Voltage
Range
3A, 300kHz,
BuckBuck
Regulator
3
Copyright2006
2006Sipex
SipexCorporation
Corporation
©©Copyright
PIN DESCRIPTION
Pin #
Pin Name
Description
1-3
PGND
Ground connection for the synchronous rectifier
4,8,19-21
GND
Ground Pin. The control circuitry of the IC and lower power driver are
referenced to this pin. Return separately from other ground traces to the (-)
terminal of Cout.
5
VFB
Feedback Voltage and Short Circuit Detection pin. It is the inverting input of
the Error Amplifier and serves as the output voltage feedback point for the
Buck Converter. The output voltage is sensed and can be adjusted through
an external resistor divider. Whenever V FB drops 0.25V below the positive
reference, a short circuit fault is detected and the IC enters hiccup mode.
6
COMP
7
UVIN
9
SS
10-13
VIN
14-16,23-26
LX
17
NC
No Connect
18
BST
High side driver supply pin. Connect BST to the external boost diode and
capacitor as shown in the Typical Application Circuit on page 1. High side
driver is connected between BST pin and SWN pin.
22
Vcc
Input for external 5V bias supply
Output of the Error Amplifier. It is internally connected to the inverting input of
the PWM comparator. An optimal filter combination is chosen and connected
to this pin and either ground or VFB to stabilize the voltage mode loop.
UVLO input for Vin voltage. Connect a resistor divider between VIN and UVIN
to set minimum operating voltage.
Soft Start. Connect an external capacitor between SS and GND to set the
soft start rate based on the 10µA source current. The SS pin is held low via a
1mA (min) current during all fault conditions.
Input connection to the high side N-channel MOSFET. Place a decoupling
capacitor between this pin and PGND.
Connect an inductor between this pinand V OUT
THEORY OF OPERATION
General Overview
The SP7650 is a fixed frequency, voltage mode,
synchronous PWM regulator optimized for high
efficiency. The part has been designed to be
especially attractive for high voltage applications utilizing 5V to power the controller and
2.5V to 28V for step down conversion.
The SP7650 contains two unique control features that are very powerful in distributed applications. First, asynchronous driver control is
enabled during start up, to prohibit the low side
switch from pulling down the output until the
high side switch has attempted to turn on. Second, a 100% duty cycle timeout ensures that the
low side switch is periodically enhanced during
extended periods at 100% duty cycle. This guarantees the synchronized refreshing of the BST
capacitor during very large duty ratios.
The heart of the SP7650 is a wide bandwidth
transconductance amplifier designed to accommodate Type II and Type III compensation
schemes. A precision 0.8V reference, present
on the positive terminal of the error amplifier
permits the programming of the output voltage
down to 0.8V via the VFB pin. The output of the
error amplifier, COMP, compared to a 1.1V
peak-to-peak ramp is responsible for trailing
edge PWM control. This voltage ramp, and
PWM control logic are governed by the internal
oscillator that accurately sets the PWM frequency to 300kHz.
Date:
Date: 2/16/06
11/15/06
The SP7650 also contains a number of valuable
protection features. Programmable VIN UVLO
allows the user to set the exact value at which
the conversion voltage can safely begin down
conversion, and an internal VCC UVLO which
ensures that the controller itself has enough
voltage to operate properly. Other protection
SP7650
Voltage
Range
3A, 300kHz,
Regulator
SP7650
WideWide
InputInput
Voltage
Range
3A, 300kHz,
BuckBuck
Regulator
4
Copyright 2006
2006 Sipex
Sipex Corporation
Corporation
©© Copyright
THEORY OF OPERATION
Thermal and Short-Circuit
Protection
features include thermal shutdown and shortcircuit detection. In the event that either a thermal, short-circuit, or UVLO fault is detected,
the SP7650 is forced into an idle state where the
output drivers are held off for a finite period
before a restart is attempted.
Because the SP7650 is designed to drive large
output current, there is a chance that the power
converter will become too hot. Therefore, an
internal thermal shutdown (145°C) has been
included to prevent the IC from malfunctioning
at extreme temperatures.
Soft Start
“Soft Start” is achieved when a power converter
ramps up the output voltage while controlling
the magnitude of the input supply source current. In a modern step down converter, ramping
up the positive terminal of the error amplifier
controls soft start. As a result, excess source
current can be defined as the current required to
charge the output capacitor.
A short-circuit detection comparator has also
been included in the SP7650 to protect against
an accidental short at the output of the power
converter. This comparator constantly monitors
the positive and negative terminals of the error
amplifier, and if the VFB pin falls more than
250mV (typical) below the positive reference, a
short-circuit fault is set. Because the SS pin
overrides the internal 0.8V reference during soft
start, the SP7650 is capable of detecting shortcircuit faults throughout the duration of soft
start as well as in regular operation.
IVIN = COUT * (6VOUT / 6TSOFT-START)
The SP7650 provides the user with the option to
program the soft start rate by tying a capacitor
from the SS pin to GND. The selection of this
capacitor is based on the 10uA pull up current
present at the SS pin and the 0.8V reference
voltage. Therefore, the excess source can be
redefined as:
Handling of Faults:
Upon the detection of power (UVLO), thermal,
or short-circuit faults, the SP7650 is forced into
an idle state where the SS and COMP pins are
pulled low and both switches are held off. In the
event of UVLO fault, the SP7650 remains in this
idle state until the UVLO fault is removed.
Upon the detection of a thermal or short-circuit
fault, an internal 200ms timer is activated. In the
event of a short-circuit fault, a re-start is attempted immediately after the 200ms timeout
expires. Whereas, when a thermal fault is detected the 200ms delay continuously recycles
and a re-start cannot be attempted until the
thermal fault is removed and the timer expires.
IVIN = COUT * (6VOUT *10µA / (CSS * 0.8V)
Under Voltage Lock Out (UVLO)
The SP7650 contains two separate UVLO comparators to monitor the bias (VCC) and conversion (VIN) voltages independently. The VCC
UVLO threshold is internally set to 4.25V,
whereas the VIN UVLO threshold is programmable through the UVIN pin. When the UVIN
pin is greater than 2.5V, the SP7650 is permitted
to start up pending the removal of all other
faults. Both the VCC and VIN UVLO comparators have been designed with hysteresis to prevent noise from resetting a fault.
Date: 11/15/06
2/16/06
Date:
Error Amplifier and Voltage Loop
Since the heart of the SP7650 voltage error loop
is a high performance, wide bandwidth transconductance amplifier. Because of the amplifier’s
current limited (+/-150µA) transconductance,
there are many ways to compensate the voltage
loop or to control the COMP pin externally. If
a simple, single pole, single zero response is
SP7650
Voltage
Range
3A, 300kHz,
Regulator
SP7650
WideWide
InputInput
Voltage
Range
3A, 300kHz,
Buck Buck
Regulator
5
Copyright2006
2006Sipex
SipexCorporation
Corporation
©©Copyright
THEORY OF OPERATION
desired, then compensation can be as simple as
an RC circuit to Ground. If a more complex
compensation is required, then the amplifier has
enough bandwidth (45° at 4 MHz) and enough
gain (60dB) to run Type III compensation
schemes with adequate gain and phase margins
at crossover frequencies greater than 50kHz.
VBST
GH
Voltage
VSWN
V(VCC)
GL
Voltage
The common mode output of the error amplifier
is 0.9V to 2.2V. Therefore, the PWM voltage
ramp has been set between 1.1V and 2.2V to
ensure proper 0% to 100% duty cycle capability.
The voltage loop also includes two other very
important features. One is an asynchronous
startup mode. Basically, the synchronous rectifier cannot turn on unless the high side switch
has attempted to turn on or the SS pin has
exceeded 1.7V. This feature prevents the controller from “dragging down” the output voltage
during startup or in fault modes. The second
feature is a 100% duty cycle timeout that ensures synchronized refreshing of the BST capacitor at very high duty ratios. In the event that
the high side NFET is on for 20 continuous
clock cycles, a reset is given to the PWM flipflop half way through the 21st cycle. This forces
GL to rise for the cycle, in turn refreshing the
BST capacitor. The boost capacitor is used to
generate a high voltage drive supply for the high
side switch, which is 5V above VIN.
0V
V(VIN)
SWN
Voltage
-0V
-V(Diode) V
V(VIN)+V(VCC)
BST
Voltage
V(VCC)
Setting Output Voltages
The SP7650 can be set to different output voltages. The relationship in the following formula
is based on a voltage divider from the output to
the feedback pin VFB, which is set to an internal
reference voltage of 0.80V. Standard 1% metal
film resistors of surface mount size 0603 are
recommended.
Power MOSFETs
The SP7650 contains a pair of integrated low
resistance N-channel switches designed to drive
up to 3A of output current. Care should be taken
to de-rate the output current based on the thermal conditions in the system such as ambient
temperature, airflow and heat sinking. Maximum output current could be limited by thermal
limitations of a particular application by taking
advantage of the integrated-over-temperature
protective scheme employed in the SP7650.
The SP7650 incorporates a built-in over-temperature protection to prevent internal overheating.
Date: 2/16/06
Date: 11/15/06
TIME
Vout = 0.80V ( R1 / R2 + 1 ) =>
R2 = R1 / [ ( Vout / 0.80V ) – 1 ]
Where R1 = 68.1K1 and for Vout = 0.80V
setting, simply remove R2 from the board.
Furthermore, one could select the value of the
R1 and R2 combination to meet the exact
output voltage setting by restricting R1
resistance range such that 50K1 < R1 <
100K1 for overall system loop stability.
SP7650 Wide Input Voltage Range 3A, 300kHz, Buck Regulator
SP7650 Wide Input Voltage Range 3A, 300kHz, Buck Regulator
6
© Copyright 2006 Sipex Corporation
© Copyright 2006 Sipex Corporation
APPLICATIONS INFORMATION
Inductor Selection
There are many factors to consider in selecting
the inductor including core material, inductance
vs. frequency, current handling capability, efficiency, size and EMI. In a typical SP7650 circuit, the inductor is chosen primarily for value,
saturation current and DC resistance. Increasing
the inductor value will decrease output voltage
ripple, but degrade transient response. Low inductor values provide the smallest size, but
cause large ripple currents, poor efficiency and
require more output capacitance to smooth out
the larger ripple current. The inductor must be
able to handle the peak current at the switching
frequency without saturating, and the copper
resistance in the winding should be kept as low
as possible to minimize resistive power loss. A
good compromise between size, loss and cost is
to set the inductor ripple current to be within
20% to 40% of the maximum output current.
I PEAK = I OUT (max) +
...and provide low core loss at the high switching frequency. Low cost powdered iron cores
have a gradual saturation characteristic but can
introduce considerable AC core loss, especially
when the inductor value is relatively low and the
ripple current is high. Ferrite materials, although
more expensive, and have an abrupt saturation
characteristic with the inductance dropping
sharply when the peak design current is exceeded. Nevertheless, they are preferred at high
switching frequencies because they present very
low core loss while the designer is only required
to prevent saturation. In general, ferrite or
molypermalloy materials are a better choice for
all but the most cost sensitive applications.
The switching frequency and the inductor operating point determine the inductor value as follows:
L=
Optimizing Efficiency
The power dissipated in the inductor is equal to
the sum of the core and copper losses. To minimize copper losses, the winding resistance needs
to be minimized, but this usually comes at the
expense of a larger inductor. Core losses have a
more significant contribution at low output current where the copper losses are at a minimum,
and can typically be neglected at higher output
currents where the copper losses dominate. Core
loss information is usually available from the
magnetics vendor. Proper inductor selection can
affect the resulting power supply efficiency by
more than 15%!
VOUT (V IN (max) < VOUT )
VIN (max) FS Kr I OUT ( max)
where:
fS = switching frequency
Kr = ratio of the AC inductor ripple current to
the maximum output current
The peak to peak inductor ripple current is:
I PP =
The copper loss in the inductor can be calculated
using the following equation:
VOUT (VIN (max) < VOUT )
PL( Cu) = I L2 ( RMS ) RWINDING
VI N (max) FS L
where IL(RMS) is the RMS inductor current that
can be calculated as follows:
Once the required inductor value is selected, the
proper selection of core material is based on
peak inductor current and efficiency requirements. The core must be large enough not to
saturate at the peak inductor current...
Date: 11/15/06
2/16/06
Date:
I PP
2
IL(RMS) = IOUT(max) 1 + 1
3
SP7650
Voltage
Range
3A, 300kHz,
Regulator
SP7650
WideWide
Input Input
Voltage
Range
3A, 300kHz,
Buck Buck
Regulator
7
(
IPP
IOUT(max)
)
2
Copyright2006
2006Sipex
SipexCorporation
Corporation
©©Copyright
APPLICATIONS INFORMATION
Output Capacitor Selection
FS = Switching Frequency
The required ESR (Equivalent Series Resistance) and capacitance drive the selection of the
type and quantity of the output capacitors. The
ESR must be small enough that both the resistive voltage deviation due to a step change in the
load current and the output ripple voltage do not
exceed the tolerance limits expected on the
output voltage. During an output load transient,
the output capacitor must supply all the additional current demanded by the load until the
SP7650 adjusts the inductor current to the new
value.
D = Duty Cycle
COUT = Output Capacitance Value
Input Capacitor Selection
The input capacitor should be selected for ripple
current rating, capacitance and voltage rating.
The input capacitor must meet the ripple current
requirement imposed by the switching current.
In continuous conduction mode, the source current of the high-side MOSFET is approximately
a square wave of duty cycle VOUT/VIN. More
accurately the current wave form is trapezoidal,
given a finite turn-on and turn-off, switch transition slope. Most of this current is supplied by
the input bypass capacitors. The RMS current
handling capability of the input capacitors is
determined at maximum output current and
under the assumption that the peak to peak
inductor ripple current is low, it is given by:
ICIN(RMS) = IOUT(max) 3 D(1 - D)
In order to maintain VOUT ,the capacitance must
be large enough so that the output voltage is held
up while the inductor current ramps to the value
corresponding to the new load current. Additionally, the ESR in the output capacitor causes
a step in the output voltage equal to the current.
Because of the fast transient response and inherent 100%/0% duty cycle capability provided by
the SP7650 when exposed to output load transients, the output capacitor is typically chosen
for ESR, not for capacitance value.
The worse case occurs when the duty cycle D is
50% and gives an RMS current value equal to
IOUT/2.
The output capacitor’s ESR, combined with the
inductor ripple current, is typically the main
contributor to output voltage ripple. The maximum allowable ESR required to maintain a
specified output voltage ripple can be calculated
by:
Select input capacitors with adequate ripple
current rating to ensure reliable operation.
The power dissipated in the input capacitor is:
RESR ) 6VOUT
2
PCIN = ICIN
( rms ) R ESR ( CIN )
IPK-PK
This can become a significant part of power
losses in a converter and hurt the overall energy
transfer efficiency. The input voltage ripple
primarily depends on the input capacitor ESR
and capacitance. Ignoring the inductor ripple
current, the input voltage ripple can be determined by:
where:
6VOUT = Peak to Peak Output Voltage Ripple
IPK-PK = Peak to Peak Inductor Ripple Current
The total output ripple is a combination of the
ESR and the output capacitance value and can
be calculated as follows:
6 VIN = I out (max) RE SR (CIN ) +
(
6VOUT = IPP (1 – D)
COUTFS
Date:
Date:2/16/06
11/15/06
)
2
I OUT ( MAX )VOUT (VI N < VOUT )
FS C INV IN
2
+ (IPPRESR)2
SP7650
Wide
Input
Voltage
Range
300kHz,
Regulator
SP7650
Wide
Input
Voltage
Range
3A, 3A,
300kHz,
BuckBuck
Regulator
8
© Copyright
Copyright 2006
2006 Sipex
Sipex Corporation
Corporation
©
APPLICATIONS INFORMATION
The first step of compensation design is to pick
the loop crossover frequency. High crossover
frequency is desirable for fast transient response,
but often jeopardizes the power supply stability.
Crossover frequency should be higher than the
ESR zero but less than 1/5 of the switching
frequency or 60kHz. The ESR zero is contributed by the ESR associated with the output
capacitors and can be determined by:
The capacitor type suitable for the output capacitors can also be used for the input capacitors.
However, exercise additional caution when tantalum capacitors are used. Tantalum capacitors are
known for catastrophic failure when exposed to
surge current, and input capacitors are prone to
such surge current when power supplies are connected “live” to low impedance power sources.
Although tantalum capacitors have been successfully employed at the input, it is generally not
recommended.
ƒZ(ESR) =
The next step is to calculate the complex conjugate poles contributed by the LC output filter,
Loop Compensation Design
The open loop gain of the whole system can be
divided into the gain of the error amplifier,
PWM modulator, buck converter output stage,
and feedback resistor divider. In order to cross
over at the desired frequency cut-off (FCO), the
gain of the error amplifier has to compensate for
the attenuation caused by the rest of the loop at
this frequency. The goal of loop compensation
is to manipulate loop frequency response such
that its crossover gain at 0db results in a slope of
-20db/dec.
ƒP(LC) =
+
_
1
2/
L COUT
When the output capacitors are of a Ceramic
Type, the SP7650 Evaluation Board requires a
Type III compensation circuit to give a phase
boost of 180° in order to counteract the effects of
an underdamped resonance of the output filter at
the double pole frequency.
Type III Voltage Loop
Compensation
GAMP (s) Gain Block
VREF
(Volts)
1
2/ COUT RESR
PWM Stage
GPWM Gain
Block
Output Stage
GOUT (s) Gain
Block
VIN
(SRz2Cz2+1)(SR1Cz3+1)
(SRESRCOUT+ 1)
VRAMP_PP
SR1Cz2(SRz3Cz3+1)(SRz2Cp1+1)
[S^2LCOUT+S(RESR+RDC) COUT+1]
VOUT
(Volts)
Notes: RESR = Output Capacitor Equivalent Series Resistance.
RDC = Output Inductor DC Resistance.
VRAMP_PP = SP6132 Internal RAMP Amplitude Peak to Peak Voltage.
Condition: Cz2 >> Cp1 & R1 >> Rz3
Output Load Resistance >> RESR & RDC
Voltage Feedback
GFBK Gain Block
R2
VFBK
(Volts)
(R1 + R2)
or
VREF
VOUT
SP7650 Voltage Mode Control Loop with Loop Dynamic
Definitions:
RESR = Output Capacitor Equivalent Series Resistance
RDC = Output Inductor DC Resistance
RRAMP_PP = SP7650 internal RAMP Amplitude Peak to Peak Voltage
Conditions:
CZ2 >> Cp1 and R1 >> Rz3
Output Load Resistance >> RESR and RDC
Date: 2/16/06
Date: 11/15/06
SP7650 Wide Input Voltage Range 3A, 300kHz, Buck Regulator
SP7650 Wide Input Voltage Range 3A, 300kHz, Buck Regulator
9
© Copyright 2006 Sipex Corporation
© Copyright 2006 Sipex Corporation
APPLICATIONS INFORMATION
SP765X Thermal Resistance
The SP765X family has been tested with a
variety of footprint layouts along with different
copper area and thermal resistance has been
measured. The layouts were done on 4 layer
FR4 PCB with the top and bottom layers using
3oz copper and the power and ground layers
using 1oz copper.
Using a minimum of 0.1 square inches of (3
ounces of) Copper on the top layer with no vias
connecting to the 3 other layers produced a
thermal resistance of 44°C/W. This thermal
impedance is only 22% higher than the medium
and large footprint layouts, indicating that space
constrained designs can still benefit thermally
from the Powerblox family of ICs. This indicates that a minimum footprint of 0.1 square
inch, if used on a 4 layer board, can produce
44°C/W thermal resistance. This approach is
still very worthwhile if used in a space constrained design.
For the Minimum footprint, only about 0.1 square
inch (of 3 ounces of) Copper was used on the top
or footprint layer, and this layer had no vias to
connect to the 3 other layers. For the Medium
footprint, about 0.7 square inches (of 3 ounces
of) Copper was used on the top layer, but vias
were used to connect to the other 3 layers. For
the Maximum footprint, about 1.0 square inch
(of 3 ounces of) Copper was used on the top
layer and many vias were used to connect to the
3 other layers.
The following page shows the footprint layouts
from an ORCAD file. The thermal data was
taken for still air, not with forced air. If forced
air is used, some improvement in thermal resistance would be seen.
The results show that only about 0.7 square
inches (of 3 ounces of) Copper on the top layer
and vias connecting to the 3 other layers are
needed to get the best thermal resistance of
36°C/W. Adding area on the top beyond the 0.7
square inches did not reduce thermal resistance.
SP765X Thermal Resistance
4 Layer Board:
Top Layer 3ounces Copper
GND Layer 1ounce Copper
Power Layer 1ounce Copper
Bottom Layer 3ounces Copper
Minimum Footprint: 44°C/W
Top Layer: 0.1 square inch
No Vias to other 3 Layers
Medium Footprint: 36°C/W
Top Layer: 0.7 square inch
Vias to other 3 Layers
Maximum Footprint: 36°C/W
Top Layer: 1.0 square inch
Vias to other 3 Layers
Date: 2/16/06
Date: 11/15/06
SP7650 Wide Input Voltage Range 3A, 300kHz, Buck Regulator
SP7650 Wide Input Voltage Range 3A, 300kHz, Buck Regulator
10
10
© Copyright 2006 Sipex Corporation
© Copyright 2006 Sipex Corporation
Date: 2/16/06
Date: 11/15/06
SP7650 Wide Input Voltage Range 3A, 300kHz, Buck Regulator
SP7650 Wide Input Voltage Range 3A, 300kHz, Buck Regulator
11
11
© Copyright 2006 Sipex Corporation
© Copyright 2006 Sipex Corporation
APPLICATIONS INFORMATION
Gain
(dB)
Error Amplifier Gain
Bandwidth Product
Condition:
C22 >> CP1, R1 >> RZ3
1/6.28 (RZ3) (CZ3)
1/6.28 (RZ2) (CP1)
1/6.28 (R1) (CZ2)
1/6.28 (R1) (CZ3)
1/6.28(R22) (CZ2)
20 Log (RZ2/R1)
Frequency
(Hz)
Bode Plot of Type III Error Amplifier Compensation.
CP1
RZ3
CZ3
CZ2
VOUT
R1
68.1k, 1%
5
VFB
R
SET
+
+
- 0.8V
R
SET
RZ2
6
COMP
CF1
=54.48/ (VOUT -0.8) (k1)
Type III Error Amplifier Compensation Circuit
Date:
Date:2/16/06
11/15/06
SP7650
Wide
Input
Voltage
Range
300kHz,
Regulator
SP7650
Wide
Input
Voltage
Range
3A, 3A,
300kHz,
BuckBuck
Regulator
12
12
© Copyright
Copyright 2006
2006 Sipex
Sipex Corporation
Corporation
©
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs Load at 3.3Vin
100
Efficiency vs Load at 5.0Vin
100
95
95
90
90
85
85
80
Vout=2.5V
75
80
Vout=3.3V
75
Vout=2.5V
70
Vout=1.8V
70
Vout=1.8V
65
Vout=1.2V
65
Vout=1.2V
60
60
0.0
0.5
1.0
1.5
Output Load (A)
2.0
2.5
Efficiency vs Load at 12Vin
100
0.0
3.0
0.5
1.0
95
95
90
90
85
85
80
Vout=3.3V
70
Vout=1.2V
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
3.0
Output Load (A)
Output Load (A)
Date:
Date:2/16/06
11/15/06
2.5
Vout=2.5V
60
60
0.0
Vout=3.3V
65
Vout=1.8V
65
3.0
Vout=5.0V
70
Vout=2.5V
2.5
Vout=12V
75
Vout=5.0V
75
2.0
Efficiency vs Load at 24Vin
100
80
1.5
Output Load (A)
SP7650
Voltage
Range
3A, 300kHz,
Regulator
SP7650
WideWide
InputInput
Voltage
Range
3A, 300kHz,
BuckBuck
Regulator
13
13
© Copyright
Copyright 2006
2006 Sipex
Sipex Corporation
Corporation
©
TYPICAL PERFORMANCE CHARACTERISTICS
95.0
SP7650 Effi. v.s Iout Plots @
Vin=12V, and Vout=3.3V
Output Voltage (V)
Efficiency (%)
90.0
85.0
80.0
75.0
70.0
0.5
SP7650 Vout v.s Iout Plots @
Vin=12V, and Vout=3.3V
3.34
3.33
3.32
3.31
3.3
1.0
1.5
2.0
2.5
0
3.0
0.5
1.0
94.0
SP7650 Effi. v.s Iout Plots @
Vin=12V, and Vout=5.0V
Output Voltage (V)
Efficiency (%)
2.5
3.0
4.9700
88.0
86.0
84.0
82.0
80.0
78.0
76.0
4.9690
4.9680
4.9670
4.9660
4.9650
1.0
1.5
2.0
2.5
0
3.0
0.5
1.0
1.5
2.0
2.5
3.0
Load Current (A)
Load Current (A)
Date:
Date: 2/16/06
11/15/06
2.0
SP7650 Vout v.s Iout Plots @
Vin=12V, and Vout=5.0V
4.9710
92.0
90.0
74.0
0.5
1.5
Load Current (A)
Load Current (A)
SP7650
Voltage
Range
3A, 300kHz,
Regulator
SP7650
WideWide
InputInput
Voltage
Range
3A, 300kHz,
BuckBuck
Regulator
14
Copyright2006
2006Sipex
SipexCorporation
Corporation
©©Copyright
Date: 11/15/06
SP7650 Wide Input Voltage Range 3A, 300kHz, Buck Regulator
15
© Copyright 2006 Sipex Corporation
Part Number
Temperature
Package
SP7650ER ................................................. -40°C to +85°C ................................. 26 Pin 7 X 4 DFN
SP7650ER-L .............................................. -40°C to +85°C ............. (Lead Free) 26 Pin 7 X 4 DFN
SP7650ER/TR ........................................... -40°C to +85°C ................................. 26 Pin 7 X 4 DFN
SP7650ER-L/TR ........................................ -40°C to +85°C ............. (Lead Free) 26 Pin 7 X 4 DFN
Bulk Pack minimum quantity is 500.
/TR = Tape and Reel. Pack quantity is 3,000 DFN.
Sipex Corporation
Sipex Corporation
Solved By Sipex
Solved by Sipex
TM
tm
Headquarters and
Headquarters and
Sales Office
Sales Office
233 South Hillview Drive
233 South Hillview Drive
Milpitas, CA 95035
Milpitas, CA 95035
TEL: (408) 934-7500
TEL: (408) 934-7500
FAX: (408) 935-7600
FAX: (408) 935-7600
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the
any liability arising out of the application or use of any product or circuit described herein; neither does it convey
application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
any license under its patent rights nor the rights of others.
Date: 2/16/06
Date: 11/15/06
SP7650 Wide Input Voltage Range 3A, 300kHz, Buck Regulator
16
16
SP7650 Wide Input Voltage Range 3A, 300kHz, Buck Regulator
© Copyright 2006 Sipex Corporation
© Copyright 2006 Sipex Corporation
