SP7652EU

SP7652 Evaluation Board Manual Easy Evaluation for the SP7652EU 0 to 28V Input, 0 to 8A Output Synchronous Buck Converter Built in Low Rds(on) Power FETs UVLO Detects Both VCC and VIN High Integrated Design, Minimal Components High Efficiency: 90% Feature Rich: UVIN, Programmable Softstart, External VCC Supply and Output Dead Short Circuit Shutdown SP7652EB SCHEMATIC Rev 07/07/04 SP7652 Evaluation Manual Copyright 2004 Sipex Corporation USING THE EVALUATION BOARD 1) Powering Up the SP7652EB Circuit Connect the SP7652 Evaluation Board with an external +12V power supply. Connect with short leads and large diameter wire directly to the “VIN” and “GND” posts. Connect a Load between the VOUT and GND2 posts, again using short leads with large diameter wire to minimize inductance and voltage drops. 2) Measuring Output Load Characteristics It’s best to GND reference scope and digital meters using the Star GND post in the center of the board. VOUT ripple can best be seen touching probe tip to the pad for C3 and scope GND collar touching Star GND post – avoid a GND lead on the scope which will increase noise pickup. 3) Using the Evaluation Board with Different Output Voltages While the SP7652 Evaluation Board has been tested and delivered with the output set to 3.30V, by simply changing one resistor, R2, the SP7652 can be set to other output voltages. The relationship in the following formula is based on a voltage divider from the output to the feedback pin VFB, which is set to an internal reference voltage of 0.80V. Standard 1% metal film resistors of surface mount size 0603 are recommended. Vout = 0.80V ( R1 / R2 + 1 ) => R2 = R1 / [ ( Vout / 0.80V ) – 1 ] Where R1 = 68.1KΩ and for Vout = 0.80V setting, simply remove R2 from the board. Furthermore, one could select the value of R1 and R2 combination to meet the exact output voltage setting by restricting R1 resistance range such that 50KΩ ≤ R1 ≤ 100KΩ for overall system loop stability. Note that since the SP7652 Evaluation Board design was optimized for 12V down conversion to 3.30V, changes of output voltage and/or input voltage will alter performance from the data given in the Power Supply Data section. In addition, the SP7652EU provides short circuit protection by sensing Vout at GND. POWER SUPPLY DATA The SP7652EU is designed with a very accurate 1.0% reference over line, load and temperature. Figure 1 data shows a typical SP7652 Evaluation Board Efficiency plot, with efficiencies to 90% and output currents to 8A. SP7652EU Load Regulation is shown in Figure 2 of only 0.4% change in output voltage from no load to 8A load. Figures 3 and 4 illustrate a 4A to 8A and 0A to 8A Load Step. Start-up Response in Figures 5, 6 and 7 show a controlled start-up with different output load behavior when power is applied where the input current rises smoothly as the Softstart ramp increases. In Figure 8 the SP7652EU is configured for hiccup mode in response to an output dead short circuit condition and will Softstart until the over-load is removed. Figure 9 and 10 show output voltage ripple less than 50mV at no load to 8A load. While data on individual power supply boards may vary, the capability of the SP7652EU of achieving high accuracy over a range of load conditions shown here is quite impressive and desirable for accurate power supply design. 2 Vin=12V Vout=3.3V Vin=12V Vout=3.3V Figure 1. Efficiency vs Load Figure 2. Load Regulation Vout Vin Vout Vin Iout (5A/div) Vin=12V Vout=3.3V Iout (5A/div) Vin=12V Vout=3.3V Figure 3. Load Step Response: 4->8A Figure 4. Load Step Response: 0->8A Vout Vout Vin SoftStart Vin SoftStart Iout (5A/div) Iout (5A/div) Figure 5. Start-Up Response: No Load Vout Figure 6. Start-Up Response: 4A Load SoftStart Vin Vout Iout (5A/div) Ichoke (5A/div) Figure 7. Start-Up Response: 8A Load Figure 8. Output Load Short Circuit 3 +5V BIAS SUPPLY APPLICATION SCHEMATIC In this application example, the SP7652EU is power by an external +5V bias supply which current consumption of 20mA Maximum. If this supply is not available than it is recommend Sipex SPX5205 Low-Noise LDO Voltage Regulator which is included on the SP7652 Evaluation Board. Vout ripple = 30mV Vout ripple = 50mV Vin Vin Ichoke (5A/div) Ichoke(5A/div) Figure 9. Output Ripple: No Load Figure 10. Output Ripple: 8A Load 4 DIFFERENT +5V BIAS SUPPLY SCHEMES APPLICATION SCHEMATIC The SP7652EU VCC Bias Supply can be derived from Vin or external bias with several biasing options. The transistor plus zener diode +5V bias supply could also be used as shown in Figure 11. Figure 11. Transistor plus Zener Diode +5V Supply Application Schematic Table 1: SP7652EB Suggested Components and Vendor Lists 5 TYPE III LOOP COMPENSATION DESIGN The open loop gain of the SP7652EB can be divided into the gain of the error amplifier Gamp(s), PWM modulator Gpwm, buck converter output stage Gout(s), and feedback resistor divider Gfbk. In order to crossover at the selecting frequency fco, the gain of the error amplifier has to compensate for the attenuation caused by the rest of the loop at this frequency. The goal of loop compensation is to manipulate the open loop frequency response such that its gain crosses over 0dB at a slope of –20dB/dec. The open loop crossover frequency should be higher than the ESR zero of the output capacitors but less than 1/5 to 1/10 of the switching frequency fs to insure proper operation. Since the SP7652EB is designed with Ceramic Type output capacitors, a Type III compensation circuit is required to give a phase boost of 180° in order to counteract the effects of the output LC under damped resonance double pole frequency. Figure 12. Voltage Mode Control Loop with Loop Dynamic for Type III Compensation 6 The simple guidelines for positioning the poles and zeros and for calculating the component values for Type III compensation are as follows. a. b. c. d. e. f. g. h. i. Choose fco = fs / 10 Calculate fp_LC fp_LC = 1 / 2π [(L) (C)] ^ 1/2 Calculate fz_ESR fz_ESR = 1 / 2π (Resr) (Cout) Select R1 component value such that 50kΩ ≤ R1 ≤ 100kΩ Calculate R2 base on the desired Vout R2 = R1 / [(Vout / 0.80V) – 1] Select the ratio of Rz2 / R1 gain for the desired gain bandwidth Rz2 = R1 (Vramp_pp / Vin_max) (fco / fp_LC) Calculate Cz2 by placing the zero at ½ of the output filter pole frequency Cz2 = 1 / π (Rz2) (fp_LC) Calculate Cp1 by placing the first pole at ESR zero frequency Cp1 = 1 / 2π (Rz2) (fz_ESR) Calculate Rz3 by setting the second pole at ½ of the switching frequency and the second zero at the output filter double pole frequency Rz3 = 2 (R1) (fp_LC) / fs Calculate Cz3 from Rz3 component value above Cz3 = 1 / π (Rz3) (fs) Choose 100pF ≤ Cf1 ≤ 220pF to stabilize the SP7652EU internal Error Amplify j. k. As a particular example, consider for the following SP7652EB with a Type III Voltage Loop Compensation component selections: Vin = 5 to 15V Vout = 3.30V @ 0 to 8A load Select L = 1.5uH => yield ≈ 35% of maximum 8A output current ripple. Select Cout = 47uF Ceramic capacitor (Resr ≈ 2mΩ) fs = 600khz SP7652 internal Oscillator Frequency Vramp_pp = 1.0V SP7652 internal Ramp Peak to Peak Amplitude Step by step design procedures: a. b. c. fco = 600khz / 10 = 60khz fp_LC = 1 / 2π [(1.5uH)(47uF)]^1/2 ≈ 20khz fz_ESR = 1 / 2π (2mΩ)(47uF) ≈ 1.7Mhz 7 d. e. f. g. h. i. j. k. R1 = 68.1kΩ, 1% R2 = 68.1kΩ / [(3.30V / 0.80V) – 1] ≅ 21.5kΩ, 1% Rz2 = 68.1kΩ (1.0V / 15V) (60khz / 20khz) ≈ 11.8kΩ, 1% Cz2 = 1 / π (11.8kΩ) (20khz) ≈ 1,000pF, X7R Cp1 = 1 / 2π (11.8kΩ) (1.7Mhz) ≈ 10pF => Select Cp1 = 22pF for noise filtering Rz3 = 2 (68.1kΩ) (20khz) / 600khz ≈ 5.23kΩ, 1% Cz3 = 1 / π (5.23kΩ) (600khz) ≅ 100pF, COG Cf1 = 100pF to stabilize SP7652EU internal Error Amplify +5V INPUT WITH A TYPE III COMPENSATION APPLICATION SCHEMATIC Figure 13 shows another example of SP7652EU configures for +5V input by simply changing a few external resistors and capacitors components value for delivering a 08A output with excellent line and load regulation. Figure 13. SP7652EU Configures for Vin = 5V, Vout = 3.3V at 0-8A Output Load Current 8 TYPE II LOOP COMPENSATION DESIGN Type II compensation is specifically used when an Electrolytic or Tantalum output capacitor is chosen at the converter output due to its low cost. In that case, the zero caused by the output capacitor ESR is within a few khz and this is of course greatly simplifying the voltage loop compensation design. By adding an additional zero in the compensation loop before the first pole, the voltage loop bandwidth is extended with a 90º phase boost and hence the overall transient response time is improved. Most previous guidelines for calculating the component values for Type III compensation can be carries over for Type II except for the new Rz, Cz and Cp components. Note that Rz2, Cz2, Cp1, Rz3, and Cz3 components are not required for the Type II Loop Compensation Design. Figure 14. Voltage Mode Control Loop with Loop Dynamic for Type II Compensation 9 f. g. h. Select the ratio of Rz / R1 gain for the desired gain bandwidth Rz = R1 (Vramp_pp / Vin_max) (fco) [fz_ESR / (fp_LC) ^ 2] Calculate Cz by placing the zero at 1/10 of the output filter pole frequency Cz = 1 / 0.1(2π) (Rz) (fp_LC) Calculate Cp by placing the second pole at ½ of the switching frequency Cp = 1 / π (Rz) (fs) As a particular example, consider for the following SP7652EB with a Type II Voltage Loop Compensation component selections: Vin = 5 to 15V Vout = 3.30V @ 0 to 8A load Select L = 1.5uH => yield ≈ 35% of maximum 8A output current ripple. Select Cout = 330uF Tantalum capacitor (Resr ≈ 10mΩ) fs = 600khz SP7652 internal Oscillator Frequency Vramp_pp = 1.0V SP7652 internal Ramp Peak to Peak Amplitude Step by step design procedures: a. b. c. d. e. f. g. h. l. fco = 600khz / 10 = 60khz fp_LC = 1 / 2π [(1.5uH) (330uF)] ^ 1/2 ≈ 7khz fz_ESR = 1 / 2π (10mΩ) (330uF) ≈ 50khz R1 = 68.1kΩ, 1% R2 = 68.1kΩ / [(3.30V / 0.80V) – 1] ≅ 21.5kΩ, 1% Rz = 68.1kΩ (1.0V / 15V) (60khz) [50khz / (7khz) ^ 2] ≈ 280kΩ, 1% Cz = 1 / 0.1 (2π) (280kΩ) (7khz) ≈ 820pF, COG Cp = 1 / π (280kΩ) (600khz) ≈ 2.2pF Cf1 = 100pF to stabilize SP7652EU internal Error Amplify +5V OUTPUT WITH A TYPE II COMPENSATION APPLICATION SCHEMATIC SP7652EU with Tantalum output capacitor configures for Vin = 12V, Vout = +5V at 0-8A output current. Figure 16 and 17 show output voltage ripple less than 53mV at no load to 8A load. Figure 18 and 19 show typical 92% efficiency and 0.3% load regulation plots with a Type II compensation application circuits. 10 Figure 15. SP7652EU with Tantalum Output Capacitor Configures for +5V Output Vout ripple = 35mV Vout ripple = 53mV Vin Vin Ichoke(5A/div) Ichoke(5A/div) Figure 16. Output Ripple: No Load Figure 17. Output Ripple: 8A Load Vin=12V Vout=5.0V Vin=12V Vout=5.0V Figure 18. Efficiency vs Load Figure 19. Load Regulation 11 +5V INPUT WITH A TYPE II COMPENSATION APPLICATION SCHEMATIC SP7652EU with Tantalum output capacitor configures for Vin = 5V, Vout = +3.3V at 08A output current. Figure 21 and 22 show output voltage ripple less than 30mV at no load to 8A load. Figure 23 and 24 show typical 94% efficiency and 0.3% load regulation plots with a Type II compensation application circuits. Figure 20. SP7652EU with Tantalum Output Capacitor Configures for +5V Input Vout ripple = 16mV Vout ripple = 30mV Vin Vin Ichoke(5A/div) Ichoke(5A/div) Figure 21. Output Ripple: No Load Figure 22. Output Ripple: 8A Load 12 Vin=5.0V Vout=3.3V Vin=5.0V Vout=3.3V Figure 23. Efficiency vs Load Figure 24. Load Regulation PC LAYOUT DRAWINGS Figure 25. SP7652EB Component Placement 13 Figure 26. SP7652EB PC Layout Top Side Figure 27. SP7652EB PC Layout 2nd Layer Side Figure 28. SP7652EB PC Layout 3rd Layer Side 14 Figure 29. SP7652EB PC Layout Bottom Side Table 2: SP7652EB List of Materials ORDERING INFORMATION Model Temperature Range Package Type SP7652EB…................................-40°C to +85°C...............…SP7652 Evaluation Board SP7652EU..............................…. -40°C to +85°C.................................……26-pin DFN 15