SP800LEP

® SP691A/693A/800L/800M Low Power Microprocessor Supervisory with Battery Switch-Over FEATURES ■ Precision 4.65V/4.40V Voltage Monitoring ■ 200ms Or Adjustable Reset Time ■ 100ms, 1.6s Or Adjustable Watchdog Time ■ 60µA Maximum Operating Supply Current ■ 2.0µA Maximum Batter y Backup Current ■ 0.1µA Maximum Batter y Standby Current ■ Power Switching 250mA Output in Vcc Mode (0.6Ω) 25mA Output in Batter y Mode (5Ω) ■ On-Board Gating of Chip-Enable Signals Memor y Write-Cycle Completion 6ns CE Gate Propagation Delay ■ Voltage Monitor for Power-Fail or Low Batter y ■ Backup-Batter y Monitor ■ RESET Valid to Vcc=1V ■ 1% Accuracy Guaranteed (SP800L/800M) ■ Pin Compatible Upgrade to MAX691A/693A/ 800L/800M VBATT VOUT Vcc GND BATT ON LOWLINE OSCIN OSCSEL 1 2 3 4 Corporation TOP VIEW 16 RESET 15 RESET 14 WDO 13 CEIN 12 CEOUT 11 WDI 10 9 5 6 7 8 PFO PFI DIP/SO Now Available in Lead Free Packaging DESCRIPTION The SP691A/693A/800L/800M is a microprocessor (µP) supervisory circuit that integrates a myriad of components involved in discrete solutions to monitor power-supply and battery-control functions in µP and digital systems. The SP691A/693A/800L/800M offers complete µP monitoring and watchdog functions. The SP691A/693A/800L/800M is ideal for a low-cost battery management solution and is well suited for portable, battery-powered applications with its supply current of 35µA. The 6ns chip-enable propagation delay, the 25mA current output in battery-backup mode, and the 250mA current output in standard operation also makes the SP691A/693A/800L/800M suitable for larger scale, high-performance equipment. Part Number SP691A SP693A SP800L SP800M RESET Threshold 4.65V 4.40V 4.65V 4.40V RESET Accuracy +125mV +125mV +50mV +50mV PFI Accuracy +4% +4% +1% +1% Backup-Battery Switch YES YES YES YES Date: 4/18/05 SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over © Copyright 2005 Sipex Corporation 1 These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. Terminal Voltages (with respect to GND) VCC.......................................................................................-0.3V to +6V VBATT.....................................................................................-0.3V to +6V All Other Inputs........................................................-0.3V to (VCC +0.3V) Input Currents VCC Peak...........................................................................................1.0A VCC Continuous.............................................................................250mA VBATT Peak....................................................................................250mA VBATT Continuous............................................................................25mA GND, BATT ON............................................................................100mA All Other Inputs..............................................................................25mA ABSOLUTE MAXIMUM RATINGS Enhanced ESD Specifications........................+4kV Human Body Model Power Dissipation Per Package 16-pin PDIP (derate 14.3mW/OC above +70OC).......................1150mW 16-pin Narrow SOIC (derate 13.6mW/OC above 70OC)............1090mW 16-pin Wide SOIC (derate 11.2mW/OC above 70OC).................900mW Storage Temperature....................................................-65OC to +150OC Lead Temperature (soldering,10 sec).........................................+300OC ELECTRICAL CHARACTERISTICS VCC = +4.75V to +5.5V for the SP691A/800L, VCC = +4.5V to +5.5V for the SP693A/800M, VBATT = +2.8V, and TAMB = TMIN to TMAX unless otherwise noted. Typical values apply at TAMB=+25OC. PARAMETERS Operating Voltage Range, VCC or VBATT, NOTE 1 Output Voltage, VOUT in Normal Operating Mode MIN. 0 VCC-0.05 VCC-0.3 VCC-0.2 TYP. MAX. 5.5 UNITS CONDITIONS V VCC=4.5V, IOUT=25mA VCC=4.5V, IOUT=250mA VCC=3.0V, VBATT=2.8V, IOUT=100mA VCC=4.5V VCC=3.0V VBATT=4.5V, IOUT=20mA VBATT=2.8V, IOUT=10mA VBATT=2.0V, IOUT=5mA VBATT=4.5V VBATT=2.8V VBATT=2.0V VCC>(VBATT-1V), excluding IOUT VCC(VBATT+0.2V), excluding IOUT power-up power-down Peak to Peak VCC-0.015 VCC-0.15 VCC-0.09 0.6 0.9 1.2 2.0 V VCC-to-VOUT On-Resistance VOUT in Battery-Backup Mode VBATT-0.3 VBATT-0.25 VBATT-0.15 Ω VBATT-0.1 VBATT-0.07 VBATT-0.05 5 7 10 35 15 25 30 60 V VBATT-to-VOUT On-Resistance Ω Supply Current in Normal Operating Mode, IVcc Supply Current in BatteryBackup Mode, IBATT, NOTE 2 VBATT Standby Current, IBATT, NOTE 3 Battery Switchover Threshold -0.1 µA µA µA 0.001 2.0 0.02 VBATT+0.03 VBATT-0.03 60 V mV Battery Switchover Hysteresis Date: 4/18/05 SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over © Copyright 2005 Sipex Corporation 2 VCC = +4.75V to +5.5V for the SP691A/800L, VCC = +4.5V to +5.5V for the SP693A/800M, VBATT = +2.8V, and TAMB = TMIN to TMAX unless otherwise noted. Typical values apply at TAMB=+25OC. ELECTRICAL CHARACTERISTICS PARAMETERS BATT ON Output Low Voltage BATT ON Output Short Circuit Current MIN. TY P . 0.1 0 .7 MA X . 0.4 1.5 100 UNITS CONDITIONS V mA µA ISINK=3.2mA ISINK=25mA sink current source current 1 60 15 RESET, LOWLINE, AND WATCHDOG TIMER Reset Threshold Voltage 4.50 4.25 4.60 4.35 4.65 4.40 4.65 4.40 15 80 800 140 200 280 4.75 4.50 4.70 4.45 SP691A SP693A SP800L SP800M center-to-peak power down power down power-up V Reset Threshold Hysteresis VCC to RESET Delay LOWLINE to RESET Delay Reset Active Timeout Period for the Internal Oscillator Reset Active Timeout Period for the External Clock, N O TE 4 Watchdog Timeout Period for the Internal Oscillator Watchdog Timeout Period for the External Clock, NOTE 4 Minimum Watchdog Input Pulse Width RESET Output Voltage 3 .5 RESET Output Short-Circuit Current RESET Output Voltage Low, NOTE 5 LOWLINE Output Voltage 3.5 LOWLINE Output Short Circuit Current WDO Output Voltage 3.5 WDO Output Short-Circuit Current Date: 4/18/05 mV µs ns ms 2048 1 .0 70 1 .6 100 4096 1024 100 0.004 0.1 0 .3 0.4 2.25 140 clock power-up cycles sec ms long period short period clock long period cycles short period ns VIL=0.8V,VIH=0.75xVCC ISINK=50µA, VCC=1V, VCC falling ISINK=3.2mA, VCC=4.25V ISOURCE=1.6mA, VCC=5V output source current ISINK=3.2mA ISINK=3.2mA, VCC=4.25V ISOURCE=1µA, VCC=5V output source current ISINK=3.2mA ISOURCE=500µA, VCC=5V output source current V 7 0.1 0 .1 20 0.4 0.4 mA V V µA V mA 15 0 .1 100 0.4 3 10 SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over © Copyright 2005 Sipex Corporation 3 ELECTRICAL CHARACTERISTICS VCC = +4.75V to +5.5V for the SP691A/800L, VCC = +4.5V to +5.5V for the SP693A/800M, VBATT = +2.8V, and TAMB = TMIN to TMAX unless otherwise noted. Typical values apply at TAMB=+25OC. PARAMETERS WDI Threshold Voltage, NOTE 6 WDI Input Current MIN. 0.75xVCC TYP. M AX . UNITS V µA CONDITIONS VIH VIL WDI=0V WDI=VOUT 0.8 -50 -10 20 50 POWER-FAIL COMPARATOR PFI Input Threshold 1.237 1.200 1.25 1.25 +0.01 0.1 1.263 1.300 1.225 PFI Leakage Current PFO Output Voltage 3.5 PFO Short Circuit Current 1 PFI-to-PFO Delay 1.275 +25 0.4 V nA V mA SP691A/693A, VCC=5V SP800L/800M, VCC=5V ISINK=3.2mA ISOURCE=1µA, VCC=5V output sink current output source current VOD=15mV VOD=15mV 60 15 25 60 100 µA µs CHIP-ENABLE GATING CEIN Leakage Current CEIN to CEOUT Resistance, NOTE 7 CEOUT Short-Circuit Current (RESET Active) CEIN to CEOUT Propagation Delay, NOTE 8 CEOUT Output Voltage High (RESET Active) RESET to CEOUT Delay INTERNAL OSCILLATOR OSCIN Leakage Current OSCIN Input Pull-Up Current OSCSEL Input Pull-Up Current OSCIN Frequency Range OSCIN External Oscillator Threshold Voltage OSCIN Frequency with External Capacitor VOUT-0.3 0.10 10 10 200 VOUT-0.6 3.65 2 +5.0 100 100 µA µA µA kHz V OSCSEL=0V OSCSEL=VOUT or floating, OSCIN=0V OSCSEL=0V OSCSEL=0V VIH VIL OSCSEL=0V, COSC=47pF 3.5 2.7 12 0.1 +0.005 65 +1 150 µA Ω mA disable mode enable mode 0.75 2.0 disable mode, CEOUT=0V 50Ω source impedance driver, CLOAD=50pF VCC=5V, IOUT= 100µA VCC=0V, VBATT=2.8V, IOUT=1µA power-down 6 10 ns V µs 2.0 kHz Date: 4/18/05 SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over © Copyright 2005 Sipex Corporation 4 ELECTRICAL CHARACTERISTICS VCC = +4.75V to +5.5V for the SP691A/800L, VCC = +4.5V to +5.5V for the SP693A/800M, VBATT = +2.8V, and TAMB = TMIN to TMAX unless otherwise noted. Typical values apply at TAMB=+25OC. NOTE 1: Either VCC or VBATT can go to 0V, if the other is greater than 2.0V. NOTE 2: The supply current drawn by the SP691A/693A/800L/800M from the battery (excluding IOUT) typically goes to 5µA when (VBATT - 1V) < VCC < VBATT. In most applications, this is a brief period as VCC falls through this region. NOTE 3: "+" = battery-discharging current, "-" = battery-charging current. NOTE 4: Although presented as typical values, the number of clock cycles for the reset and watchdog timeout periods are fixed and do not vary with process or temperature. NOTE 5: RESET is an open-drain output and sinks current only. NOTE 6: WDI is internally connected to a voltage divider between VOUT and GND. If unconnected, WDI is driven to 1.6V (typ), disabling the watchdog function. NOTE 7: The chip-enable resistance is tested with VCC = +4.75V for the SP691A/800L and VCC = +4.5V for the SP693A/800M. CEIN = CEOUT = VCC/2. NOTE 8: The chip-enable propagation delay is measured from the 50% point at CEIN to the 50% point at CEOUT. TYPICAL PERFORMANCE CHARACTERISTICS (TAMB = 25 C, unless otherwise noted) o 2.5 43 40 VCC Current (µA) 37 34 31 28 25 -60 VCC = 5V VBATT = 2.8V VBATT Current (µA) 2.0 1.5 1.0 0.5 0.0 -0.5 -30 0 30 60 90 Temperature (oC) 120 -60 -30 0 30 60 90 Temperature (oC) 120 150 VCC = 1.6V VBATT = 2.8V Figure 1. VCC Supply Current vs. Temperature (Normal Operating Mode) Figure 2. Battery Supply Current vs. Temperature (Battery-Backup Mode) 75.0 CE-IN Resistance (Ω) 70.0 65.0 60.0 55.0 50.0 45.0 40.0 -80 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (oC) VCC = 4.75V VBATT = 2.8V CE IN = VCC/2 14 12 10 Resistance (Ω) 8 6 4 2 0 -60 -30 0 VBATT = 2V VBATT = 2.8V VBATT = 4.5V 30 60 90 Temperature (oC) 120 150 VCC = 0V Figure 3. Chip-Enable On-Resistance vs. Temperature Date: 4/18/05 Figure 4. VBATT to VOUT On-Resistance vs. Temperature SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over © Copyright 2005 Sipex Corporation 5 TYPICAL PERFORMANCE CHARACTERISTICS 1.256 0.9 Resistance (Ω) VCC = 4.5V VBATT = 2.8V PFI Threshold (V) 1.252 1.248 1.244 1.240 1.236 -30 0 30 60 90 Temperature (oC) 120 150 -60 -30 0 30 60 90 Temperature (oC) 120 150 VCC = 5V VBATT = 0V 0.7 0.5 0.3 -60 Figure 5. VCC to VOUT On-Resistance vs. Temperature Figure 6. PFI Threshold vs. Temperature 4.69 4.68 Reset Threshold (V) 4.67 VBATT = 0V 400 350 300 VCC Rising VCC Falling Resistance (Ω) 250 200 150 100 50 Sourcing VCC = 5V Sinking VCC = 4.25V 4.66 4.65 4.64 4.63 4.62 4.61 4.60 -60 -30 0 30 60 90 Temperature (oC) 120 150 0 -60 -30 0 30 60 90 Temperature (oC) 120 150 Figure 7. Reset Threshold vs. Temperature Figure 8. RESET Output Resistance vs. Temperature 0.240 Reset Timeout Period (s) 0.230 0.220 0.210 0.200 0.190 0.180 -60 VBATT Current (A), Log Scale VCC = 5V VBATT = 2.8V 1.E-04 1.E-05 1.E-06 1.E-07 1.E-08 1.E-09 1.E-10 1.E-11 1.E-12 1.E-13 1.E-14 -30 0 30 60 90 Temperature (oC) 120 150 0 1 2 VCC (V) 3 4 5 VBATT = 2.8V Figure 9. Reset Delay vs. Temperature Date: 4/18/05 Figure 10. Battery Current vs. Input Supply Voltage SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over © Copyright 2005 Sipex Corporation 6 TYPICAL PERFORMANCE CHARACTERISTICS 1000 100 Propagation Delay (µs) Watchdog and Reset Timeout Period (s) Long Watchdog Timeout Period Reset Active Timeout Period Short Watchdog Timeout Period 30 25 20 15 10 5 0 VCC = 5V VBATT = 2.8V 50Ω driver 10 1 VCC = 5V VBATT = 2.8V 0.1 10 100 1000 OSCIN Capacitor (pF) 10000 0 50 100 150 200 Cload (pF) 250 300 350 Figure 11. Watchdog and Reset Timeout Period vs. OSCIN Timing Capacitor (COSC) Figure 12. Chip-Enable Propagation Delay vs. CEOUT Load Capacitance 1000 1000 Voltage Drop (mV) Voltage Drop (mV) 100 100 10 VCC = 4.5V VBATT = 0V Slope = 0.6Ω 10 VCC = 4.5V VBATT = 0V Slope = 5Ω 1 1 10 IOUT (mA) 100 1000 1 1 10 IOUT (mA) 100 1000 Figure 13. VCC to VOUT vs. Output Current (Normal Operating Mode) Figure 14. VBATT to VOUT vs. Output Current (BatteryBackup Mode) VCC Reset Threshold RESET LOWLINE +5V 0V 80µs HI LOW 1.1µs HI LOW 16µs HI CEOUT LOW Figure 15. VCC to LOWLINE and CEOUT Delay Date: 4/18/05 SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over © Copyright 2005 Sipex Corporation 7 PINOUT TOP VIEW VBATT VOUT Vcc GND BATT ON LOWLINE OSCIN OSCSEL 1 2 3 4 Corporation 16 RESET 15 RESET 14 WDO 13 CEIN 12 CEOUT 11 WDI 10 9 5 6 7 8 PFO PFI Pin 7 — OSCIN — External Oscillator Input. When OSCSEL is unconnected or driven HIGH, a 10µA pull-up connects from VOUT to this input pin, the internal oscillator sets the reset and watchdog timeout periods, and this input pin selects between fast and slow watchdog timeout periods. When OSCSEL is driven LOW, the reset and watchdog timeout periods may be set either by a capacitor from this input pin to ground or by an external clock at this pin (refer to Figure 21). Pin 8 — OSCSEL — Oscillator Select. When OSCSEL is unconnected or driven HIGH, the internal oscillator sets the reset delay and watchdog timeout period. When OSCSEL is driven LOW, the external oscillator input pin, OSCIN, is enabled (refer to Table 1). This input pin has a 10µA internal pull-up. Pin 9 — PFI — Power-Fail Input. This is the n o n i nv e r t i n g i n p u t t o t h e p ow e r - f a i l comparator. When PFI is less than 1.25V, PFO goes low. Connect PFI to GND or VOUT when not used. Pin 10 — PFO — Power-Fail Output. This is the output of the power-fail comparator. PFO goes low when PFI is less than 1.25V. This is an uncommitted comparator, and has no effect on any other internal circuitry. Pin 11 — WDI — Watchdog Input. This is a three-level input pin. If WDI remains either HIGH or LOW for longer than the watchdog timeout period, WDO goes LOW and RESET is asserted for the reset timeout period. WDO remains LOW until the next transition at this input pin. Leaving this input pin unconnected disables the watchdog function. This input pin connects to an internal voltage divider between VOUT and ground, which sets it to mid-supply when left unconnected. DIP/SO PIN ASSIGNMENTS Pin 1 — VBATT — Battery-Backup Input. Connect to the external battery supply or supercharging capacitor and charging circuit. If a backup battery is not provided, connect this pin to ground. Pin 2 —VOUT — Output Supply Voltage. VOUT connects to VCC when VCC is greater than VBATT and VCC is above the reset threshold. When VCC falls below VBATT and VCC is below the reset threshold, VOUT connects to VBATT. Connect a 0.1µF capacitor from VOUT to GND. Pin 3 — VCC — +5V Input Supply Voltage. Pin 4 — GND — Ground reference for all signals. Pin 5 — BATT ON — Battery On Output. Goes high when VOUT switches to VBATT. Goes low when VOUT switches to VCC. Connect the base of a PNP through a current-limiting resistor to BATT ON for VOUT current requirements greater than 250mA. Pin 6 — LOWLINE — Low Line Output. This output pin goes LOW when VCC falls below the reset threshold voltage. This output pin returns to its HIGH output as soon as VCC rises above the reset threshold voltage. Date: 4/18/05 SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over © Copyright 2005 Sipex Corporation 8 Pin 12 — CEOUT — Chip-Enable Output. This output pin goes LOW only when CEIN is LOW and VCC is above the reset threshold voltage. If CEIN is LOW when RESET is asserted, this output pin will stay low for 16µs or until CEIN goes HIGH, whichever occurs first. Pin 13 — CEIN — Chip-Enable Input. This is the input pin to the chip-enable gating circuit. If this input pin is not used, connect it to ground or VOUT. Pin 14 — WDO — Watchdog Output. If WDI remains HIGH or LOW longer than the watchdog timeout period, this output pin goes LOW and RESET is asserted for the reset timeout period. This output pin returns HIGH on the next transition at WDI. This output pin remains HIGH if WDI is unconnected. Pin 15 — RESET — Active LOW Reset Output. This output pin goes LOW whenever VCC falls below the reset threshold. This output pin will remain low typically for 200ms after VCC crosses the reset threshold voltage on power-up. Pin 16 — RESET — Active HIGH Reset Output. This output pin is open drain and the inverse of RESET. PFI 9 10 PFO WDI 11 Watchdog Transition Detector 1.25V Watchdog Timer 14 15 Reset Generator CEOUT Control 6 16 WDO RESET RESET OSCSEL OSCIN 8 7 Reset / Watchdog Timebase 4.65V or 4.40V* LOWLINE VCC 3 2 VOUT 5 BATT ON VBATT CEIN 1 13 * 4.65V for the SP691A/800L 4.40V for the SP693A/800M 4 GND 12 CEOUT Figure 16. Internal Block Diagram of the SP691A/693A/800L/800M Date: 4/18/05 SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over © Copyright 2005 Sipex Corporation 9 Unregulated DC R1 Regulated +5V R2 VCC VCC µP RESET NMI A0-A15 I/O LINE Backup Supply BUS PFI RESET PFO WDI VBATT WDO alarm system status indicator LOWLINE Address Decode BATT ON CEIN CMOS RAM1 to RAMn VCC VOUT CEOUT 0.1µF GND Figure 17. Typical Application Circuit of the SP691A/693A/800L/800M FEATURES The SP691A/693A/800L/800M devices are microprocessor (µP) supervisory circuits that monitor the power supplied to digital circuits such as microprocessors, microcontrollers, or memory. The SP691A/693A/800L/800M series is an ideal solution for portable, batterypowered equipment that require power supply monitoring. The SP691A/693A/800L/800M watchdog functions will continuously oversee the operational status of a system. Implementing the SP691A/693A/800L/800M series will reduce the number of components and overall complexity in a design that requires power supply monitoring circuitry. The operational features and benefits of this series are described in more detail below. Date: 4/18/05 THEORY OF OPERATION The SP691A/693A/800L/800M series is a complete µP supervisor IC and provides the following main functions: 1) µP reset ➡ Reset output is asserted during p ow e r f l u x i a t i o n s s u c h a s p ow e r- u p , power-down, and brown out conditions, and is guaranteed to be in the correct state for VCC down to 1V, even with no battery in the circuit. 2) µP reset ➡ Reset output is pulsed if the optional watc hdog timer has not been toggled within a specified time. 3) Power Fail Comparator ➡ Pr ovides for p ow e r- f a i l w a r n i n g a n d l ow - b a t t e r y d e t e c t i o n , o r m o n i t o r s a n o t h e r p ow e r supply. 10 SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over © Copyright 2005 Sipex Corporation 4) Watchdog function ➡ Monitors µP activity where the watchdog output goes to a logic LOW state if the watchdog input is not toggled for greater than the timeout period. 5) Internal switch ➡ Switches over from VCC to VBATT if the VCC falls below the reset threshold. RESET and RESET Outputs T h e S P 6 9 1 A / 6 9 3 A / 8 0 0 L / 8 0 0 M d ev i c e s ' RESET and RESET outputs ensure that the µP p ow e r s u p i n a k n ow n s t a t e , a n d p r eve n t s code-execution errors during power-down or brownout conditions. The RESET output is active low, and typically sinks 3.2mA at 0.1V saturation voltage in its active state. When deasserted, RESET sources 1.6mA at typically VOUT – 0.5V. RESET output is open drain, active high, and typically sinks 3.2mA with a saturation voltage of 0.1V. When no backup battery is used, RESET output is guaranteed to be valid down to VCC = 1V, and an external 10kΩ pull-down resistor on RESET ensures that RESET will be valid with VCC down to GND as shown on Figure 18. As VCC goes below 1V, the gate drive to the RESET output switch reduces accordingly, increasing the RDS(ON) and the saturation voltage. The 10kΩ pull-down resistor ensures the parallel combination of switch plus resistor is around RESET 15 10kΩ TO µP RESET Corporation Figure 18. External Pull-down Resistor Ensures RESET is Valid with VCC Down to Ground. 10kΩ and the output saturation voltage is below 0.4V while sinking 40µA. When using a 10kΩ external pull-down resistor, the high state for the RESET output with Vcc = 4.75V is 4.5V typical. For battery voltages less than or equal to 2V connected to VBATT, RESET and RESET remains valid for VCC from 0V to 5.5V. RESET and RESET are asserted when VCC falls below the reset threshold and remain asserted for the Reset Timeout Period (200ms nominal) after VCC rises above the reset threshold voltage on power-up. Refer to Figure 19. The devices' battery-switchover comparator does not affect reset assertion. However, both reset outputs are asserted in battery-backup mode since VCC must be below the reset threshold to enter this mode. Vcc RESET THRESHOLD CE IN CE OUT 12µ 100µs 100µs RESET RESET Figure 19. Reset and Chip-Enable Timing Date: 4/18/05 SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over © Copyright 2005 Sipex Corporation 11 WDI WDO t2 RESET t1 t1 t3 t1 = RESET Timeout Period t2 = Normal Watchdog Timeout Period t3 = Watchdog Timeout Period Immediately After RESET Figure 20. Watchdog Timeout Period and Reset Active Time Watchdog Function The watchdog monitors µP activity via the Watchdog Input (WDI). If the µ P becomes i n a c t ive , R E S E T a n d R E S E T a r e a s s e r t e d . To use the watchdog function, connect WDI to a bus line or µP I/O line. If WDI remains high or low for longer than the watchdog timeout period (1.6s nominal). WDO, RESET, and RESET are asserted, indicating a software fault or idle conditions. Refer to RESET and RESET Outputs and Watchdog Output sections. Watchdog Input A change of logic state (minimum 100ns duration) at WDI during the watchdog period will reset the watchdog timer. The watchdog default timout is 1.6sec. To disable the watchdog function, leave WDI floating. An internal resistor network (100kΩ equivalent impedance at WDI) biases WDI to a p p r o x i m a t e l y 1 . 6 V. I n t e r n a l c o m p a r a t o r s detect this level and disable the watchdog timer. When Vcc is below the reset threshold, the wa t c h d o g f u n c t i o n i s d i s a b l e d a n d W D I i s disconnected from its internal resistor network, thus becoming high impedance. Watchdog Output WDO remains high if there is activity (transition or pulse) at WDI during the watchdog-timeout period. The watchdog function is disabled and WDO is a logic high when VCC is less than the reset threshold or when WDI is an open circuit. In watchdog mode, if no transition occurs at W D I d u r i n g t h e wa t c h d o g - t i m e o u t p e ri o d , Date: 4/18/05 7 OSCIN X No Connect X No Connect 8 OSCSEL 1.6sec Normal Watchdog Timeout Internal Oscillator 7 OSCIN 8 OSCSEL X No Connect 100ms Normal Watchdog Timeout Internal Oscillator CIN 7 OSCIN 8 OSCSEL Normal Watchdog Timeout = 600 x CIN [ms] 47pF External Oscillator 7 OSCIN 8 OSCSEL Normal Watchdog Timeout = 1024 Clock Periods External Clock Figure 21. Selecting Timeout Periods SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over © Copyright 2005 Sipex Corporation 12 Watchdog Timeout Period OSCSEL LOW LOW Floating Floating OSCIN Normal External Clock Input External Capacitor LOW Floating 1024 clocks (600/47pF x C) ms 100 ms 1.6 s Immediately After Reset 4096 clocks (2.4 /47 pf x C) sec 1.6 s 1.6 s 2048 clocks (1200/47pF x C) ms 200 ms 200 ms Reset Timeout Period Table 1. Reset Pulse Width and Watchdog Timeout Selections RESET and RESET are asserted for the reset timeout period (200ms nominal). WDO goes to logic low and remains low until the next transition at WDI. Refer to Figure 20. If WDI is held high or low indefinitely, RESET and RESET will generate 200ms pulses every 1.6s. WDO has a 2 x TTL output characteristic. S e l e c t i n g a n A l t e r n a t i v e Wa t c h d o g Timeout Period T h e O S C SEL a n d O S C IN i n p u t s c o n t r o l t h e watchdog are reset timeout periods. Floating OSCSEL and OSCIN or tying them both to VOUT s e l e c t s t h e n o m i n a l 1 . 6 s wat c h d o g t i m e o u t period and 200ms reset timout period. Connecting OSCIN to ground and floating or connecting OSCSEL to VOUT selects a 100ms normal watchdog timeout period and a 1.6s timeout period immediately after reset. The reset timeout period remains 200ms. Refer to Figure 20. Select alternative timeout periods by connecting OSCSEL to ground and connecting a capacitor between OSCIN and ground, or by externally driving OSCIN . A synopsis of this control can be found in Figure 21 and Table 1. Chip-Enable Signal Gating T h e S P 6 9 1 A / 6 9 3 A / 8 0 0 L / 8 0 0 M d ev i c e s provide internal gating of chip-enable (CE) s i g n a l s , t o p r ev e n t e r r o n e o u s d a t a f r o m corrupting the CMOS RAM in the event of a power failure. During normal operation, the CE gate is enabled and passes all CE transitions. When reset is asserted, this path becomes d i s a b l e d , p r ev e n t i n g e r r o n e o u s d a t a f r o m corrupting the CMOS RAM. The SP691A/ 693A/800L/800M devices use a series transmission gate from CEIN to CEOUT. Refer to Figure 16. Date: 4/18/05 The 10ns maximum CE propagation from CEIN t o C E OUT e n a b l e s t h e S P 6 9 1 A / 6 9 3 A / 8 0 0 L / 800M devices to be used with most µPs. Chip-Enable Input CEIN is in high impedance (disabled mode) while RESET and/or RESET are asserted. During a power-down sequence where VCC falls below the reset threshold, CEIN assumes a high impedance state when the voltage at CEIN goes high or 12µs after RESET is asserted, whichever occurs first. Refer to Figure 19. During a power-up sequence, CEIN remains high impedance until RESET is deasserted. In the high-impedance mode, the leakage currents into CEIN are