ST16C550IJ44

ST16C550 -UART With 16-Byte FIFOs HomeNewsCareers Investor Relations Contact Us PartnerNet Login Search CommunicationsInterfacePower Management ST16C550 Support Info Request How to Order Samples How to Buy Print this page UART With 16-Byte FIFOs Specifications Features CH 1 CPUInterface Intel ● ● ● ● Design ● ● ● Technical Documentation ● ● ● Technical FAQs ● ● Pin to pin and functionally compatible to the Industry Standard 16C550 24MHz clock operation at 5V 16MHz clock operation at 3.3V 16 byte transmit FIFO 16 byte receive FIFO with error flags Full duplex operation Transmit and receive control Four selectable receive FIFO interrupt trigger levels Standard modem interface Compatible with ST16C450 Low operating current ( 1.2mA typ.) Pb-Free, RoHS Compliant Versions Offered Product Finder Data Rate@5/3.3/2.5V 1.5/1.0/na Tx/RxFIFO(Bytes) 16/16 Tx/RxFIFOCtrs No Tx/RxFIFOINT Trig No/ 4 Levels AutoRTS/CTS No IrDaSup No 5VTolInputs No Sup V 2.97-5.5 Pkgs PDIP-40, PLCC-44, TQFP-48 Product Tree Applications Documents Technical Support ● Packaging ● ● Evaluation Boards Cross References Product Change Notifications Obsolescence Interface Brochure IBIS Models BSDL ICI ● ● Battery Operated Electronics Internet Appliances Handheld Terminal Personal Digital Assistants Cellular Phones DataPort Datasheet Version 5.0.1 April 2005 241.16 KB Description Application Notes The ST16C550 is a universal asynchronous receiver and transmitter with 16 byte transmit and receive FIFO. A programmable baud rate generator is pro- vided to select transmit and receive clock rates from 50 bps to 1.5 Mbps. DAN-108, UART Crystal Oscillator Design Guide Version 1.0.0 March 2000 58.16 KB The ST16C550 is an improved version of the NS16C550 UART with higher operating speed and lower access time. The ST16C550 on board status registers provides the error conditions, type and status of the transfer operation being performed. Included is complete MODEM control capability, and a processor interrupt system that may be software tailored to the user’s requirements. The ST16C550 provides internal loop-back capability for on board diagnostic testing. AN-450/AN-550, ST16C450/550 Application Example Version 1.0.0 December 1996 44.16 KB The ST16C550 is available in 40-pin PDIP, 44-pin PLCC, and 48-pin TQFP packages. It is fabricated in an advanced 0.6m CMOS process to achieve low drain power and high speed requirements. DAN-132, EXAR's ST16C550 vs. TL16C550C Version 1.0.0 June 2002 121.52 KB UART Finder Quality and Reliability Datasheets http://www.exar.com/Common/Content/ProductDetails.aspx?ID=ST16C550 (1 of 2) [31-Jul-09 11:23:28 AM] ST16C550 -UART With 16-Byte FIFOs Quality & Reliability Homepage For UART technical support or to obtain an IBIS model for this product, please email Exar's UART Technical Support group. General UART Application Note Version 1.0.0 December 1996 39.81 KB show obsolete parts Material Declaration Sheets Quality Manual Quarterly Quality & Reliability Report RoHS-Green Solutions Part Number Pkg Code Min Max Buy Order RoHS Temp. Temp. Status Now Samples (°C) (°C) ST16C550CJ44-F PLCC44 0 70 Active ST16C550CQ48-F TQFP48 0 70 Active PLCC44 -40 85 Active ST16C550IQ48-F TQFP48 -40 85 Active ST16C550IJ44-F Part Status Legend Active - the part is released for sale, standard product. EOL (End of Life) - the part is no longer being manufactured, there may or may not be inventory still in stock. Related News 10/28/2002 Exar Adds 3.3V Two-Channel and FourChannel PCI UARTs to its Broad Data Communications Product Portfolio CF (Contact Factory) - the part is still active but customers should check with the factory for availability. Longer lead-times may apply. PRE (Pre-introduction) - the part has not been introduced or the part number is an early version available for sample only. OBS (Obsolete) - the part is no longer being manufactured and may not be ordered. Schematics ISA Eval Board Schematic Version 1.2.0 August 2007 81.36 KB ISA Eval Board Schematic Version 1.4.0 August 2007 77.56 KB Evaluation Board Manuals Evaluation Board User's Manual Version 1.1.0 October 2003 14.34 KB NRND (Not Recommended for New Designs) - the part is not recommended for new designs. © 2000-2009 Exar Corporation, Fremont California, U.S.A.Terms of Use | Site Map http://www.exar.com/Common/Content/ProductDetails.aspx?ID=ST16C550 (2 of 2) [31-Jul-09 11:23:28 AM] ST16C550 UART WITH 16-BYTE FIFO’s April 2005 GENERAL DESCRIPTION D4 D3 D2 D1 D0 N.C. VCC -RI -CD -DSR -CTS 6 5 4 3 2 1 44 43 42 41 40 PLCC Package D5 7 39 RESET D6 8 38 -OP1 D7 9 37 -DTR RCLK 10 36 -RTS RX 11 35 -OP2 N.C. 12 34 N.C. TX 13 33 INT CS0 14 32 -RXRDY CS1 15 31 A0 -CS2 16 30 A1 -BAUDOUT 17 29 A2 18 19 20 21 22 23 24 25 26 27 28 XTAL2 -IOW IOW GND N.C. -IOR IOR -DDIS -TXRDY -AS ST16C550CJ44 XTAL1 The ST16C550 (550) is a universal asynchronous receiver and transmitter with 16 byte transmit and receive FIFO. It operates at 2.97 to 5.5 volts. A programmable baud rate generator can select transmit and receive clock rates from 50 bps to 1.5 Mbps. The ST16C550 is an improved version of the NS16C550 UART with higher operating speed and lower access time. The ST16C550 on board status registers provides the error conditions, type and status of the transfer operation being performed. Included is complete MODEM control capability, and a processor interrupt system that may be software tailored to the user’s requirements. The ST16C550 provides internal loopback capability for on board diagnostic testing. The ST16C550 is available in 40 pin PDIP, 44 pin PLCC, and 48 pin TQFP packages. It is fabricated in an advanced CMOS process to achieve low drain power and high speed requirements. FEATURES • Pin to pin and functionally compatible to the Industry Standard 16C550 • 2.97 to 5.5 volt operation • 24MHz clock operation at 5V • 16MHz clock operation at 3.3V • 16 byte transmit FIFO • 16 byte receive FIFO with error flags • Full duplex operation • Transmit and receive control • Four selectable receive FIFO interrupt trigger levels • Standard modem interface • Compatible with ST16C450 • Low operating current ( 1.2mA typ.) ORDERING INFORMATION Part number Package ST16C550CP40 ST16C550CJ44 ST16C550CQ48 ST16C550IP40 ST16C550IJ44 ST16C550IQ48 40-Lead 44-Lead 48-Lead 40-Lead 44-Lead 48-Lead PDIP PLCC TQFP PDIP PLCC TQFP Operating temperature Device Status 0° C to + 70° C 0° C to + 70° C 0° C to + 70° C -40° C to + 85° C -40° C to + 85° C -40° C to + 85° C Active. See the ST16C550CQ48 for new designs. Active Active Active. See the ST16C550IQ48 for new designs. Active Active Rev. 5.01 EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 • (510) 668-7000 • FAX (510) 668-7017 ST16C550 Figure 1, PACKAGE DESCRIPTION, ST16C550 N.C. 1 36 N.C. D5 2 35 RESET D6 3 34 -OP1 D7 4 33 -DTR RCLK 5 N.C. 6 RX 7 ST16C550CQ48 32 -RTS 31 -OP2 30 INT D0 1 40 VCC D1 2 39 -RI D2 3 38 -CD D3 4 37 -DSR D4 5 36 -CTS D5 6 35 RESET D6 7 34 -OP1 33 -DTR 32 -RTS 31 -OP2 30 INT D7 8 RCLK 9 ST16C550CP40 -CTS N.C. 37 -DSR -CD -RI VCC D0 D1 D2 D3 D4 40 Pin DIP Package 38 39 40 41 42 43 44 45 46 47 48 N.C. 48 Pin TQFP Package TX 8 29 -RXRDY RX 10 CS0 9 28 A0 TX 11 CS1 10 27 A1 CS0 12 29 -RXRDY -CS2 11 26 A2 CS1 13 28 A0 12 13 14 15 16 17 18 19 20 21 22 23 24 N.C. XTAL2 -IOW IOW GND -IOR IOR N.C. -DDIS -TXRDY -AS 25 XTAL1 -BAUDOUT N.C. Rev. 5.01 2 -CS2 14 27 A1 -BAUDOUT 15 26 A2 XTAL1 16 25 -AS XTAL2 17 24 -TXRDY -IOW 18 23 -DDIS IOW 19 22 IOR GND 20 21 -IOR ST16C550 Inter Connect Bus Lines & Control signals A0-A2 -AS CS0,CS1 -CS2 Register Select Logic D0-D7 -IOR,IOR -IOW,IOW RESET Data bus & Control Logic Figure 2, BLOCK DIAGRAM Transmit FIFO Registers Transmit Shift Register TX Receive FIFO Registers Receive Shift Register RX -DDIS Clock & Baud Rate Generator XTAL1 RCLK XTAL2 -BAUDOUT INT -RXRDY -TXRDY Interrupt Control Logic -DTR,-RTS -OP1,-OP2 Rev. 5.01 3 Modem Control Logic -CTS -RI -CD -DSR ST16C550 SYMBOL DESCRIPTION Symbol 40 Pin 44 48 Signal type A0 28 31 28 I Address-0 Select Bit Internal registers address selection. A1 27 30 27 I Address-1 Select Bit Internal registers address selection. A2 26 29 26 I Address-2 Select Bit Internal registers address selection. IOR 22 25 20 I Read data strobe. Its function is the same as -IOR (see IOR), except it is active high. Either an active -IOR or IOR is required to transfer data from 16C550 to CPU during a read operation. Connect to logic 0 when using -IOR. CS0 12 14 9 I Chip Select-0. Logical 1 on this pin provides the chip select0 function. Connect CS0 to logic 1 if using CS1 or -CS2. CS1 13 15 10 I Chip Select-1. Logical 1 on this pin provides the chip select1 function. Connect CS1 to logic 1 if using CS0 or -CS2. -CS2 14 16 11 I Chip Select -2. Logical 0 on this pin provides the chip select2 function. Connect to logic 0 if using CS0 or CS1. IOW 19 21 17 I Write data strobe. Its function is the same as -IOW (see IOW), but it acts as an active high input signal. Either -IOW or IOW is required to transfer data from the CPU to ST16C550 during a write operation. Connect to logic 0 when using -IOW. -AS 25 28 24 I Address Strobe. A logic 1 transition on -AS latches the state of the chip selects and the register select bits, A0-A2. This input is used when address and chip selects are not stable for the duration of a read or write operation, i.e., a microprocessor that needs to de-multiplex the address and data bits. If not required, the -AS input can be permanently tied to a logic 0. D0-D7 1-8 2-9 43-47 2-4 I/O Data Bus (Bi-directional) - These pins are the eight bit, tristate data bus for transferring information to or from the controlling CPU. D0 is the least significant bit and the first data bit in a transmit or receive serial data stream. 18 Pwr Signal and Power Ground. GND 20 22 Pin Description Rev. 5.01 4 ST16C550 SYMBOL DESCRIPTION Symbol 40 Pin 44 48 Signal type Pin Description -IOR 21 24 19 I Read data strobe (active low strobe). A logic 0 on this pin transfers the contents of the ST16C550 data bus to the CPU. Connect to logic 1 when using IOR. -IOW 18 20 16 I Write data strobe (active low strobe). A logic 0 on this pin transfers the contents of the CPU data bus to the addressed internal register. Connect to logic 1 when using IOW. INT 30 33 30 O Interrupt Request (active high). Interrupts are enabled in the interrupt enable register (IER), and when an interrupt condition exists. Interrupt conditions include: receiver errors, available receiver buffer data, transmit buffer empty, or when a modem status flag is detected. -RXRDY 29 32 29 O Receive Ready. When operating in the FIFO mode, one of two types of DMA signaling can be selected using the FIFO control register bit-3. When operating in the ST16C450 mode, only DMA mode “0” is allowed. Mode “0” supports single transfer DMA in which a transfer is made between CPU bus cycles. Mode “1” supports multi-transfer DMA in which multiple transfers are made continuously until the receiver FIFO has been emptied. In DMA mode “0” -RXRDY is low, when there is at least one character in the receiver FIFO or receive holding register. In DMA mode “1”, -RXRDY is low, when the trigger level or the time-out has been reached. -TXRDY 24 27 23 O Transmit Ready. When operating in the FIFO mode, one of two types of DMA signaling can be selected using the FIFO control register bit-3. When operating in the ST16C450 mode, only DMA mode “0” is allowed. Mode “0” supports single transfer DMA in which a transfer is made between CPU bus cycles. Mode “1” supports multi-transfer DMA in which multiple transfers are made continuously until the transmit FIFO has been filled. -BAUDOUT 15 17 12 O Baud Rate Generator Output. This pin provides the 16X clock of the selected data rate from the baud rate generator. The RCLK pin must be connected externally to -BAUDOUT when the receiver is operating at the same data rate. Rev. 5.01 5 ST16C550 SYMBOL DESCRIPTION Symbol 40 Pin 44 48 Signal type Pin Description -DDIS 23 26 22 O Drive Disable. This pin goes to a logic 0 when the external CPU is reading data from the ST16C550. This signal can be used to disable external transceivers or other logic functions. -OP1 34 38 34 O Output-1 (User Defined) - See bit-2 of modem control register (MCR bit-2). RESET 35 39 35 I Reset. (active high) - A logic 1 on this pin will reset the internal registers and all the outputs. The UART transmitter output and the receiver input will be disabled during reset time. (See ST16C550 External Reset Conditions for initialization details.) RCLK 9 10 5 I Receive Clock Input. This pin is used as external 16X clock input to the receiver section. External connection to Baudout pin is required in order to utilize the internal baud rate generator. -OP2 31 35 31 O Output-2 (User Defined). This pin provides the user a general purpose output. See bit-3 modem control register (MCR bit-3). VCC 40 44 42 Pwr XTAL1 16 18 14 I Crystal or External Clock Input - Functions as a crystal input or as an external clock input. A crystal can be connected between this pin and XTAL2 to form an internal oscillator circuit. An external 1 MΩ resistor is required between the XTAL1 and XTAL2 pins (see figure 3). Alternatively, an external clock can be connected to this pin to provide custom data rates (Programming Baud Rate Generator section). XTAL2 17 19 15 O Output of the Crystal Oscillator or Buffered Clock - (See also XTAL1). Crystal oscillator output or buffered clock output. -CD 38 42 40 I Carrier Detect (active low) - A logic 0 on this pin indicates that a carrier has been detected by the modem. Power Supply Input. Rev. 5.01 6 ST16C550 SYMBOL DESCRIPTION Symbol 40 Pin 44 48 Signal type Pin Description -CTS 36 40 38 I Clear to Send (active low) - A logic 0 on the -CTS pin indicates the modem or data set is ready to accept transmit data from the ST16C550. Status can be tested by reading MSR bit-4. This pin has no effect on the UART’s transmit or receive operation. -DSR 37 41 39 I Data Set Ready (active low) - A logic 0 on this pin indicates the modem or data set is powered-on and is ready for data exchange with the UART. This pin has no effect on the UART’s transmit or receive operation. -DTR 33 37 33 O Data Terminal Ready (active low) - A logic 0 on this pin indicates that the ST16C550 is powered-on and ready. This pin can be controlled via the modem control register. Writing a logic 1 to MCR bit-0 will set the -DTR output to logic 0, enabling the modem. This pin will be a logic 1 after writing a logic 0 to MCR bit-0, or after a reset. This pin has no effect on the UART’s transmit or receive operation. -RI 39 43 41 I Ring Indicator (active low) - A logic 0 on this pin indicates the modem has received a ringing signal from the telephone line. A logic 1 transition on this input pin will generate an interrupt. -RTS 32 36 32 O Request to Send (active low) - A logic 0 on the -RTS pin indicates the transmitter has data ready and waiting to send. Writing a logic 1 in the modem control register (MCR bit-1) will set this pin to a logic 0 indicating data is available. After a reset this pin will be set to a logic 1. This pin has no effect on the UART’s transmit or receive operation. RX 10 11 7 I Receive Data - This pin provides the serial receive data input to the ST16C550. A logic 1 indicates no data or an idle channel. During the local loop-back mode, the RX input pin is disabled and TX data is internally connected to the UART RX Input, internally, see figure 12. TX 11 13 8 O Transmit Data - This pin provides the serial transmit data from the ST16C550, the TX signal will be a logic 1 during reset, idle (no data). During the local loop-back mode, the TX pin is set to a logic 1 and TX data is internally connected to the UART RX Input, see figure 12. Rev. 5.01 7 ST16C550 GENERAL DESCRIPTION FUNCTIONAL DESCRIPTIONS The ST16C550 provides serial asynchronous receive data synchronization, parallel-to-serial and serial-toparallel data conversions for both the transmitter and receiver sections. These functions are necessary for converting the serial data stream into parallel data that is required with digital data systems. Synchronization for the serial data stream is accomplished by adding start and stops bits to the transmit data to form a data character (character orientated protocol). Data integrity is insured by attaching a parity bit to the data character. The parity bit is checked by the receiver for any transmission bit errors. The electronic circuitry to provide all these functions is fairly complex especially when manufactured on a single integrated silicon chip. The ST16C550 represents such an integration with greatly enhanced features. The ST16C550 is fabricated with an advanced CMOS process. Internal Registers The ST16C550 provides 12 internal registers for monitoring and control. These registers are shown in Table 3 below. These registers function as data holding registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control register (FCR), line status and control registers, (LCR/LSR), modem status and control registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM), and a user assessable scratchpad register (SPR). The ST16C550 is an upward solution that provides 16 bytes of transmit and receive FIFO memory, instead of 1 byte provided in the 16C450. The ST16C550 is designed to work with high speed modems and shared network environments, that require fast data processing time. Increased performance is realized in the ST16C550 by the larger transmit and receive FIFO’s. This allows the external processor to handle more networking tasks within a given time. The 4 selectable levels of FIFO trigger provided for maximum data throughput performance especially when operating in a multi-channel environment. The combination of the above greatly reduces the bandwidth requirement of the external controlling CPU, increases performance, and reduces power consumption. The ST16C550 is capable of operation to 1.5Mbps with a 24 MHz crystal or external clock input. With a crystal of 14.7464 MHz and through a software option, the user can select data rates up to 460.8Kbps or 921.6Kbps. Rev. 5.01 8 ST16C550 Table 2, INTERNAL REGISTER DECODE A2 A1 A0 READ MODE WRITE MODE General Register Set (THR/RHR, IER/ISR, MCR/MSR, LCR/LSR, SPR): 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Receive Holding Register Interrupt Enable Register Interrupt Status Register Line Control Register Modem Control Register Line Status Register Modem Status Register Scratchpad Register Transmit Holding Register Interrupt Enable Register FIFO Control Register Line Control Register Modem Control Register Reserved Reserved Scratchpad Register Baud Rate Generator Registers (DLL/DLM). Accessible only when LCR bit-7 is set to 1. 0 0 0 0 0 1 LSB of Divisor Latch MSB of Divisor Latch LSB of Divisor Latch MSB of Divisor Latch FIFO Operation The 16 byte transmit and receive data FIFO’s are enabled by the FIFO Control Register (FCR) bit-0. With 16C550 devices, the user can set the receive trigger level but not the transmit trigger level. The receiver FIFO section includes a time-out function to ensure data is delivered to the external CPU. An interrupt is generated whenever the Receive Holding Register (RHR) has not been read following the loading of a character or the receive trigger level has not been reached. characters than the programmed trigger level. Following the removal of a data byte, the user should recheck LSR bit-0 for additional characters. A Receive Time Out will not occur if the receive FIFO is empty. The time out counter is reset at the center of each stop bit received or each time the receive holding register (RHR) is read (see Figure 10, Receive Time-out Interrupt). The actual time out value is T (Time out length in bits) = 4 X P (Programmed word length) + 12. To convert the time out value to a character value, the user has to consider the complete word length, including data information length, start bit, parity bit, and the size of stop bit, i.e., 1X, 1.5X, or 2X bit times. Time-out Interrupts When two interrupt conditions have the same priority, it is important to service these interrupts correctly. Receive Data Ready and Receive Time Out have the same interrupt priority (when enabled by IER bit-0). The receiver issues an interrupt after the number of characters have reached the programmed trigger level. In this case the ST16C550 FIFO may hold more Example -A: If the user programs a word length of 7, with no parity and one stop bit, the time out will be: T = 4 X 7( programmed word length) +12 = 40 bit times. The character time will be equal to 40 / 9 = 4.4 characters, or as shown in the fully worked out ex- Rev. 5.01 9 ST16C550 For internal clock oscillator operation, an industry standard microprocessor crystal (parallel resonant/ 22 pF load) is connected externally between the XTAL1 and XTAL2 pins, with an external 1 MΩ resistor across it. Alternatively, an external clock can be connected to the XTAL1 pin to clock the internal baud rate generator for standard or custom rates. See figure 3 for crystal oscillator connection. ample: T = [(programmed word length = 7) + (stop bit = 1) + (start bit = 1) = 9]. 40 (bit times divided by 9) = 4.4 characters. Example -B: If the user programs the word length = 7, with parity and one stop bit, the time out will be: T = 4 X 7(programmed word length) + 12 = 40 bit times. Character time = 40 / 10 [ (programmed word length = 7) + (parity = 1) + (stop bit = 1) + (start bit = 1) = 4 characters. The generator divides the input 16X clock by any divisor from 1 to 216 -1. The ST16C550 divides the basic crystal or external clock by 16. The frequency of the -BAUDOUT output pin is exactly 16X (16 times) of the selected baud rate (-BAUDOUT =16 x Baud Rate). Customized Baud Rates can be achieved by selecting the proper divisor values for the MSB and LSB sections of baud rate generator. Programmable Baud Rate Generator The ST16C550 supports high speed modem technologies that have increased input data rates by employing data compression schemes. For example a 33.6Kbps modem that employs data compression may require a 115.2Kbps input data rate. A 128.0Kbps ISDN modem that supports data compression may need an input data rate of 460.8Kbps. The ST16C550 can support a standard data rate of 921.6Kbps. Programming the Baud Rate Generator Registers DLM (MSB) and DLL (LSB) provides a user capability for selecting the desired final baud rate. The example in Table 3 below shows selectable baud rates when using a 1.8432 MHz crystal. The programmable Baud Rate Generator is capable of accepting an input clock up to 24 MHz, as required for supporting a 1.5Mbps data rate. The ST16C550 can be configured for internal or external clock operation. For custom baud rates, the divisor value can be calculated using the following equation: Divisor (in decimal) = (XTAL1 clock frequency) / (serial data rate x 16) Table 3, BAUD RATE GENERATOR PROGRAMMING TABLE (1.8432 MHz CLOCK): Output Baud Rate User 16 x Clock Divisor (Decimal) User 16 x Clock Divisor (HEX) DLM Program Value (HEX) DLL Program Value (HEX) 50 75 150 300 600 1200 2400 4800 7200 9600 19.2k 38.4k 57.6k 115.2k 2304 1536 768 384 192 96 48 24 16 12 6 3 2 1 900 600 300 180 C0 60 30 18 10 0C 06 03 02 01 09 06 03 01 00 00 00 00 00 00 00 00 00 00 00 00 00 80 C0 60 30 18 10 0C 06 03 02 01 Rev. 5.01 10 ST16C550 DMA Operation D0-D7. The user optionally compares the received data to the initial transmitted data for verifying error free operation of the UART TX/RX circuits. The ST16C550 FIFO trigger level provides additional flexibility to the user for block mode operation. The user can optionally operate the transmit and receive FIFO’s in the DMA mode (FCR bit-3). The DMA mode affects the state of the -RXRDY and -TXRDY output pins. The following tables show this: In this mode , the receiver and transmitter interrupts are fully operational. The Modem Control Interrupts are also operational. The interrupts are still controlled by the IER. -RXRDY pin: Non-DMA mode 1 = FIFO empty 0 = at least 1 byte in FIFO DMA mode 0 to 1 transition when FIFO empties 1 to 0 transition when FIFO reaches trigger level, or timeout occurs -TXRDY pin: Non-DMA mode 1 = at least 1 byte in FIFO 0 = FIFO empty DMA mode 1 = FIFO is full 0 = FIFO has at least 1 empty location Figure 3, TYPICAL EXTERNAL CRYSTAL OSCILLATOR CONNECTION Loop-back Mode The internal loop-back capability allows onboard diagnostics. In the loop-back mode the normal modem interface pins are disconnected and reconfigured for loop-back internally. In this mode MSR bits 4-7 are also disconnected. However, MCR register bits 0-3 can be used for controlling loop-back diagnostic testing. In the loop-back mode -OP1 and -OP2 in the MCR register (bits 0-1) control the modem -RI and -CD inputs respectively. MCR signals -DTR and -RTS (bits 0-1) are used to control the modem -CTS and -DSR inputs respectively. The transmitter output (TX) and the receiver input (RX) are disconnected from their associated interface pins, and instead are connected together internally (See Figure 4). The -CTS, -DSR, -CD, and -RI are disconnected from their normal modem control inputs pins, and instead are connected internally to DTR, -RTS, -OP1 and -OP2. Loop-back test data is entered into the transmit holding register via the user data bus interface, D0-D7. The transmit UART serializes the data and passes the serial data to the receive UART via the internal loop-back connection. The receive UART converts the serial data back into parallel data that is then made available at the user data interface, XTAL1 XTAL2 R1 0-120 (Optional) R2 1M Y1 1.8432 - 24 MHz C1 22-47pF Rev. 5.01 11 C2 22-47pF ST16C550 Figure 4, INTERNAL LOOP-BACK MODE DIAGRAM INT -TXRDY -RXRDY Receive Shift Register TX MCR Bit-4=1 Receive FIFO Registers RX VCC -RTS VCC Interrupt Control Logic -DDIS Transmit Shift Register -CTS -DTR Modem Control Logic A0-A2 -AS CS0,CS1 -CS2 Transmit FIFO Registers Inter Connect Bus Lines & Control signals -IOR,IOR -IOW,IOW RESET Register Select Logic D0-D7 Data bus & Control Logic VCC Clock & Baud Rate Generator VCC -DSR -OP1 VCC -RI -OP2 Rev. 5.01 12 XTAL2 -BAUDOUT XTAL1 RCLK -CD ST16C550 REGISTER FUNCTIONAL DESCRIPTIONS The following table delineates the assigned bit functions for the twelve ST16C550 internal registers. The assigned bit functions are more fully defined in the following paragraphs. Table 4, ST16C550 INTERNAL REGISTERS A2 A1 A0 Register [Default] Note *2 BIT-7 BIT-6 BIT-5 BIT-4 BIT-3 BIT-2 BIT-1 BIT-0 General Register Set 0 0 0 RHR [XX] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 0 THR [XX] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 1 IER [00] 0 0 0 0 modem status interrupt receive line status interrupt transmit holding register receive holding register 0 1 0 FCR [00] RCVR trigger (MSB) RCVR trigger (LSB) 0 0 DMA mode select XMIT FIFO reset RCVR FIFO reset FIFO enable 0 1 0 ISR [01] FIFO’s enabled FIFO’s enabled 0 0 INT priority bit-2 INT priority bit-1 INT priority bit-0 INT status 0 1 1 LCR [00] divisor latch enable set break set parity even parity parity enable stop bits word length bit-1 word length bit-0 1 0 0 MCR [00] 0 0 0 loopback enable -OP2 -OP1 -RTS -DTR 1 0 1 LSR [60] FIFO data error trans. empty trans. holding empty break interrupt framing error parity error overrun error receive data ready 1 1 0 MSR [X0] CD RI DSR CTS delta -CD delta -RI delta -DSR delta -CTS 1 1 1 SPR [FF] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 Baud Rate Generator Divisor Registers. Accessible when LCR bit-7 is set to logic 1. Note 1* 0 0 0 DLL [XX] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 1 DLM [XX] bit-15 bit-14 bit-13 bit-12 bit-11 bit-10 bit-9 bit-8 Note *1: The BRG registers are accessible only when LCR bit-7 is set to a logic 1. Note *2: The value represents the register’s initialized HEX value. An “X” signifies a 4-bit un-initialized nibble. Rev. 5.01 13 ST16C550 Transmit and Receive Holding Register B) FIFO status will also be reflected in the user accessible ISR register when the FIFO trigger level is reached. Both the ISR register status bit and the interrupt will be cleared when the FIFO drops below the trigger level. The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and Transmit Shift Register (TSR). The status of the THR is provided in the Line Status Register (LSR). Writing to the THR transfers the contents of the data bus (D7-D0) to the THR, providing that the THR or TSR is empty. The THR empty flag in the LSR register will be set to a logic 1 when the transmitter is empty or when data is transferred to the TSR. Note that a write operation can be performed when the transmit holding register empty flag is set (logic 0 = at least one byte in FIFO / THR, logic 1= FIFO/THR empty). C) The data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to the receive FIFO. It is reset when the FIFO is empty. IER Vs Receive/Transmit FIFO Polled Mode Operation When FCR BIT-0 equals a logic 1; resetting IER bits 0-3 enables the ST16C550 in the FIFO polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). The serial receive section also contains an 8-bit Receive Holding Register, RHR. Receive data is removed from the ST16C550 and receive FIFO by reading the RHR register. The receive section provides a mechanism to prevent false starts. On the falling edge of a start or false start bit, an internal receiver counter starts counting clocks at 16x clock rate. After 7 1/2 clocks the start bit time should be shifted to the center of the start bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver from assembling a false character. Receiver status codes will be posted in the LSR. A) LSR BIT-0 will be a logic 1 as long as there is one byte in the receive FIFO. B) LSR BIT 1-4 will indicate if an overrun error occurred. C) LSR BIT-5 will indicate when the transmit FIFO is empty. Interrupt Enable Register (IER) D) LSR BIT-6 will indicate when both the transmit FIFO and transmit shift register are empty. The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter empty, line status and modem status registers. These interrupts would normally be seen on the ST16C550 INT output pin. E) LSR BIT-7 will indicate any FIFO data errors. IER BIT-0: Logic 0 = Disable the receiver ready interrupt. (normal default condition) Logic 1 = Enable the receiver ready interrupt. IER Vs Receive FIFO Interrupt Mode Operation When the receive FIFO (FCR BIT-0 = a logic 1) and receive interrupts (IER BIT-0 = logic 1) are enabled, the receive interrupts and register status will reflect the following: IER BIT-1: Logic 0 = Disable the transmitter empty interrupt. (normal default condition) Logic 1 = Enable the transmitter empty interrupt. A) The receive data available interrupts are issued to the external CPU when the FIFO has reached the programmed trigger level. It will be cleared when the FIFO drops below the programmed trigger level. IER BIT-2: Logic 0 = Disable the receiver line status interrupt. (normal default condition) Logic 1 = Enable the receiver line status interrupt. Rev. 5.01 14 ST16C550 3 = logic 0) and when there are no characters in the transmit FIFO or transmit holding register, the TXRDY pin will be a logic 0. Once active the -TXRDY pin will go to a logic 1 after the first character is loaded into the transmit holding register. IER BIT-3: Logic 0 = Disable the modem status register interrupt. (normal default condition) Logic 1 = Enable the modem status register interrupt. IER BIT 4-7: Not used and set to “0”. Receive operation in mode “0”: When the ST16C550 is in mode “0” (FCR bit-0 = logic 0) or in the FIFO mode (FCR bit-0 = logic 1, FCR bit3 = logic 0) and there is at least one character in the receive FIFO, the -RXRDY pin will be a logic 0. Once active the -RXRDY pin will go to a logic 1 when there are no more characters in the receiver. FIFO Control Register (FCR) This register is used to enable the FIFO’s, clear the FIFO’s, set the transmit/receive FIFO trigger levels, and select the DMA mode. The DMA, and FIFO modes are defined as follows: Transmit operation in mode “1”: When the ST16C550 is in FIFO mode ( FCR bit-0 = logic 1, FCR bit-3 = logic 1 ), the -TXRDY pin will be a logic 1 when the transmit FIFO is completely full. It will be a logic 0 if one or more FIFO locations are empty. DMA MODE: See description and DMA tables on page 11. FCR BIT-0: Logic 0 = Disable the transmit and receive FIFO. (normal default condition) Logic 1 = Enable the transmit and receive FIFO. This bit must be a “1” when other FCR bits are written to or they will not be programmed. Receive operation in mode “1”: When the ST16C550 is in FIFO mode (FCR bit-0 = logic 1, FCR bit-3 = logic 1) and the trigger level has been reached, or a Receive Time Out has occurred, the -RXRDY pin will go to a logic 0. Once activated, it will go to a logic 1 after there are no more characters in the FIFO. FCR BIT-1: Logic 0 = No FIFO receive reset. (normal default condition) Logic 1 = Clears the contents of the receive FIFO and resets the FIFO counter logic (the receive shift register is not cleared or altered). This bit will return to a logic 0 after clearing the FIFO. FCR BIT 4-5: Not used. FCR BIT-2: Logic 0 = No FIFO transmit reset. (normal default condition) Logic 1 = Clears the contents of the transmit FIFO and resets the FIFO counter logic (the transmit shift register is not cleared or altered). This bit will return to a logic 0 after clearing the FIFO. FCR BIT 6-7: These bits are used to set the trigger level for the receive FIFO interrupt. An interrupt is generated when the number of characters in the FIFO equals the programmed trigger level. However the FIFO will continue to be loaded until it is full. FCR BIT-3: Logic 0 = Set DMA mode “0”. (normal default condition) Logic 1 = Set DMA mode “1.” Transmit operation in mode “0”: When the ST16C550 is in the ST16C450 mode (FIFO’s disabled, FCR bit-0 = logic 0) or in the FIFO mode (FIFO’s enabled, FCR bit-0 = logic 1, FCR bitRev. 5.01 15 BIT-7 BIT-6 RX FIFO trigger level 0 0 1 1 0 1 0 1 1 4 8 14 ST16C550 Interrupt Status Register (ISR) The ST16C550 provides four levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the ISR will provide the user with the highest pending interrupt level to be serviced. No other interrupts are acknowledged until the pending interrupt is serviced. Whenever the interrupt status register is read, the interrupt status is cleared. However it should be noted that only the current pending interrupt is cleared by the read. A lower level interrupt may be seen after rereading the interrupt status bits. The Interrupt Source Table 5 (below) shows the data values (bit 0-3) for the four prioritized interrupt levels and the interrupt sources associated with each of these interrupt levels: Table 5, INTERRUPT SOURCE TABLE Priority Level X 1 2 2 3 4 [ISR] Bit-3 Bit-2 Bit-1 Bit-0 0 0 0 1 0 0 0 1 1 1 0 0 0 1 0 0 1 0 1 0 0 0 0 0 Source of the interrupt No interrupt pending LSR (Receiver Line Status Register) RXRDY (Received Data Ready) RXRDY (Receive Data time out) TXRDY ( Transmitter Holding Register Empty) MSR (Modem Status Register) Rev. 5.01 16 ST16C550 ISR BIT-0: Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt service routine. Logic 1 = No interrupt pending. (normal default condition) ISR BIT 1-3: (logic 0 or cleared is the default condition) These bits indicate the source for a pending interrupt at interrupt priority levels 1, 2, and 3 (See Interrupt Source Table). ISR BIT 6-7: (logic 0 or cleared is the default condition) These bits are set to a logic 0 when the FIFO is not being used. They are set to a logic 1 when the FIFO’s are enabled The Line Control Register is used to specify the asynchronous data communication format. The word length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. LCR BIT 0-1: (logic 0 or cleared is the default condition) These two bits specify the word length to be transmitted or received. Word length 0 0 1 1 0 1 0 1 5 6 7 8 Stop bit length (Bit time(s)) 0 1 1 5,6,7,8 5 6,7,8 1 1-1/2 2 LCR BIT-4: If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR BIT-4 selects the even or odd parity format. Logic 0 = ODD Parity is generated by forcing an odd number of logic 1’s in the transmitted data. The receiver must be programmed to check the same format. (normal default condition) Logic 1 = EVEN Parity is generated by forcing an even the number of logic 1’s in the transmitted. The receiver must be programmed to check the same format. Line Control Register (LCR) BIT-0 Word length LCR BIT-3: Parity or no parity can be selected via this bit. Logic 0 = No parity (normal default condition) Logic 1 = A parity bit is generated during the transmission, receiver checks the data and parity for transmission errors. ISR BIT 4-5: Not used and set to “0”. BIT-1 BIT-2 LCR BIT-5: If the parity bit is enabled, LCR BIT-5 selects the forced parity format. LCR BIT-5 = logic 0, parity is not forced (normal default condition) LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive data. LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive data. LCR BIT-2: (logic 0 or cleared is the default condition) The length of stop bit is specified by this bit in conjunction with the programmed word length. Rev. 5.01 17 LCR Bit-5 LCR Bit-4 LCR Bit-3 Parity selection X 0 0 1 1 X 0 1 0 1 0 1 1 1 1 No parity Odd parity Even parity Force parity “1” Forced “0” ST16C550 LCR BIT-6: When enabled the Break control bit causes a break condition to be transmitted (the TX output is forced to a logic 0 state). This condition exists until disabled by setting LCR bit-6 to a logic 0. Logic 0 = No TX break condition. (normal default condition) Logic 1 = Forces the transmitter output (TX) to a logic 0 for alerting the remote receiver to a line break condition. MCR BIT 5-7: Not used and set to “0”. Line Status Register (LSR) This register provides the status of data transfers between. the ST16C550 and the CPU. LSR BIT-0: Logic 0 = No data in receive holding register or FIFO. (normal default condition) Logic 1 = Data has been received and is saved in the receive holding register or FIFO. LCR BIT-7: The internal baud rate counter latch and Enhance Feature mode enable. Logic 0 = Divisor latch disabled. (normal default condition) Logic 1 = Divisor latch and enhanced feature register enabled. LSR BIT-1: Logic 0 = No overrun error. (normal default condition) Logic 1 = Overrun error. A data overrun error occurred in the receive shift register. This happens when additional data arrives while the FIFO is full. In this case the previous data in the shift register is overwritten. Note that under this condition the data byte in the receive shift register is not transfer into the FIFO, therefore the data in the FIFO is not corrupted by the error. Modem Control Register (MCR) This register controls the interface with the modem or a peripheral device. MCR BIT-0: Logic 0 = Force -DTR output to a logic 1. (normal default condition) Logic 1 = Force -DTR output to a logic 0. LSR BIT-2: Logic 0 = No parity error (normal default condition) Logic 1 = Parity error. The receive character does not have correct parity information and is suspect. In the FIFO mode, this error is associated with the character at the top of the FIFO. MCR BIT-1: Logic 0 = Force -RTS output to a logic 1. (normal default condition) Logic 1 = Force -RTS output to a logic 0. LSR BIT-3: Logic 0 = No framing error (normal default condition). Logic 1 = Framing error. The receive character did not have a valid stop bit(s). In the FIFO mode this error is associated with the character at the top of the FIFO. MCR BIT-2: Logic 0 = Set -OP1 output to a logic 1. (normal default condition) Logic 1 = Set -OP1 output to a logic 0. LSR BIT-4: Logic 0 = No break condition (normal default condition) Logic 1 = The receiver received a break signal (RX was a logic 0 for one character frame time). In the FIFO mode, only one break character is loaded into the FIFO. MCR BIT-3: Logic 0 = Set -OP2 output to a logic 1. (normal default condition) Logic 1 = Set -OP2 output to a logic 0. MCR BIT-4: Logic 0 = Disable loop-back mode. (normal default condition) Logic 1 = Enable local loop-back mode (diagnostics). LSR BIT-5: This bit is the Transmit Holding Register Empty indicator. This bit indicates that the UART is ready to accept a new character for transmission. In addition, Rev. 5.01 18 ST16C550 this bit causes the UART to issue an interrupt to CPU when the THR interrupt enable is set. The THR bit is set to a logic 1 when a character is transferred from the transmit holding register into the transmitter shift register. The bit is reset to logic 0 concurrently with the loading of the transmitter holding register by the CPU. In the FIFO mode this bit is set when the transmit FIFO is empty; it is cleared when at least 1 byte is written to the transmit FIFO. MSR BIT-2: Logic 0 = No -RI Change (normal default condition) Logic 1 = The -RI input to the ST16C550 has changed from a logic 0 to a logic 1. A modem Status Interrupt will be generated. MSR BIT-3: Logic 0 = No -CD Change (normal default condition) Logic 1 = Indicates that the -CD input to the has changed state since the last time it was read. A modem Status Interrupt will be generated. LSR BIT-6: This bit is the Transmit Empty indicator. This bit is set to a logic 1 whenever the transmit holding register and the transmit shift register are both empty. It is reset to logic 0 whenever either the THR or TSR contains a data character. In the FIFO mode this bit is set to one whenever the transmit FIFO and transmit shift register are both empty. MSR BIT-4: CTS (active high, logical 1). Normally this bit is the compliment of the -CTS input. In the loop-back mode, this bit is equivalent to the RTS bit in the MCR register. MSR BIT-5: DSR (active high, logical 1). Normally this bit is the compliment of the -DSR input. In the loop-back mode, this bit is equivalent to the DTR bit in the MCR register. LSR BIT-7: Logic 0 = No Error (normal default condition) Logic 1 = At least one parity error, framing error or break indication is in the current FIFO data. This bit is cleared when there are no remaining LSR errors in the RX FIFO. MSR BIT-6: RI (active high, logical 1). Normally this bit is the compliment of the -RI input. In the loop-back mode this bit is equivalent to the OP1 bit in the MCR register. Modem Status Register (MSR) This register provides the current state of the control interface signals from the modem, or other peripheral device that the ST16C550 is connected to. Four bits of this register are used to indicate the changed information. These bits are set to a logic 1 whenever a control input from the modem changes state. These bits are set to a logic 0 whenever the CPU reads this register. MSR BIT-7: CD (active high, logical 1). Normally this bit is the compliment of the -CD input. In the loop-back mode this bit is equivalent to the OP2 bit in the MCR register. Scratchpad Register (SPR) The ST16C550 provides a temporary data register to store 8 bits of user information. MSR BIT-0: Logic 0 = No -CTS Change (normal default condition) Logic 1 = The -CTS input to the ST16C550 has changed state since the last time it was read. A modem Status Interrupt will be generated. MSR BIT-1: Logic 0 = No -DSR Change (normal default condition) Logic 1 = The -DSR input to the ST16C550 has changed state since the last time it was read. A modem Status Interrupt will be generated. Rev. 5.01 19 ST16C550 ST16C550 EXTERNAL RESET CONDITIONS REGISTERS IER ISR RESET STATE FCR IER BITS 0-7 = logic 0 ISR BIT-0=1, ISR BITS 1-7 = logic 0 BITS 0-7 = logic 0 LSR BITS 0-4 = logic 0, LSR BITS 5-6 = logic 1 LSR, BIT 7 = logic 0 MSR BITS 0-3 = logic 0, MSR BITS 4-7 = logic levels of the input signals BITS 0-7 = logic 0 SIGNALS RESET STATE TX -OP1 -OP2 -RTS -DTR -RXRDY -TXRDY INT Logic 1 Logic 1 Logic 1 Logic 1 Logic 1 Logic 1 Logic 0 Logic 0 LCR, MCR LSR MSR Rev. 5.01 20 ST16C550 AC ELECTRICAL CHARACTERISTICS TA=0° - 70°C (-40° - +85°C for Industrial grade packages), Vcc=3.3 - 5.0 V ± 10% unless otherwise specified. Symbol T1w,T2w T3w T4w T5s T5h T6s T6h T6s' T7d T7w T7w' T7h T7h' T8d T9d T11d T12d T12h T13d T13w T13w' T13h T14d T15d T16s T16h T17d T18d T19d T20d T21d T22d T23d T24d T25d T26d T27d T28d TR N Parameter Limits 3.3 Min Max 17 16 35 5 5 5 0 10 10 77 77 0 5 10 77 15 35 25 10 27 77 0 10 77 20 5 50 40 40 1 45 45 8 24 Clock pulse duration Oscillator/Clock frequency Address strobe width Address setup time Address hold time Chip select setup time Chip select hold time Address setup time -IOR delay from chip select -IOR strobe width Chip select width Chip select hold time from -IOR Address hold time -IOR delay from address Read cycle delay -IOR to -DDIS delay Delay from -IOR to data Data disable time -IOW delay from chip select -IOW strobe width Chip select width Chip select hold time from -IOW -IOW delay from address Write cycle delay Data setup time Data hold time Delay from -IOW to output Delay to set interrupt from MODEM input Delay to reset interrupt from -IOR Delay from stop to set interrupt Delay from -IOR to reset interrupt Delay from stop to interrupt Delay from initial INT reset to transmit start Delay from -IOW to reset interrupt Delay from stop to set -RxRdy Delay from -IOR to reset -RxRdy Delay from -IOW to set -TxRdy Delay from start to reset -TxRdy Reset pulse width Baud rate divisor Limits Units Conditions 5.0 Min Max 17 ns 24 MHz 25 ns 0 ns 5 ns 0 ns 0 ns 5 ns see Note 1 10 ns 38 ns 38 ns 0 ns 5 ns see Note 1 10 ns 38 ns 10 ns 100 pF load 25 ns 15 ns 10 ns 15 ns 38 ns 0 ns 10 ns 38 ns 15 ns 5 ns 40 ns 100 pF load 35 ns 100 pF load 35 ns 100 pF load 1 Rclk 40 ns 100 pF load 40 ns 8 24 Rclk 45 1 45 45 8 40 1 Note 1: Applicable only when -AS is tied low. Rev. 5.01 21 216-1 40 1 40 40 8 40 1 216-1 ns Rclk ns ns Rclk ns Rclk ST16C550 ABSOLUTE MAXIMUM RATINGS Supply range Voltage at any pin Operating temperature Storage temperature Package dissipation 7 Volts GND - 0.3 V to VCC +0.3 V -40° C to +85° C -65° C to 150° C 500 mW DC ELECTRICAL CHARACTERISTICS TA=0° - 70°C (-40° - +85°C for Industrial grade packages), Vcc=3.3 - 5.0 V ± 10% unless otherwise specified. Symbol VILCK VIHCK VIL VIH VOL VOL VOH VOH IIL ICL I CC CP Parameter Clock input low level Clock input high level Input low level Input high level Output low level on all outputs Output low level on all outputs Output high level Output high level Input leakage Clock leakage Avg power supply current Input capacitance Limits 3.3 Min Max Limits 5.0 Min Max -0.3 2.4 -0.3 2.0 -0.5 3.0 -0.5 2.2 0.6 VCC 0.8 VCC 0.6 VCC 0.8 VCC 0.4 0.4 2.4 2.0 ±10 ±10 1.3 5 Rev. 5.01 22 ±10 ±10 3 5 Units V V V V V V V V µA µA mA pF Conditions IOL= 5 mA IOL= 4 mA IOH= -5 mA IOH= -1 mA ST16C550 T1w T2w EXTERNAL CLOCK T3w -BAUDOUT 1/2 -BAUDOUT 1/3 -BAUDOUT 1/3> -BAUDOUT X450-CK-1 Clock timing Rev. 5.01 23 ST16C550 T4w -A S T5h T5s V a lid A d d re ss A 0 -A 2 T6h T6s -C S 2 C S 1 -C S 0 V a lid T7d T7h T7w T8d -IO R IO R T9d A c tiv e T11d T11d A c tiv e -D D IS T12h T12d D a ta D 0 -D 7 X 5 5 0-R D -1 General Read Timing when using -AS signal T4w -AS T5h T5s Valid Address A0-A2 T6h T6s -CS2 CS1-CS0 Valid T13d T14d -IOW IOW T13h T13w T15d Active T16s D0-D7 T16h Data X550-W D-1 General Write Timing when using -AS signal. Rev. 5.01 24 ST16C550 Valid Address A0-A2 Valid Address T7h' T6s' T7h' T6s' T7w’ Active -CS Active T7w -IOR T9d Active T12d D0-D7 T12h T12d T12h Data General Read Timing when -AS is tied to GND Valid Address A0-A2 Valid Address T7h' T6s' -CS Active Active T13w -IOW T15d T13w’ Active T16s D0-D7 T7h' T6s' T16h Data General Write Timing when -AS is tied to GND Rev. 5.01 25 T16s T16h ST16C550 -IOW IOW Active T17d -RTS -DTR Change of state Change of state -CD -CTS -DSR Change of state Change of state T18d T18d INT Active Active Active T19d -IOR IOR Active Active Active T18d Change of state -RI X450-MD-1 Modem input/output timing Rev. 5.01 26 ST16C550 START BIT RX STOP BIT DATA BITS (5-8) D0 D1 D2 D3 D4 D5 5 DATA BITS 6 DATA BITS 7 DATA BITS D6 D7 PARITY BIT NEXT DATA START BIT T20d Active INT T21d -IOR IOR 16 BAUD RATE CLOCK Receive timing Rev. 5.01 27 X450-RX-1 ST16C550 START BIT DATA BITS (5-8) D0 RX STOP BIT D1 D2 D3 D4 D5 D6 D7 PARITY BIT NEXT DATA START BIT T25d Active Data Ready -RXRDY T26d -IOR IOR Active X550-RX-2 Receive ready timing in non FIFO mode Rev. 5.01 28 ST16C550 START BIT DATA BITS (5-8) D0 RX STOP BIT D1 D2 D3 D4 D5 D6 D7 PARITY BIT First byte that reaches the trigger level T25d Active Data Ready -RXRDY T26d -IOR IOR Active X550-RX-3 Receive ready timing in FIFO mode Rev. 5.01 29 ST16C550 START BIT DATA BITS (5-8) D0 TX STOP BIT D1 D2 D3 D4 D5 5 DATA BITS D6 D7 PARITY BIT 6 DATA BITS 7 DATA BITS T22d INT Active TX Ready T24d T23d IOW/ -IOW Active Active 16 BAUD RATE CLOCK Transmit timing Rev. 5.01 30 ST16C550 START BIT DATA BITS (5-8) D0 TX STOP BIT D1 D2 D3 D4 D5 D6 D7 PARITY BIT -IOW IOW NEXT DATA START BIT Active T28d BYTE #1 T27d -TXRDY Active Transmitter ready Transmitter not ready X550-TX-2 Transmit ready timing in non FIFO mode Rev. 5.01 31 ST16C550 START BIT DATA BITS (5-8) TX D0 D1 D2 D3 D4 STOP BIT D5 D6 5 DATA BITS D7 PARITY BIT 6 DATA BITS 7 DATA BITS -IOW IOW Active T28d D0-D7 BYTE #16 T27d -TXRDY FIFO Full X550-TX-3 Transmit ready timing in FIFO mode Rev. 5.01 32 ST16C550 PACKAGE OUTLINE DRAWING 44LEAD PLASTIC LEADED CHIP CARRIER (PLCC) C D Seating Plane D1 2 1 45° x H1 45° x H2 A2 44 B1 D D1 B D3 e R D3 A1 A Note: The control dimension is the inch column SYMBOL INCHES MILLIMETERS MIN MAX MIN MAX 4.57 A 0.165 0.180 4.19 A1 0.090 0.120 2.29 3.05 A2 0.020 ----- 0.51 ------ B 0.013 0.021 0.33 0.53 B1 0.026 0.032 0.66 0.81 C 0.008 0.013 0.19 0.32 D 0.685 0.695 17.40 17.65 D1 0.650 0.656 16.51 16.66 D2 0.590 0.630 14.99 16.00 D3 0.500 typ 12.70 typ e 0.50 BSC 1.27BSC H1 0.042 0.056 1.07 1.42 H2 0.042 0.048 1.07 1.22 R 0.025 0.045 0.64 1.14 Rev. 5.01 33 D2 ST16C550 PACKAGE OUTLINE DRAWING 48 LEAD THIN QUAD FLAT PACK (TQFP) D D1 36 25 37 24 D1 48 13 1 2 1 B e A2 C A α Seating Plane A1 L Note: The control dimension is the millimeter column SYMBOL INCHES MILLIMETERS MIN MAX MIN MAX A 0.039 0.047 1.00 1.20 A1 0.002 0.006 0.05 0.15 A2 0.037 0.041 0.95 1.05 B 0.007 0.011 0.17 0.27 C 0.004 0.008 0.09 0.20 D 0.346 0.362 8.80 9.20 D1 0.272 0.280 6.90 7.10 e 0.20 BSC 0.50BSC L 0.018 0.030 0.45 0.75 α 0° 7° 0° 7° Rev. 5.01 34 D ST16C550 EXPLANATION OF DATA SHEET REVISIONS: FROM TO 4.20 4.30 Added revision history. Added Device Status to front page. Sept 2003 4.30 5.00 Updated AC Timing values for IOW, CS and IOR pulse widths and Read/Write cycle delays. This applies to devices with top mark date code of "B2 YYWW" and newer. Feb 2005 5.00 5.01 CHANGES Corrected the AC Timing values. Added Chip Select Width for clarification. DATE Apr 2005 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2005 EXAR Corporation Datasheet April 2005 Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com Reproduction, in part or whole, without prior written consent of EXAR Corporation is prohibited. Rev. 5.01 35