XR16V554DIVTR-F

XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO JULY 2010 REV. 1.0.3 GENERAL DESCRIPTION FEATURES • Pin-to-pin compatible with ST16C454, ST16C554, The XR16V554 (V554) is a quad Universal Asynchronous Receiver and Transmitter (UART) with 16 bytes of transmit and receive FIFOs, selectable receive FIFO trigger levels and data rates of up to 4 Mbps at 3.3 V. Each UART has a set of registers that provide the user with operating status and control, receiver error indications, and modem serial interface controls. An internal loopback capability allows onboard diagnostics. The V554 is available in a 48pin QFN, 64-pin LQFP, 68-pin PLCC and 80-pin LQFP packages. The 64-pin and 80-pin packages only offer the 16 mode interface, but the 48- and 68pin packages offer an additional 68 mode interface which allows easy integration with Motorola processors. The XR16V554IV (64-pin) offers three state interrupt output while the XR16V554DIV provides continuous interrupt output. The XR16V554 is compatible with the industry standard ST16C554. TI’s TL16C554A and Philip’s SC16C554B • Intel or Motorola Data Bus Interface select • Four independent UART channels ■ Register Set Compatible to 16C550 ■ Data rates of up to 4 Mbps at 3.3 V and 3.125 Mbps at 2.5 V ■ 16 byte Transmit FIFO ■ 16 byte Receive FIFO with error tags ■ 4 Selectable RX FIFO Trigger Levels ■ Full modem interface • 2.25V to 3.6V supply operation • Crystal oscillator or external clock input APPLICATIONS • Portable Appliances • Telecommunication Network Routers • Ethernet Network Routers • Cellular Data Devices • Factory Automation and Process Controls FIGURE 1. XR16V554 BLOCK DIAGRAM * 5 Volt Tolerant Inputs ( Except XTAL1 input) A2:A0 D7:D0 CSA# UART Channel A UART 16 Byte TX FIFO Regs TX & RX CSB# BRG IOR# IOW# CSC# CSD# INTA 2.25V to 3.6 V VCC GND TXA, RXA, DTRA#, DSRA#, RTSA#, CTSA#, CDA#, RIA# 16 Byte RX FIFO UART Channel B (same as Channel A) TXB, RXB, DTRB#, DSRB#, RTSB#, CTSB#, CDB#, RIB# UART Channel C (same as Channel A) TXC, RXC, DTRC#, DSRC#, RTSC#, CTSC#, CDC#, RIC# Reset UART Channel D (same as Channel A) TXD, RXD, DTRD#, DSRD#, RTSD#, CTSD#, CDD#, RID# 16/ 68# INTSEL Crystal Osc / Buffer INTB INTC INTD Data Bus Interface TXRDY# A-D RXRDY# A-D XTAL1 XTAL2 554BLK Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO REV. 1.0.3 10 60 DSRD# CTSA# 11 59 CTSD# DTRA# 12 58 DTRD# VCC 13 57 GND RTSA# 14 56 RTSD# INTA 15 55 INTD CSA# 16 TXA 17 IOW# 18 TXB 19 CSB# CSC# A3 RXD RID# CDD# 63 43 CDC# 46 DTRD# 4 45 GND RTSA# 5 44 RTSD# INTA 6 43 INTD CSA# 7 42 CSD# TXA 8 IOW# 9 XR16V554/554D 64-pin TQFP Intel Mode Only 41 TXD 40 IOR# TXC 2 30 31 32 CDC# DSRC# CTSC# RIC# 33 29 16 RXC CTSB# 28 DTRC# GND 34 26 15 27 VCC DTRB# XTAL2 RTSC# 35 RESET 36 14 25 13 GND XTAL1 RTSB# 23 INTC 24 37 A0 12 A1 CSC# INTB 21 38 22 39 11 A2 10 VCC TXB CSB# 20 62 42 RIC# 3 VCC 19 VCC 41 RXC DTRA# RIB# 63 40 GND CTSD# RXB 64 39 TXRDY# DSRD# 47 17 D0 38 RXRDY# 48 2 18 GND 37 RESET 1 CTSA# CDB# 65 D1 36 XTAL2 DSRA# DSRB# 66 D2 67 35 34 A0 XTAL1 33 49 A1 CDD# 50 32 RID# 51 A2 31 RXD 52 16/68# VCC 53 VCC D0 54 RXB D2 D1 55 43 CDC# RXA GND 42 RIC# 61 41 62 40 RXC RIA# GND CDA# 64 63 39 TXRDY# 30 DSRC# DSRC# 29 44 44 28 26 26 27 DSRB# DSRB# D4 CTSC# D3 DTRC# 45 56 46 25 45 D5 24 CTSB# 46 25 57 DTRB# 24 CTSB# 58 DTRC# CTSC# DTRB# D7 VCC D6 47 VCC 60 23 47 59 RTSC# GND 23 38 N.C. 48 GND RXRDY# A4 49 RTSC# 37 50 22 INTC 48 RESET TXC 20 21 49 22 36 51 N.C. 21 XTAL2 XR16V554 68-pin PLCC Motorola Mode (16/68# pin connected to GND) RTSB# INTB RTSB# 35 D3 N.C. 50 XTAL1 68 TXD 52 20 34 D4 N.C. 53 19 A0 1 54 TXB 33 D5 N.C. TXC A1 2 RTSD# 55 51 32 D6 56 15 18 A2 3 14 IRQ# R/W# 31 D7 RTSA# IOR# 16/68# 4 GND 52 30 GND DTRD# 57 17 29 5 58 13 16 RXB RXA 12 VCC TXA VCC 6 DTRA# CS# 28 RIA# CTSD# CSD# 27 7 DSRD# 59 TXD RIB# CDA# 60 11 53 CDB# 8 10 CTSA# 54 XR16V554 68-pin PLCC Intel Mode (16/68# pin connected to VCC) 9 DSRA# RIB# CDD# DSRA# CDB# RID# 67 63 D1 68 RXD D2 1 62 D3 2 VCC D4 3 63 D5 4 64 D6 5 D0 D7 6 INTSEL GND 7 65 RXA 8 66 CDA# RIA# 9 FIGURE 2. PIN OUT ASSIGNMENT FOR 68-PIN PLCC PACKAGES IN 16 AND 68 MODE AND 64-PIN LQFP PACKAGES XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO REV. 1.0.3 1 36 RXD VCC 2 35 CTSD# RTSA# 3 34 GND INTA 4 33 CSA# 5 32 TXA 6 IOW# 7 TXB 8 CSB# XR16V554 48-pin QFN Intel Mode (16/68# pin connected to VCC) 37 VCC 38 INTSEL 40 D1 39 D0 D3 41 D2 43 D4 42 44 D5 46 D7 45 D6 RXA 48 CTSA# 47 GND 37 VCC 38 INTSEL 40 D1 39 D0 D3 41 D2 43 D4 42 44 D5 46 D7 45 D6 RXA 48 47 GND FIGURE 3. PIN OUT ASSIGNMENT FOR 48-PIN QFN PACKAGE AND 80-PIN LQFP PACKAGE CTSA# 1 36 RXD VCC 2 35 CTSD# RTSA# 3 34 GND RTSD# INTA 4 33 RTSD# INTD CSA# 5 32 INTD 31 CSD# TXA 6 XR16V554 48-pin QFN Motorola Mode (16/68# pin connected to GND) 31 CSD# 23 24 VCC XTAL2 RXC NC CTSC# 63 61 DTRC# 64 DSRC# VCC 65 62 18 RTSC# 66 XTAL1 INTC 67 RXB CSC# 68 16/68# TXC 69 NC IOR# 70 71 72 73 TXD CSD# INTD 74 RXC RTSD# 75 GND GND 76 20 RESET DTRD# 19 XTAL2 77 18 XTAL1 CTSD# 78 A1 A0 DSRD# 79 80 NC RXB CTSC# RTSC# 21 INTC 25 22 26 12 GND 11 CTSB# 20 RTSB# RTSC# RESET INTC 25 19 26 12 17 11 A0 RTSB# CTSB# 15 CSC# 16 27 A1 10 A2 INTB 14 CSC# 13 27 23 10 24 TXC INTB VCC 28 CTSC# 9 21 CSB# 22 TXC 17 28 15 9 16 8 A2 7 TXB 16/68# IOW# IOR# 14 TXD 29 13 30 NC 1 60 NC CDD# 2 59 CDC# RID# 3 58 RIC# 4 57 RXC 5 56 GND 6 55 TXRDY# 54 RXRDY# 53 RESET 52 NC RXD VCC INTSEL D0 7 D1 8 D2 9 NC 10 D3 11 D4 12 XR16 V 554 80 - pin LQFP Intel Mode Only 51 XTAL2 50 XTAL1 49 NC D5 13 48 A0 D6 14 47 A1 D7 15 46 A2 GND 16 45 VCC RXA 17 44 RXB 3 34 35 36 37 38 39 40 INTB GND DTRB# CTSB# DSRB# NC 33 RTSB# 32 30 NC TXB 29 TXA CSB# 28 CSA# 31 27 INTA IOW# 26 DSRA NC # RTSA# NC 25 41 VCC 20 24 NC DTRA # CDB# 23 RIB# 42 CTSA# 43 19 22 18 21 RIA# CDA# 30 TXD 29 IOR# XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO REV. 1.0.3 ORDERING INFORMATION PART NUMBER PACKAGE OPERATING TEMPERATURE RANGE DEVICE STATUS XR16V554IJ 68-Lead PLCC -40°C to +85°C Active XR16V554IV 64-Lead LQFP -40°C to +85°C Active XR16V554DIV 64-Lead LQFP -40°C to +85°C Active XR16V554IL 48-pin QFN -40°C to +85°C Active XR16V554IV80 80-Lead LQFP -40°C to +85°C Active PIN DESCRIPTIONS Pin Description NAME 48-QFN PIN # 64-LQFP 68-PLCC 80-LQFP TYPE PIN # PIN# PIN # DESCRIPTION DATA BUS INTERFACE A2 A1 A0 15 16 17 22 23 24 32 33 34 46 47 48 I D7 D6 D5 D4 D3 D2 D1 D0 46 45 44 43 42 41 40 39 60 59 58 57 56 55 54 53 5 4 3 2 1 68 67 66 15 14 13 12 11 9 8 7 I/O IOR# (VCC) 29 40 52 70 I When 16/68# pin is HIGH, the Intel bus interface is selected and this input becomes read strobe (active low). The falling edge instigates an internal read cycle and retrieves the data byte from an internal register pointed by the address lines [A2:A0], puts the data byte on the data bus to allow the host processor to read it on the rising edge. When 16/68# pin is LOW, the Motorola bus interface is selected and this input is not used and should be connected to VCC. IOW# (R/W#) 7 9 18 31 I When 16/68# pin is HIGH, it selects Intel bus interface and this input becomes write strobe (active low). The falling edge instigates the internal write cycle and the rising edge transfers the data byte on the data bus to an internal register pointed by the address lines. When 16/68# pin is LOW, the Motorola bus interface is selected and this input becomes read (HIGH) and write (LOW) signal. CSA# (CS#) 5 7 16 28 I When 16/68# pin is HIGH, this input is chip select A (active low) to enable channel A in the device. When 16/68# pin is LOW, this input becomes the chip select (active low) for the Motorola bus interface. 4 Address data lines [2:0]. These 3 address lines select one of the internal registers in UART channel A-D during a data bus transaction. Data bus lines [7:0] (bidirectional). XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO REV. 1.0.3 Pin Description NAME 48-QFN PIN # 64-LQFP 68-PLCC 80-LQFP TYPE PIN # PIN# PIN # DESCRIPTION CSB# (A3) 9 11 20 33 I When 16/68# pin is HIGH, this input is chip select B (active low) to enable channel B in the device. When 16/68# pin is LOW, this input becomes address line A3 which is used for channel selection in the Motorola bus interface. CSC# (A4) 27 38 50 68 I When 16/68# pin is HIGH, this input is chip select C (active low) to enable channel C in the device. When 16/68# pin is LOW, this input becomes address line A4 which is used for channel selection in the Motorola bus interface. CSD# (VCC) 31 42 54 73 I When 16/68# pin is HIGH, this input is chip select D (active low) to enable channel D in the device. When 16/68# pin is LOW, this input is not used and should be connected VCC. INTA (IRQ#) 4 6 15 27 INTB INTC INTD (N.C.) 10 26 32 12 37 43 21 49 55 34 67 74 O When 16/68# pin is HIGH for Intel bus interface, these ouputs become the interrupt outputs for channels B, C, and D. The output state is defined by the user through the software setting of MCR[3]. The interrupt outputs are set to the active mode when MCR[3] is set to a logic 1 and are set to the three state mode when MCR[3] is set to a logic 0 (default). See MCR[3]. When 16/68# pin is LOW for Motorola bus interface, these outputs are unused and will stay at logic zero level. Leave these outputs unconnected. TXRDY# - - 39 55 O Transmitter Ready (active low). This output is a logically ANDed status of TXRDY# A-D. See Table 5. If this output is unused, leave it unconnected. RXRDY# - - 38 54 O Receiver Ready (active low). This output is a logically ANDed status of RXRDY# A-D. See Table 5. If this output is unused, leave it unconnected. O When 16/68# pin is HIGH for Intel bus interface, this (OD) ouput becomes channel A interrupt output. The output state is defined by the user and through the software setting of MCR[3]. INTA is set to the active mode when MCR[3] is set to a logic 1. INTA is set to the three state mode when MCR[3] is set to a logic 0 (default). See MCR[3]. When 16/68# pin is LOW for Motorola bus interface, this output becomes device interrupt output (active low, open drain). An external pull-up resistor is required for proper operation. 5 XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO REV. 1.0.3 Pin Description NAME 48-QFN PIN # INTSEL 38 64-LQFP 68-PLCC 80-LQFP TYPE PIN # PIN# PIN # - DESCRIPTION 65 6 I Interrupt Select (active high, input with internal pulldown). When 16/68# pin is HIGH for Intel bus interface, this pin can be used in conjunction with MCR bit-3 to enable or disable the INT A-D pins or override MCR bit-3 and enable the interrupt outputs. Interrupt outputs are enabled continuously when this pin is HIGH. MCR bit-3 enables and disables the interrupt output pins. In this mode, MCR bit-3 is set to a logic 1 to enable the continuous output. See MCR bit-3 description for full detail. This pin must be LOW in the Motorola bus interface mode. For the 64 pin packages, this pin is bonded to VCC internally in the XR16V554D so the INT outputs operate in the continuous interrupt mode. This pin is bonded to GND internally in the XR16V554 and therefore requires setting MCR bit-3 for enabling the interrupt output pins. MODEM OR SERIAL I/O INTERFACE TXA TXB TXC TXD 6 8 28 30 8 10 39 41 17 19 51 53 29 32 69 72 O UART channels A-D Transmit Data and infrared transmit data. In this mode, the TX signal will be HIGH during reset, or idle (no data). RXA RXB RXC RXD 48 13 22 36 62 20 29 51 7 29 41 63 17 44 57 4 I UART channel A-D Receive Data. Normal receive data input must idle HIGH. RTSA# RTSB# RTSC# RTSD# 3 11 25 33 5 13 36 44 14 22 48 56 26 35 66 75 O UART channels A-D Request-to-Send (active low) or general purpose output. If these outputs are not used, leave them unconnected. CTSA# CTSB# CTSC# CTSD# 1 12 23 35 2 16 33 47 11 25 45 59 23 38 63 78 I UART channels A-D Clear-to-Send (active low) or general purpose input. These inputs should be connected to VCC when not used. DTRA# DTRB# DTRC# DTRD# - 3 15 34 46 12 24 46 58 24 37 64 77 O UART channels A-D Data-Terminal-Ready (active low) or general purpose output. If these outputs are not used, leave them unconnected. DSRA# DSRB# DSRC# DSRD# - 1 17 32 48 10 26 44 60 22 39 62 79 I UART channels A-D Data-Set-Ready (active low) or general purpose input. This input should be connected to VCC when not used. This input has no effect on the UART. 6 XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO REV. 1.0.3 Pin Description NAME 48-QFN PIN # 64-LQFP 68-PLCC 80-LQFP TYPE PIN # PIN# PIN # CDA# CDB# CDC# CDD# - 64 18 31 49 9 27 43 61 19 42 59 2 I UART channels A-D Carrier-Detect (active low) or general purpose input. This input should be connected to VCC when not used. This input has no effect on the UART. RIA# RIB# RIC# RID# - 63 19 30 50 8 28 42 62 18 43 58 3 I UART channels A-D Ring-Indicator (active low) or general purpose input. This input should be connected to VCC when not used. This input has no effect on the UART. DESCRIPTION ANCILLARY SIGNALS XTAL1 18 25 35 50 I Crystal or external clock input. Caution: this input is not 5V tolerant. XTAL2 19 26 36 51 O Crystal or buffered clock output. 16/68# 14 - 31 - I Intel or Motorola Bus Select (input with internal pull-up). When 16/68# pin is HIGH, 16 or Intel Mode, the device will operate in the Intel bus type of interface. When 16/68# pin is LOW, 68 or Motorola mode, the device will operate in the Motorola bus type of interface. Motorola bus interface is not available on the 64 pin package. RESET (RESET#) 20 27 37 53 I When 16/68# pin is HIGH for Intel bus interface, this input becomes the Reset pin (active high). In this case, a 40 ns minimum HIGH pulse on this pin will reset the internal registers and all outputs. The UART transmitter output will be held HIGH, the receiver input will be ignored and outputs are reset during reset period (Table 13). When 16/68# pin is at LOW for Motorola bus interface, this input becomes Reset# pin (active low). This pin functions similarly, but instead of a HIGH pulse, a 40 ns minimum LOW pulse will reset the internal registers and outputs. Motorola bus interface is not available on the 64 pin package. 13, 30, 47, 64 5, 25, 45, 65 Pwr 2.25V to 3.6V power supply. All inputs, except XTAL1, are 5V tolerant. VCC 2, 24, 37 4, 21, 35, 52 GND 21, 47 14, 28, 45, 61 6, 23, 40, 57 16, 36, 56, 76 Pwr Power supply common, ground. GND Center Pad N/A N/A N/A Pwr The center pad on the backside of the QFN package is metallic and should be connected to GND on the PCB. The thermal pad size on the PCB should be the approximate size of this center pad and should be solder mask defined. The solder mask opening should be at least 0.0025" inwards from the edge of the PCB thermal pad. 7 XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO REV. 1.0.3 Pin Description NAME 48-QFN PIN # N.C. - 64-LQFP 68-PLCC 80-LQFP TYPE PIN # PIN# PIN # - - 1, 10, 20, 21, 30, 40, 41, 49, 52, 60, 61, 71, 80 DESCRIPTION No Connection. These pins are not used in either the Intel or Motorola bus modes. Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain. 8 XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO REV. 1.0.3 1.0 PRODUCT DESCRIPTION The XR16V554 (V554) integrates the functions of 4 enhanced 16C550 Universal Asynchrounous Receiver and Transmitter (UART). Each UART is independently controlled and has its own set of device configuration registers. The configuration registers set is 16550 UART compatible for control, status and data transfer. Additionally, each UART channel has 16 bytes of transmit and receive FIFOs, programmable baud rate generator and data rate up to 4 Mbps at 3.3 V. The XR16V554 can operate from 2.25 to 3.6 volts. The V554 is fabricated with an advanced CMOS process. Enhanced FIFO The V554 QUART provides a solution that supports 16 bytes of transmit and receive FIFO memory, instead of one byte in the ST16C454. The V554 is designed to work with high performance data communication systems, that require fast data processing time. Increased performance is realized in the V554 by the larger transmit and receive FIFOs and Receiver FIFO trigger level control. This allows the external processor to handle more networking tasks within a given time. This increases the service interval giving the external CPU additional time for other applications and reducing the overall UART interrupt servicing time. Data Bus Interface, Intel or Motorola Type The V554 provides a single host interface for the 4 UARTs and supports Intel or Motorola microprocessor (CPU) data bus interface. The Intel bus compatible interface allows direct interconnect to Intel compatible type of CPUs using IOR#, IOW# and CSA#, CSB#, CSC# or CSD# inputs for data bus operation. The Motorola bus compatible interface instead uses the R/W#, CS#, A3 and A4 signals for data bus transactions. Few data bus interface signals change their functions depending on user’s selection, see pin description for details. The Intel and Motorola bus interface selection is made through the pin 16/68#. Data Rate The V554 is capable of operation up to 4 Mbps at 3.3V. The device can operate at 3.3V with a crystal oscillator of up to 24 MHz crystal on pins XTAL1 and XTAL2, or external clock source of 64 MHz on XTAL1 pin. With a typical crystal of 14.7456 MHz and through a software option, the user can set the sampling rate for data rates of up to 921.6 Kbps. Enhanced Features The rich feature set of the V554 is available through the internal registers. Selectable receive FIFO trigger levels, programmable baud rates, infrared encoder/decoder interface and modem interface controls are all standard features. In the 16 mode INTSEL and MCR bit-3 can be configured to provide a software controlled or continuous interrupt capability. For backward compatibility to the ST16C554, the 64-pin LQFP does not have the INTSEL pin. Instead, two different LQFP packages are offered. The XR16V554DIV operates in the continuous interrupt enable mode by internally bonding INTSEL to VCC. The XR16V554IV operates in conjunction with MCR bit-3 by internally bonding INTSEL to GND. 9 XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO REV. 1.0.3 2.0 FUNCTIONAL DESCRIPTIONS 2.1 CPU Interface The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and write transactions. The V554 data interface supports the Intel compatible types of CPUs and it is compatible to the industry standard 16C550 UART. No clock (oscillator nor external clock) is required for a data bus transaction. Each bus cycle is asynchronous using CS# A-D, IOR# and IOW# or CS#, R/W#, A4 and A3 inputs. All four UART channels share the same data bus for host operations. A typical data bus interconnection for Intel and Motorola mode is shown in Figure 4. FIGURE 4. XR16V554 TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A0 A1 A2 VCC TXA RXA UART Channel A DTRA# RTSA# CTSA# DSRA# CDA# IOW# UART_CSA# UART_CSB# UART_CSC# UART_CSD# CSA# CSB# CSC# CSD# UART_INTA INTA UART_INTB INTB UART_INTC INTC UART_INTD INTD UART_RESET Serial Interface of RS-232 RIA# IOR# IOR# IOW# VCC UART Channel B UART Channel C UART Channel D Similar to Ch A Serial Interface of RS-232 Similar to Ch A Similar to Ch A RESET VCC GND 16/68# Intel Data Bus (16 Mode) Interconnections VCC D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A0 A1 DSRA# A2 RIA# A3 A4 CSB# CSC# CSD# VCC IOR# VCC TXA RXA UART Channel A DTRA# RTSA# CTSA# Serial Interface of RS-232 CDA# UART Channel B Similar to Ch A IOW# R/W# UART_CS# VCC CSA# VCC UART_IRQ# INTA INTB INTC INTD RESET# 16/68# (no connect) (no connect) (no connect) UART_RESET# UART Channel C UART Channel D Similar to Ch A Similar to Ch A GND Motorola Data Bus (68 Mode) Interconnections 10 Serial Interface of RS-232 XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO REV. 1.0.3 2.2 Device Reset The RESET input resets the internal registers and the serial interface outputs in all channels to their default state (see Table 13). An active high pulse of longer than 40 ns duration will be required to activate the reset function in the device. Following a power-on reset or an external reset, the V554 is software compatible with previous generation of UARTs, 16C454 and 16C554. 2.3 Channel Selection The UART provides the user with the capability to bi-directionally transfer information between an external CPU and an external serial communication device. During Intel Bus Mode (16/68# pin is connected to VCC), a logic 0 on chip select pins, CSA#, CSB#, CSC# or CSD# allows the user to select UART channel A, B, C or D to configure, send transmit data and/or unload receive data to/from the UART. Selecting all four UARTs can be useful during power up initialization to write to the same internal registers, but do not attempt to read from all four uarts simultaneously. Individual channel select functions are shown in Table 1. TABLE 1: CHANNEL A-D SELECT IN 16 MODE CSA# CSB# CSC# CSD# FUNCTION 1 1 1 1 UART de-selected 0 1 1 1 Channel A selected 1 0 1 1 Channel B selected 1 1 0 1 Channel C selected 1 1 1 0 Channel D selected 0 0 0 0 Channels A-D selected During Motorola Bus Mode (16/68# pin is connected to GND), the package interface pins are configured for connection with Motorola, and other popular microprocessor bus types. In this mode the V554 decodes two additional addresses, A3 and A4, to select one of the four UART ports. The A3 and A4 address decode function is used only when in the Motorola Bus Mode. See Table 2. TABLE 2: CHANNEL A-D SELECT IN 68 MODE CS# A4 A3 FUNCTION 1 X X UART de-selected 0 0 0 Channel A selected 0 0 1 Channel B selected 0 1 0 Channel C selected 0 1 1 Channel D selected 11 XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO 2.4 REV. 1.0.3 Channels A-D Internal Registers Each UART channel in the V554 has a set of enhanced registers for controlling, monitoring and data loading and unloading. The configuration register set is compatible to those already available in the standard single 16C550. These registers function as data holding registers (THR/RHR), interrupt status and control registers (ISR/IER), a FIFO control register (FCR), receive line status and control registers (LSR/LCR), modem status and control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/DLM), and a user accessible scratchpad register (SPR). All the register functions are discussed in full detail later in “Section 3.0, UART Internal Registers” on page 19. 2.5 INT Ouputs for Channels A-D The interrupt outputs change according to the operating mode and enhanced features setup. Table 3 and 4 summarize the operating behavior for the transmitter and receiver. Also see Figure 18 through 23. TABLE 3: INT PIN OPERATION FOR TRANSMITTER FOR CHANNELS A-D FCR BIT-0 = 0 (FIFO DISABLED) INT Pin LOW = a byte in THR HIGH = THR empty FCR BIT-0 = 1 (FIFO ENABLED) FCR Bit-3 = 0 (DMA Mode Disabled) LOW = FIFO above trigger level HIGH = FIFO below trigger level or FIFO empty FCR Bit-3 = 1 (DMA Mode Enabled) LOW = FIFO above trigger level HIGH = FIFO below trigger level or FIFO empty TABLE 4: INT PIN OPERATION FOR RECEIVER FOR CHANNELS A-D FCR BIT-0 = 0 (FIFO DISABLED) FCR BIT-0 = 1 (FIFO ENABLED) FCR Bit-3 = 0 (DMA Mode Disabled) INT Pin 2.6 LOW = no data HIGH = 1 byte LOW = FIFO below trigger level HIGH = FIFO above trigger level FCR Bit-3 = 1 (DMA Mode Enabled) LOW = FIFO below trigger level HIGH = FIFO above trigger level DMA Mode The device does not support direct memory access. The DMA Mode (a legacy term) in this document does not mean “direct memory access” but refers to data block transfer operation. The DMA mode affects the state of the RXRDY# A-D and TXRDY# A-D output pins. The transmit and receive FIFO trigger levels provide additional flexibility to the user for block mode operation. The LSR bits 5-6 provide an indication when the transmitter is empty or has an empty location(s) for more data. The user can optionally operate the transmit and receive FIFO in the DMA mode (FCR bit-3 = 1). When the transmit and receive FIFOs are enabled and the DMA mode is disabled (FCR bit-3 = 0), the V554 is placed in single-character mode for data transmit or receive operation. When DMA mode is enabled (FCR bit-3 = 1), the user takes advantage of block mode operation by loading or unloading the FIFO in a block sequence determined by the programmed trigger level. The following table show their behavior. Also see Figure 18 through 23. 12 XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO REV. 1.0.3 TABLE 5: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE FOR CHANNELS A-D PINS FCR BIT-0=0 (FIFO DISABLED) FCR BIT-0=1 (FIFO ENABLED) FCR BIT-3 = 0 (DMA MODE DISABLED) FCR BIT-3 = 1 (DMA MODE ENABLED) RXRDY# LOW = 1 byte HIGH = no data LOW = at least 1 byte in FIFO HIGH = FIFO empty HIGH to LOW transition when FIFO reaches the trigger level, or timeout occurs LOW to HIGH transition when FIFO empties TXRDY# LOW = THR empty HIGH = byte in THR LOW = FIFO empty HIGH = at least 1 byte in FIFO LOW = FIFO has at least 1 empty location HIGH = FIFO is full 2.7 Crystal Oscillator or External Clock Input The V554 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the oscillator or external clock buffer input with XTAL2 pin being the output. Caution: the XTAL1 input is not 5V tolerant. For programming details, see “Section 2.8, Programmable Baud Rate Generator” on page 13. FIGURE 5. TYPICAL CRYSTAL CONNECTIONS R=300K to 400K XTAL1 14.7456 MHz XTAL2 C2 22-47pF C1 22-47pF The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant, fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100ppm frequency tolerance) connected externally between the XTAL1 and XTAL2 pins. Typical oscillator connections are shown in Figure 5. Alternatively, an external clock can be connected to the XTAL1 pin to clock the internal baud rate generator for standard or custom rates. For further reading on oscillator circuit please see application note DAN108 on EXAR’s web site. 2.8 Programmable Baud Rate Generator Each UART has its own Baud Rate Generator (BRG) for the transmitter and receiver. The BRG further divides this clock by a programmable divisor between 1 and (216 - 0.0625) in increments of 0.0625 (1/16) to obtain a 16X sampling rate clock of the serial data rate. The sampling rate clock is used by the transmitter for data bit shifting and receiver for data sampling. The BRG divisor defaults to the maximum baud rate (DLL = 0x01 and DLM = 0x00) upon power up and reset. Programming the Baud Rate Generator Registers DLL and DLM provides the capability for selecting the operating data rate. Table 6 shows the standard data rates available with a 24MHz crystal or external clock at 16X clock rate. If the pre-scaler is used (MCR bit-7 = 1), the output data rate will be 4 times less than that shown in Table 6. 13 XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO REV. 1.0.3 FIGURE 6. BAUD RATE GENERATOR To Other Channels DLL and DLM Registers XTAL1 XTAL2 Crystal Osc / Buffer Programmable Baud Rate Generator Logic 16 X Sampling Rate Clock to Transmitter and Receiver TABLE 6: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK OUTPUT Data Rate MCR Bit-7=0 DIVISOR FOR 16x Clock (Decimal) DIVISOR FOR 16x Clock (HEX) DLM PROGRAM VALUE (HEX) DLL PROGRAM VALUE (HEX) DATA RATE ERROR (%) 400 2304 900 09 00 0 2400 384 180 01 80 0 4800 192 C0 00 C0 0 9600 96 60 00 60 0 19.2k 48 30 00 30 0 38.4k 24 18 00 18 0 76.8k 12 0C 00 0C 0 153.6k 6 06 00 06 0 230.4k 4 04 00 04 0 460.8k 2 02 00 02 0 921.6k 1 01 00 01 0 2.9 Transmitter The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 16 bytes of FIFO which includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X internal sampling clock. A bit time is 16X clock periods. The transmitter sends the start-bit followed by the number of data bits, inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and TSR are reported in the Line Status Register (LSR bit-5 and bit-6). 14 XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO REV. 1.0.3 2.9.1 Transmit Holding Register (THR) - Write Only The transmit holding register is an 8-bit register providing a data interface to the host processor. The host writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits, parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input register to the transmit FIFO of 16 bytes when FIFO operation is enabled by FCR bit-0. Every time a write operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data location. 2.9.2 Transmitter Operation in non-FIFO Mode The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty. FIGURE 7. TRANSMITTER OPERATION IN NON-FIFO MODE Data Byte 16X Clock Transmit Holding Register (THR) THR Interrupt (ISR bit-1) Enabled by IER bit-1 M S B Transmit Shift Register (TSR) L S B TXNOFIFO1 2.9.3 Transmitter Operation in FIFO Mode The host may fill the transmit FIFO with up to 16 bytes of transmit data. The THR empty flag (LSR bit-5) is set whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the FIFO becomes empty. The transmit empty interrupt is enabled by IER bit-1. The TSR flag (LSR bit-6) is set when TSR/FIFO becomes empty. FIGURE 8. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE Transmit Data Byte 16X Clock Transmit FIFO THR Interrupt (ISR bit-1) When it becomes empty. FIFO is Enabled by FCR Bit-0=1 Transmit Data Shift Register ( TSR ) TXFIFO1 15 XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO 2.10 REV. 1.0.3 Receiver The receiver section contains an 8-bit Receive Shift Register (RSR) and 16 bytes of FIFO which includes a byte-wide Receive Holding Register (RHR). The RSR uses the 16X clock for timing. It verifies and validates every bit on the incoming character in the middle of each data bit. On the falling edge of a start or false start bit, an internal receiver counter starts counting at the 16X clock rate. After 8 clocks the start bit period should be at the center of the start bit. At this time the start bit is sampled and if it is still LOW it is validated. Evaluating the start bit in this manner prevents the receiver from assembling a false character. The rest of the data bits and stop bits are sampled and validated in this same manner to prevent false framing. If there were any error(s), they are reported in the LSR register bits 2-4. Upon unloading the receive data byte from RHR, the receive FIFO pointer is bumped and the error tags are immediately updated to reflect the status of the data byte in RHR register. RHR can generate a receive data ready interrupt upon receiving a character or delay until it reaches the FIFO trigger level. Furthermore, data delivery to the host is guaranteed by a receive data ready time-out interrupt when data is not received for 4 word lengths as defined by LCR[1:0] plus 12 bits time. This is equivalent to 3.7-4.6 character times. The RHR interrupt is enabled by IER bit-0. See Figure 9 and Figure 10 below. 2.10.1 Receive Holding Register (RHR) - Read-Only The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift Register. It provides the receive data interface to the host processor. The RHR register is part of the receive FIFO of 16 bytes by 11-bit wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data byte are immediately updated in the LSR bits 2-4. FIGURE 9. RECEIVER OPERATION IN NON-FIFO MODE 16X Clock Receive Data Shift Register (RSR) Receive Data Byte and Errors Error Tags in LSR bits 4:2 Receive Data Holding Register (RHR) Data Bit Validation Receive Data Characters RHR Interrupt (ISR bit-2) RXFIFO1 16 XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO REV. 1.0.3 FIGURE 10. RECEIVER OPERATION IN FIFO 16X C lock R eceive D ata Shift R egister (R SR ) D ata Bit V alidation 16 bytes by 11-bit w ide FIFO Error Tags (16-sets) D ata falls to 4 R eceive D ata FIFO FIFO Trigger=8 Error Tags in LSR bits 4:2 D ata fills to 14 R eceive D ata Byte and Errors R eceive D ata C haracters E xam ple : - R X FIFO trigger level selected at 8 bytes (See N ote Below ) Asking for sending data w hen data falls below the flow control trigger level to restart rem ote transm itter. R H R Interrupt (IS R bit-2) program m ed for desired FIFO trigger level. FIFO is Enabled by FC R bit-0=1 Asking for stopping data w hen data fills above the flow control trigger level to suspend rem ote transm itter. R eceive D ata R XFIFO 1 17 XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO 2.11 REV. 1.0.3 Internal Loopback The V554 UART provides an internal loopback capability for system diagnostic purposes. The internal loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally. Figure 11 shows how the modem port signals are re-configured. Transmit data from the transmit shift register output is internally routed to the receive shift register input allowing the system to receive the same data that it was sending. The TX pin is held HIGH or mark condition while RTS# and DTR# are de-asserted, and CTS#, DSR# CD# and RI# inputs are ignored. Caution: the RX input must be held HIGH during loopback test else upon exiting the loopback test the UART may detect and report a false “break” signal. FIGURE 11. INTERNAL LOOPBACK VCC TX A-D Transmit Shift Register (THR/FIFO) Receive Shift Register (RHR/FIFO) RX A-D VCC RTS# A-D Modem / General Purpose Control Logic Internal Data Bus Lines and Control Signals MCR bit-4=1 RTS# CTS# CTS# A-D VCC DTR# A-D DTR# DSR# DSR# A-D OP1# RI# OP2# CD# RI# A-D CD# A-D 18 XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO REV. 1.0.3 3.0 UART INTERNAL REGISTERS Each UART channel in the V554 has its own set of configuration registers selected by address lines A0, A1 and A2 with a specific channel selected (See Table 1 and Table 2). The complete register set is shown on Table 7 and Table 8. TABLE 7: UART INTERNAL REGISTERS A2,A1,A0 ADDRESSES REGISTER READ/WRITE COMMENTS 16C550 COMPATIBLE REGISTERS 0 0 0 RHR - Receive Holding Register THR - Transmit Holding Register Read-only Write-only 0 0 0 DLL - Divisor LSB Read/Write 0 0 1 DLM - Divisor MSB Read/Write 0 0 1 IER - Interrupt Enable Register Read/Write 0 1 0 ISR - Interrupt Status Register FCR - FIFO Control Register Read-only Write-only 0 1 1 LCR - Line Control Register Read/Write 1 0 0 MCR - Modem Control Register Read/Write 1 0 1 LSR - Line Status Register Read-only 1 1 0 MSR - Modem Status Register Read-only 1 1 1 SPR - Scratch Pad Register Read/Write 19 LCR[7] = 0 LCR[7] = 1, LCR ≠ 0xBF LCR[7] = 0 LCR[7] = 0 XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO REV. 1.0.3 TABLE 8: INTERNAL REGISTERS DESCRIPTION ADDRESS A2-A0 REG NAME READ/ WRITE BIT-7 BIT-6 BIT-5 BIT-4 BIT-3 BIT-2 BIT-1 BIT-0 COMMENT 16C550 Compatible Registers 000 RHR RD Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 000 THR WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 001 IER RD/WR 0 0 0 0 010 ISR RD FIFOs FIFOs Enabled Enabled 0 0 INT Source Bit-3 INT INT INT Source Source Source Bit-2 Bit-1 Bit-0 010 FCR WR RX FIFO RX FIFO Trigger Trigger 0 0 DMA Mode Enable TX FIFO Reset 011 LCR RD/WR Divisor Enable Set TX Break Set Parity Even Parity Parity Enable Stop Bits 100 MCR RD/WR 0 0 0 Internal Lopback Enable INT Output Enable (OP2#) 101 LSR RD/WR RX FIFO Global Error THR & TSR Empty THR Empty RX Break RX Framing Error RX Parity Error RX Overrun Error RX Data Ready Modem RX Line TX RX Stat. Int. Stat. Empty Data Enable Int. Int Int. Enable Enable Enable RX FIFO Reset LCR[7] = 0 FIFOs Enable Word Word Length Length Bit-1 Bit-0 Rsvd RTS# DTR# (OP1#) Output Output Control Control 110 MSR RD/WR CD# Input RI# Input DSR# Input CTS# Input Delta CD# Delta RI# Delta DSR# Delta CTS# 111 SPR RD/WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 LCR[7] = 0 Baud Rate Generator Divisor 000 DLL RD/WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 001 DLM RD/WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 LCR[7]=1 LCR≠0xBF 4.0 INTERNAL REGISTER DESCRIPTIONS 4.1 Receive Holding Register (RHR) - Read- Only SEE”RECEIVER” ON PAGE 16. 4.2 Transmit Holding Register (THR) - Write-Only SEE”TRANSMITTER” ON PAGE 14. 4.3 Interrupt Enable Register (IER) - Read/Write The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR). 20 XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO REV. 1.0.3 4.3.1 IER versus Receive FIFO Interrupt Mode Operation When the receive FIFO (FCR BIT-0 = 1) and receive interrupts (IER BIT-0 = 1) are enabled, the RHR interrupts (see ISR bits 2 and 3) status will reflect the following: A. The receive data available interrupts are issued to the host when the FIFO has reached the programmed trigger level. It will be cleared when the FIFO drops below the programmed trigger level. B. FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register status bit and the interrupt will be cleared when the FIFO drops below the trigger level. C. The receive data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to the receive FIFO. It is reset when the FIFO is empty. 4.3.2 IER versus Receive/Transmit FIFO Polled Mode Operation When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR16V554 in the FIFO polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). A. LSR BIT-0 indicates there is data in RHR or RX FIFO. B. LSR BIT-1 indicates an overrun error has occurred and that data in the FIFO may not be valid. C. LSR BIT 2-4 provides the type of receive data errors encountered for the data byte in RHR, if any. D. LSR BIT-5 indicates THR is empty. E. LSR BIT-6 indicates when both the transmit FIFO and TSR are empty. F. LSR BIT-7 indicates a data error in at least one character in the RX FIFO. IER[0]: RHR Interrupt Enable The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or when the receive FIFO has reached the programmed trigger level in the FIFO mode. • Logic 0 = Disable the receive data ready interrupt (default). • Logic 1 = Enable the receiver data ready interrupt. IER[1]: THR Interrupt Enable This bit enables the Transmit Ready interrupt which is issued whenever the THR becomes empty. If the THR is empty when this bit is enabled, an interrupt will be generated. • Logic 0 = Disable Transmit Ready interrupt (default). • Logic 1 = Enable Transmit Ready interrupt. IER[2]: Receive Line Status Interrupt Enable If any of the LSR register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controller about the error status of the current data byte in FIFO. LSR bit-1 generates an interrupt immediately when an overrun occurs. LSR bits 2-4 generate an interrupt when the character in the RHR has an error. • Logic 0 = Disable the receiver line status interrupt (default). • Logic 1 = Enable the receiver line status interrupt. IER[3]: Modem Status Interrupt Enable • Logic 0 = Disable the modem status register interrupt (default). • Logic 1 = Enable the modem status register interrupt. IER[7:4]: Reserved 21 XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO 4.4 REV. 1.0.3 Interrupt Status Register (ISR) The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt Source Table, Table 9, shows the data values (bit 0-3) for the interrupt priority levels and the interrupt sources associated with each of these interrupt levels. 4.4.1 Interrupt Generation: • LSR is by any of the LSR bits 1, 2, 3 and 4. • RXRDY Data Ready is by RX trigger level. • RXRDY Data Time-out is by a 4-char plus 12 bits delay timer. • TXRDY is by TX FIFO empty. • MSR is by any of the MSR bits 0, 1, 2 and 3. 4.4.2 Interrupt Clearing: • LSR interrupt is cleared by a read to the LSR register. • RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level. • RXRDY Time-out interrupt is cleared by reading RHR. • TXRDY interrupt is cleared by a read to the ISR register or writing to THR. • MSR interrupt is cleared by a read to the MSR register. ] TABLE 9: INTERRUPT SOURCE AND PRIORITY LEVEL PRIORITY ISR REGISTER STATUS BITS SOURCE OF INTERRUPT LEVEL BIT-3 BIT-2 BIT-1 BIT-0 1 0 1 1 0 LSR (Receiver Line Status Register) 2 1 1 0 0 RXRDY (Receive Data Time-out) 3 0 1 0 0 RXRDY (Received Data Ready) 4 0 0 1 0 TXRDY (Transmit Ready) 5 0 0 0 0 MSR (Modem Status Register) - 0 0 0 1 None (default) ISR[0]: Interrupt Status • Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt service routine. • Logic 1 = No interrupt pending (default condition). ISR[3:1]: Interrupt Status These bits indicate the source for a pending interrupt at interrupt priority levels (See Interrupt Source Table 9). ISR[4]: Reserved ISR[5]: Reserved 22 XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO REV. 1.0.3 ISR[7:6]: FIFO Enable Status These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are enabled. 4.5 FIFO Control Register (FCR) - Write-Only This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger levels, and select the DMA mode. The DMA, and FIFO modes are defined as follows: FCR[0]: TX and RX FIFO Enable • Logic 0 = Disable the transmit and receive FIFO (default). • Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are written or they will not be programmed. FCR[1]: RX FIFO Reset This bit is only active when FCR bit-0 is a ‘1’. • Logic 0 = No receive FIFO reset (default). • Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not cleared or altered). This bit will return to a logic 0 after resetting the FIFO. FCR[2]: TX FIFO Reset This bit is only active when FCR bit-0 is a ‘1’. • Logic 0 = No transmit FIFO reset (default). • Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not cleared or altered). This bit will return to a logic 0 after resetting the FIFO. FCR[3]: DMA Mode Select Controls the behavior of the TXRDY and RXRDY pins. See DMA operation section for details. • Logic 0 = Normal Operation (default). • Logic 1 = DMA Mode. FCR[5:4]: Reserved FCR[7:6]: Receive FIFO Trigger Select (logic 0 = default, RX trigger level =1) These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when the number of the characters in the FIFO crosses the trigger level. Table 10 shows the complete selections. TABLE 10: RECEIVE FIFO TRIGGER LEVEL SELECTION FCR BIT-7 FCR BIT-6 RECEIVE TRIGGER LEVEL 0 0 1 1 0 1 0 1 1 4 8 14 23 XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO 4.6 REV. 1.0.3 Line Control Register (LCR) - Read/Write The Line Control Register is used to specify the asynchronous data communication format. The word or character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. LCR[1:0]: TX and RX Word Length Select These two bits specify the word length to be transmitted or received. BIT-1 BIT-0 WORD LENGTH 0 0 5 (default) 0 1 6 1 0 7 1 1 8 LCR[2]: TX and RX Stop-bit Length Select The length of stop bit is specified by this bit in conjunction with the programmed word length. LENGTH STOP BIT LENGTH (BIT TIME(S)) 0 5,6,7,8 1 (default) 1 5 1-1/2 1 6,7,8 2 BIT-2 WORD LCR[3]: TX and RX Parity Select Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data integrity check. See Table 11 for parity selection summary below. • Logic 0 = No parity. • Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the data character received. LCR[4]: TX and RX Parity Select If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR BIT-4 selects the even or odd parity format. • Logic 0 = ODD Parity is generated by forcing an odd number of logic 1’s in the transmitted character. The receiver must be programmed to check the same format (default). • Logic 1 = EVEN Parity is generated by forcing an even number of logic 1’s in the transmitted character. The receiver must be programmed to check the same format. 24 XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO REV. 1.0.3 LCR[5]: TX and RX Parity Select If the parity bit is enabled, LCR BIT-5 selects the forced parity format. • LCR BIT-5 = logic 0, parity is not forced (default). • LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced to HIGH for the transmit and receive data. • LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit is forced to LOW for the transmit and receive data. TABLE 11: PARITY SELECTION LCR BIT-5 LCR BIT-4 LCR BIT-3 PARITY SELECTION X X 0 No parity 0 0 1 Odd parity 0 1 1 Even parity 1 0 1 Force parity to mark, HIGH 1 1 1 Forced parity to space, LOW LCR[6]: Transmit Break Enable When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a “space’, logic 0, state). This condition remains, until disabled by setting LCR bit-6 to a logic 0. • Logic 0 = No TX break condition. (default) • Logic 1 = Forces the transmitter output (TX) to a “space”, logic 0, for alerting the remote receiver of a line break condition. LCR[7]: Baud Rate Divisors Enable Baud rate generator divisor (DLL/DLM) enable. • Logic 0 = Data registers are selected (default). • Logic 1 = Divisor latch registers are selected. 4.7 Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs. MCR[0]: DTR# Output The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as a general purpose output. • Logic 0 = Force DTR# output HIGH (default). • Logic 1 = Force DTR# output LOW. MCR[1]: RTS# Output The RTS# pin is a modem control output. If the modem interface is not used, this output may be used as a general purpose output. • Logic 0 = Force RTS# output HIGH (default). • Logic 1 = Force RTS# output LOW. MCR[2]: Reserved OP1# is not available as an output pin on the V554. But it is available for use during Internal Loopback Mode. In the Loopback Mode, this bit is used to write the state of the modem RI# interface signal. 25 XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO REV. 1.0.3 MCR[3]: INT Output Enable Enable or disable INT outputs to become active or in three-state. This function is associated with the INTSEL input, see below table for details. This bit is also used to control the OP2# signal during internal loopback mode. INTSEL pin must be LOW during 68 mode. • Logic 0 = INT (A-D) outputs disabled (three state) in the 16 mode (default). During internal loopback mode, OP2# is HIGH. • Logic 1 = INT (A-D) outputs enabled (active) in the 16 mode. During internal loopback mode, OP2# is LOW. TABLE 12: INT OUTPUT MODES INTSEL PIN MCR BIT-3 INT A-D OUTPUTS IN 16 MODE 0 0 Three-State 0 1 Active 1 X Active MCR[4]: Internal Loopback Enable • Logic 0 = Disable loopback mode (default). • Logic 1 = Enable local loopback mode, see loopback section and Figure 11. MCR[7:5]: Reserved 4.8 Line Status Register (LSR) - Read/Write This register is writeable but it is not recommended. The LSR provides the status of data transfers between the UART and the host. If IER bit-2 is enabled, LSR bit-1 will generate an interrupt immediately and LSR bits 2-4 will generate an interrupt when a character with an error is in the RHR. LSR[0]: Receive Data Ready Indicator • Logic 0 = No data in receive holding register or FIFO (default). • Logic 1 = Data has been received and is saved in the receive holding register or FIFO. LSR[1]: Receiver Overrun Flag • Logic 0 = No overrun error (default). • Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens when additional data arrives while the FIFO is full. In this case the previous data in the receive shift register is overwritten. Note that under this condition the data byte in the receive shift register is not transferred into the FIFO, therefore the data in the FIFO is not corrupted by the error. LSR[2]: Receive Data Parity Error Tag • Logic 0 = No parity error (default). • Logic 1 = Parity error. The receive character in RHR does not have correct parity information and is suspect. This error is associated with the character available for reading in RHR. LSR[3]: Receive Data Framing Error Tag • Logic 0 = No framing error (default). • Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with the character available for reading in RHR. 26 XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO REV. 1.0.3 LSR[4]: Receive Break Tag • Logic 0 = No break condition (default). • Logic 1 = The receiver received a break signal (RX was LOW for at least one character frame time). In the FIFO mode, only one break character is loaded into the FIFO. The break indication remains until the RX input returns to the idle condition, “mark” or HIGH. LSR[5]: Transmit Holding Register Empty Flag This bit is the Transmit Holding Register Empty indicator. The THR bit is set to a logic 1 when the last data byte is transferred from the transmit holding register to the transmit shift register. The bit is reset to logic 0 concurrently with the data loading to the transmit holding register by the host. In the FIFO mode this bit is set when the transmit FIFO is empty, it is cleared when the transmit FIFO contains at least 1 byte. LSR[6]: THR and TSR Empty Flag This bit is set to a logic 1 whenever the transmitter goes idle. It is set to logic 0 whenever either the THR or TSR contains a data character. In the FIFO mode this bit is set to a logic 1 whenever the transmit FIFO and transmit shift register are both empty. LSR[7]: Receive FIFO Data Error Flag • Logic 0 = No FIFO error (default). • Logic 1 = A global indicator for the sum of all error bits in the RX FIFO. At least one parity error, framing error or break indication is in the FIFO data. This bit clears when there is no more error(s) in any of the bytes in the RX FIFO. 4.9 Modem Status Register (MSR) - Read/Write This register is writeable but it is not recommended. The MSR provides the current state of the modem interface input signals. Lower four bits of this register are used to indicate the changed information. These bits are set to a logic 1 whenever a signal from the modem changes state. These bits may be used for general purpose inputs when they are not used with modem signals. MSR[0]: Delta CTS# Input Flag • Logic 0 = No change on CTS# input (default). • Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt will be generated if MSR interrupt is enabled (IER bit-3). MSR[1]: Delta DSR# Input Flag • Logic 0 = No change on DSR# input (default). • Logic 1 = The DSR# input has changed state since the last time it was monitored. A modem status interrupt will be generated if MSR interrupt is enabled (IER bit-3). MSR[2]: Delta RI# Input Flag • Logic 0 = No change on RI# input (default). • Logic 1 = The RI# input has changed from LOW to HIGH, ending of the ringing signal. A modem status interrupt will be generated if MSR interrupt is enabled (IER bit-3). MSR[3]: Delta CD# Input Flag • Logic 0 = No change on CD# input (default). • Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem status interrupt will be generated if MSR interrupt is enabled (IER bit-3). 27 XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO REV. 1.0.3 MSR[4]: CTS Input Status A HIGH on the CTS# pin will stop UART transmitter as soon as the current character has finished transmission, and a LOW will resume data transmission. Normally MSR bit-4 bit is the compliment of the CTS# input. However in the loopback mode, this bit is equivalent to the RTS# bit in the MCR register. The CTS# input may be used as a general purpose input when the modem interface is not used. MSR[5]: DSR Input Status Normally this bit is the complement of the DSR# input. In the loopback mode, this bit is equivalent to the DTR# bit in the MCR register. The DSR# input may be used as a general purpose input when the modem interface is not used. MSR[6]: RI Input Status Normally this bit is the complement of the RI# input. In the loopback mode this bit is equivalent to bit-2 in the MCR register. The RI# input may be used as a general purpose input when the modem interface is not used. MSR[7]: CD Input Status Normally this bit is the complement of the CD# input. In the loopback mode this bit is equivalent to bit-3 in the MCR register. The CD# input may be used as a general purpose input when the modem interface is not used. 4.10 Scratch Pad Register (SPR) - Read/Write This is a 8-bit general purpose register for the user to store temporary data. 4.11 Baud Rate Generator Registers (DLL and DLM) - Read/Write These registers make-up the value of the baud rate divisor. The concatenation of the contents of DLM and DLL gives the 16-bit divisor value. See ”Section 2.8, Programmable Baud Rate Generator” on page 13. 28 XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO REV. 1.0.3 TABLE 13: UART RESET CONDITIONS FOR CHANNELS A-D REGISTERS RESET STATE DLM, DLL DLM = 0x00 and DLL = 0x01. Only resets to these values during a power up. They do not reset when the Reset Pin is asserted. RHR Bits 7-0 = 0xXX THR Bits 7-0 = 0xXX IER Bits 7-0 = 0x00 FCR Bits 7-0 = 0x00 ISR Bits 7-0 = 0x01 LCR Bits 7-0 = 0x00 MCR Bits 7-0 = 0x00 LSR Bits 7-0 = 0x60 MSR Bits 3-0 = Logic 0 Bits 7-4 = Logic levels of the inputs inverted SPR Bits 7-0 = 0xFF I/O SIGNALS RESET STATE TX HIGH RTS# HIGH DTR# HIGH RXRDY# HIGH TXRDY# LOW INT (16 Mode) XR16V554 = Three-State Condition (INTSEL = LOW) XR16V554 = LOW (INTSEL = HIGH) XR16V554D = LOW IRQ# (68 Mode) HIGH (INTSEL = LOW) 29 XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO REV. 1.0.3 ABSOLUTE MAXIMUM RATINGS Power Supply Range 4 Volts Voltage at Any Pin GND-0.3 V to 5.5 V Operating Temperature -40o to +85oC Storage Temperature -65o to +150oC Package Dissipation 500 mW TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%) Thermal Resistance (48-QFN) theta-ja = 28oC/W, theta-jc = 10.5oC/W Thermal Resistance (64-LQFP) theta-ja = 50oC/W, theta-jc = 11oC/W Thermal Resistance (68-PLCC) theta-ja = 46oC/W, theta-jc = 17oC/W Thermal Resistance (80-LQFP) theta-ja = 37oC/W, theta-jc = 7oC/W ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS UNLESS OTHERWISE NOTED: TA = -40O TO +85OC, VCC IS 2.25 TO 3.6V SYMBOL PARAMETER LIMITS 2.5V MIN MAX LIMITS 3.3V MIN MAX UNITS CONDITIONS VILCK Clock Input Low Level -0.3 0.4 -0.3 0.6 V VIHCK Clock Input High Level 2.0 VCC 2.4 VCC V VIL Input Low Voltage -0.3 0.5 -0.3 0.7 V VIH Input High Voltage 1.8 5.5 2.0 5.5 V VOL Output Low Voltage 0.4 V V IOL = 6 mA V V IOH = -4 mA 0.4 VOH Output High Voltage 2.0 1.8 IIL Input Low Leakage Current ±15 ±15 uA IIH Input High Leakage Current ±15 ±15 uA CIN Input Pin Capacitance 5 5 pF ICC Power Supply Current 1.7 3 mA 30 IOL = 4 mA IOH = -2 mA Ext Clk = 2MHz XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO REV. 1.0.3 AC ELECTRICAL CHARACTERISTICS TA = -40O TO +85OC, VCC IS 2.25 TO 3.6V, 70 PF LOAD WHERE APPLICABLE SYMBOL PARAMETER LIMITS 2.5V ± 10% MIN MAX LIMITS 3.3V ± 10% MIN MAX UNIT XTAL1 UART Crystal Frequency 24 24 MHz ECLK External Clock Frequency 50 64 MHz TECLK External Clock Time Period 10 7 ns TAS Address Setup Time (16 Mode) 0 0 ns TAH Address Hold Time (16 Mode) 0 0 ns TCS Chip Select Width (16 Mode) 50 40 ns TRD IOR# Strobe Width (16 Mode) 50 40 ns TDY Read Cycle Delay (16 Mode) 50 40 ns TRDV Data Access Time (16 Mode) 45 35 ns TDD Data Disable Time (16 Mode) 10 10 ns TWR IOW# Strobe Width (16 Mode) 50 40 ns TDY Write Cycle Delay (16 Mode) 50 40 ns TDS Data Setup Time (16 Mode) 10 10 ns TDH Data Hold Time (16 Mode) 5 5 ns TADS Address Setup (68 Mode) 0 0 ns TADH Address Hold (68 Mode) 0 0 ns TRWS R/W# Setup to CS# (68 Mode) 0 0 ns TRDA Data Access Time (68 mode) 45 35 ns TRDH Data Disable Time (68 mode) 10 10 ns TWDS Write Data Setup (68 mode) 10 10 ns TWDH Write Data Hold (68 Mode) 5 5 ns TRWH CS# De-asserted to R/W# De-asserted (68 Mode) 10 5 ns TCSL CS# Strobe Width (68 Mode) 50 40 ns TCSD CS# Cycle Delay (68 Mode) 50 40 ns TWDO Delay From IOW# To Output 50 50 ns TMOD Delay To Set Interrupt From MODEM Input 50 50 ns TRSI Delay To Reset Interrupt From IOR# 50 50 ns 31 XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO REV. 1.0.3 AC ELECTRICAL CHARACTERISTICS TA = -40O TO +85OC, VCC IS 2.25 TO 3.6V, 70 PF LOAD WHERE APPLICABLE SYMBOL PARAMETER LIMITS 2.5V ± 10% MAX MIN LIMITS 3.3V ± 10% MAX MIN UNIT TSSI Delay From Stop To Set Interrupt 1 1 Bclk TRRI Delay From IOR# To Reset Interrupt 45 45 ns TSI Delay From Start To Interrupt 45 45 ns TINT Delay From Initial INT Reset To Transmit Start 24 Bclk TWRI Delay From IOW# To Reset Interrupt 45 45 ns TSSR Delay From Stop To Set RXRDY# 1 1 Bclk TRR Delay From IOR# To Reset RXRDY# 45 45 ns TWT Delay From IOW# To Set TXRDY# 45 45 ns TSRT Delay From Center of Start To Reset TXRDY# 8 8 Bclk TRST Reset Pulse Width Bclk Baud Clock 8 40 FIGURE 12. CLOCK TIMING CLK CLK EXTERNAL CLOCK OSC 32 24 8 40 ns 16X data rate Hz XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO REV. 1.0.3 FIGURE 13. MODEM INPUT/OUTPUT TIMING FOR CHANNELS A-D IO W # IO W A c t iv e TW RTS# DTR# C h a n g e o f s ta te DO C h a n g e o f s ta te CD# CTS# DSR# C h a n g e o f s ta te C h a n g e o f s ta te TMOD TMOD IN T A c t iv e A c t iv e A c t iv e T RSI IO R # A c t iv e A c t iv e A c t iv e TMOD C h a n g e o f s ta te R I# FIGURE 14. 16 MODE (INTEL) DATA BUS READ TIMING FOR CHANNELS A-D A0-A7 Valid Address TAS TCS Valid Address TAS TAH TAH TCS CS# TDY TRD TRD IOR# TDD TRDV D0-D7 Valid Data TDD TRDV Valid Data RDTm 33 XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO REV. 1.0.3 FIGURE 15. 16 MODE (INTEL) DATA BUS WRITE TIMING FOR CHANNELS A-D A0-A7 Valid Address Valid Address TAS TAS TAH TCS TAH TCS CS# TDY TWR TWR IOW# TDH TDS Valid Data D0-D7 TDH TDS Valid Data 16Write FIGURE 16. 68 MODE (MOTOROLA) DATA BUS READ TIMING FOR CHANNELS A-D A0-A7 Valid Address TADS TCSL Valid Address TADH CS# TCSD TRWS TRWH R/W# TRDH TRDA D0-D7 Valid Data Valid Data 68Read 34 XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO REV. 1.0.3 FIGURE 17. 68 MODE (MOTOROLA) DATA BUS WRITE TIMING FOR CHANNELS A-D A0-A7 Valid Address TADS TCSL Valid Address TADH CS# TCSD TRWS TRWH R/W# TWDS T WDH Valid Data D0-D7 Valid Data 68Write FIGURE 18. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A-D RX INT RXRDY# Start Bit D0:D7 Stop Bit D0:D7 D0:D7 TSSR TSSR TSSR 1 Byte in RHR 1 Byte in RHR 1 Byte in RHR TSSR TSSR Active Data Ready Active Data Ready TRR TRR TSSR Active Data Ready TRR IOR# (Reading data out of RHR) RXNFM 35 XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO REV. 1.0.3 FIGURE 19. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A-D TX Start Bit (Unloading) IER[1] enabled Stop Bit D0:D7 D0:D7 ISR is read D0:D7 ISR is read ISR is read INT* TWRI TWRI TWRI TSRT TSRT TSRT TXRDY# TWT TWT TWT IOW# (Loading data into THR) *INT is cleared when the ISR is read or when data is loaded into the THR. TXNonFIFO FIGURE 20. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A-D Start Bit RX S D0:D7 S D0:D7 T Stop Bit D0:D7 S D0:D7 T S D0:D7 T S D0:D7 T S D0:D7 T RX FIFO drops below RX Trigger Level TSSI INT FIFO Empties TSSR RX FIFO fills up to RX Trigger Level or RX Data Timeout RXRDY# First Byte is Received in RX FIFO TRRI TRR IOR# (Reading data out of RX FIFO) RXINTDMA# 36 XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO REV. 1.0.3 FIGURE 21. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A-D Start Bit RX Stop Bit S D0:D7 S D0:D7 T D0:D7 S D0:D7 T S D0:D7 T S D0:D7 T S D0:D7 T RX FIFO drops below RX Trigger Level TSSI INT RX FIFO fills up to RX Trigger Level or RX Data Timeout FIFO Empties TSSR RXRDY# TRRI TRR IOR# (Reading data out of RX FIFO) RXFIFODMA FIGURE 22. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A-D TX FIFO Empty TX Start Bit Stop Bit S D0:D7 T (Unloading) IER[1] enabled Last Data Byte Transmitted T S D0:D7 T S D0:D7 T S D0:D7 T S D0:D7 T TSI ISR is read ISR is read TSRT INT* TX FIFO fills up to trigger level TXRDY# Data in TX FIFO S D0:D7 T TX FIFO Empty TWRI TX FIFO drops below trigger level TWT IOW# (Loading data into FIFO) *INT is cleared when the ISR is read or when TX FIFO fills up to the trigger level. 37 TXDMA# XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO REV. 1.0.3 FIGURE 23. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A-D Start Bit TX Stop Bit Last Data Byte Transmitted S D0:D7 T S D0:D7 T (Unloading) IER[1] enabled D0:D7 S D0:D7 T ISR Read S D0:D7 T S D0:D7 T S D0:D7 T TSI TSRT ISR Read INT* TX FIFO fills up to trigger level TXRDY# TX FIFO drops below trigger level TWRI At least 1 empty location in FIFO TX FIFO Full TWT IOW# (Loading data into FIFO) *INT cleared when the ISR is read or when TX FIFO fills up to trigger level. 38 TXDMA XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO REV. 1.0.3 PACKAGE DIMENSIONS 48 LEAD QUAD FLAT NO LEAD (7 x 7 x 0.9 mm, 0.50 mm pitch QFN) Note: The actual center pad is metallic and the size (D2) is device-dependent with a typical tolerance of 0.3mm. The lead may be half-etched terminal. Note: The control dimension is the millimeter column INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.031 0.039 0.80 1.00 A1 0.000 0.002 0.00 0.05 A3 0.006 0.010 0.15 0.25 D 0.270 0.281 6.85 7.15 D2 0.201 0.209 5.10 5.30 b 0.007 0.012 0.18 0.30 e 0.0197 BSC 0.50 BSC L 0.012 0.020 0.30 0.50 k 0.008 - 0.20 - 39 XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO REV. 1.0.3 64 LEAD LOW-PROFILE QUAD FLAT PACK (10 x 10 x 1.4 mm LQFP) D D1 48 33 49 32 D1 D 17 64 1 16 B A2 e C A α Seating Plane A1 L Note: The control dimension is the millimeter column INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.055 0.063 1.40 1.60 A1 0.002 0.006 0.05 0.15 A2 0.053 0.057 1.35 1.45 B 0.007 0.011 0.17 0.27 C 0.004 0.008 0.09 0.20 D 0.465 0.480 11.80 12.20 D1 0.390 0.398 9.90 10.10 e 0.020 BSC 0.50 BSC L 0.018 0.030 0.45 0.75 α 0° 7° 0° 7° 40 XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO REV. 1.0.3 68 LEAD PLASTIC LEADED CHIP CARRIER (PLCC) D C Seating Plane D1 45° x H2 45° x H1 A2 2 1 68 B1 B D D3 D1 D2 e R D3 A1 A Note: The control dimension is the inch column INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.165 0.200 4.19 5.08 A1 0.090 0.130 2.29 3.30 A2 0.020 ---. 0.51 --- B 0.013 0.021 0.33 0.53 B1 0.026 0.032 0.66 0.81 C 0.008 0.013 0.19 0.32 D 0.985 0.995 25.02 25.27 D1 0.950 0.958 24.13 24.33 D2 0.890 0.930 22.61 23.62 D3 0.800 typ. 20.32 typ. e 0.050 BSC 1.27 BSC H1 0.042 0.056 1.07 1.42 H2 0.042 0.048 1.07 1.22 R 0.025 0.045 0.64 1.14 41 XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO REV. 1.0.3 80 LEAD PLASTIC QUAD FLAT PACK (12 mm x 12 mm LQFP, 1.4 mm Form) Note: The control dimension is the millimeter column INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.055 0.063 1.40 1.60 A1 0.002 0.006 0.05 0.15 A2 0.053 0.057 1.35 1.45 B 0.007 0.011 0.17 0.27 C 0.004 0.008 0.09 0.20 D 0.543 0.559 13.80 14.20 D1 0.465 0.480 11.80 12.20 e 0.0197 BSC 0.50 BSC L 0.018 0.030 0.45 0.75 α 0° 7° 0° 7° 42 XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO REV. 1.0.3 REVISION HISTORY DATE REVISION DESCRIPTION April 2006 Rev P1.0.0 Preliminary Data Sheet. July 2006 Rev P1.0.1 Updated AC Electrical Characterstics. October 2006 Rev P1.0.2 Updated DC Electrical Characteristics. January 2007 Rev 1.0.0 Final Datasheet. May 2007 Rev 1.0.1 Updated QFN package dimensions drawing to show minimum "k" parameter. September 2007 Rev 1.0.2 Changed 80-pin LQFP package pin out assignment. July 2010 Rev 1.0.3 Corrected 80-pin LQFP package pin number in pin description. NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2010 EXAR Corporation Datasheet July 2010. Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. 43