XR77103-G1R2
3-Output PMIC for MaxLinear G.hn Solutions
Data Sheet
August 30, 2022
Description
The XR77103-G1R2 universal PMIC features three 2A capable(1),
high-efficiency synchronous buck regulators with integrated power
switches. They can operate in 5V, 9V and 12V powered systems with
minimal required external components, thus providing the smallest
size solution possible.
The output voltages are pre-programmed to 1.1V, 1.5V, and 3.3V.
With a nominal switching frequency of 1.14MHz, the regulators can
also be synchronized to an external clock in applications where EMI
control is critical.
XR77103-G1R2 features a supervisor circuit that monitors each
converter output. The PGOOD pin is asserted once sequencing is
done, outputs are reported in regulation, and the reset timer expires.
The polarity of the signal is active high.
1. Subject to OCP setting.
FEATURES
■ 4.5V to 14V wide input supply voltage
range
■ Built-in MOSFET and synchronous rectifier
■ High accuracy 0.8V reference (1%)
■ Current-mode control with simple
compensation circuit
■ External synchronization
■ Power good
■ Protection
■ Thermal shutdown
■ Overvoltage transient protection
■ Overcurrent protection
■ 32-pin 4mm x 4mm TQFN package
APPLICATIONS
■ MaxLinear G.hn
Ordering Information - back page
269DSR00
1
Rev. 1B
XR77103-G1R2
Typical Application
VCC tied to VIN for 5VIN operation
28
VIN
4
Start-up
BGR
VIN = 4.5 to 14V
10
15
31
VIN
PGOOD
6
VCC
Internal
Supply
24
PGOOD
PGOOD
SYNC
OSC
VIN1
BST1
VIN2
LX1
VIN3
LX1
BUCK1
VOUT1
32
30
VOUT3 = 3.3V
29
1
2
BST3
COMP1
25
9
12
11
VOUT1 = 1.1V
8
7
LX3
BST2
LX3
BUCK3
LX2
VOUT3
LX2
BUCK2
COMP3
VOUT2
COMP2
XR77103-G1R2
EN
AGND DGND GND
26
27
19
5
16
14
13
VOUT2 = 1.5V
17
18
EP
Figure 1. Typical Application
2
Rev. 1B
XR77103-G1R2
Absolute Maximum Ratings
Operating Conditions
These are stress ratings only and functional operation
of the device at these ratings or any other above those
indicated in the operation sections of the specifications
below is not implied. Stresses beyond those listed under
absolute maximum ratings may cause permanent damage
to the device. Exposure to any absolute maximum rating
condition for extended periods may affect device reliability
and lifetime.
VIN......................................................................4.5V to 14V
VIN1, VIN2, VIN3, LX1, LX2, LX3........................ -0.3V to 18V
NOTE:
1. LX# pins’ DC range is from -0.3V, transient -1V for less than 10ns.
VCC....................................................................4.5V to 5.5V
LX#.................................................................-0.3V to 14V(1)
Junction temperature range (TJ).................. -40°C to 125°C
XR77103 package power dissipation max at 25°C...... 3.4W
XR77103 thermal resistance θJA.............................. 30°C/W
EN, VCC.............................................................. -0.3V to 7V
PGOOD, SYNC, VOUT#.................................... -0.3V to 7V
BST# to LX#....................................................... -0.3V to 7V
AGND, DGND to GND..................................... -0.3V to 0.3V
Storage temperature..................................... -65°C to 150°C
Junction temperature.................................................. 150°C
Power dissipation...................................... Internally Limited
Lead temperature (soldering, 10 seconds)................. 260°C
CDM............................................................................. 700V
ESD rating (HBM – human body model)........................ 2kV
Electrical Characteristics
TA = 25°C, VIN = 12V, EN = VCC, fSW = 1MHz, unless otherwise specified. Limits applying over the full operating temperature
range are denoted by a •.
Symbol
Parameter
Conditions
•
Min
•
•
Typ
Max
Units
5.5
14
V
4.5
5.5
V
Power Supply Characteristics
VIN
Input voltage range
VIN
Input voltage range
VCC tied to VIN
VUVLO
UVLO threshold
VIN rising/falling
UVLODEGLITCH
UVLO deglitch
IVIN
IVINQ
VIN supply current
4.22/4.1
V
Rising/falling
110
µs
EN = GND
250
µA
EN = high, no load
2.6
mA
Internal Supply Voltage
VCC
Internal biasing supply
ILOAD = 0mA
•
IVCC
Internal biasing supply current
VIN = 12V
•
VUVLO
UVLO threshold for VCC
UVLODEGLITCH
UVLO deglitch for VCC
4.9
5
5.1
V
10
mA
VCC rising
3.8
V
VCC falling
3.6
V
Falling edge
110
µs
3
Rev. 1B
XR77103-G1R2
Electrical Characteristics (Continued)
TA = 25°C, VIN = 12V, EN = VCC, fSW = 1MHz, unless otherwise specified. Limits applying over the full operating temperature
range are denoted by a •.
Symbol
Parameter
Conditions
•
TSD
Thermal shutdown temperature
HYTSD
Thermal shutdown hysteresis
Temperature rising, Non-latch off.
TSD release threshold,
temperature = TSD - HYTSD
TSD_DEGLITCH
Thermal shutdown deglitch
VOVBUCK
Threshold voltage for buck
overvoltage
Min
Typ
Max
Units
Protections
160
°C
20
°C
110
µs
Output rising
(HS FET will be forced off)
109
%
Output falling
(HS FET will be allowed to switch)
107
%
Buck Converter
fSW
Switching frequency
1.14
MHz
tSS
Soft-start period
0.83
ms
ILIMx
Peak inductor current limit
accuracy
Peak inductor current limit set at
2.5A for VOUT1, and 2A for VOUT2
and VOUT3
RON_HSx
HS switch on-resistance
VIN = 12V
200
mΩ
RON_LS1
LS switch on-resistance of Buck1
VIN = 12V
60
mΩ
RON_LS2/3
LS switch on-resistance of Buck2/3
VIN = 12V
80
mΩ
IOx
Output current capability
Continuous loading(1)
2
A
DMAX
Maximum duty cycle
95
%
tON MIN
Minimum on time
120
ns
VINX = 5.5V to 14V, IOX = 1A
0.5
%/V
VINX = 4.5V to 5.5V, IOX = 1A
0.5
%/V
IOX = 10% to 90% of IO(MAX)
0.5
%
Line regulation (ΔVOX/VOX)/ΔVINX
Load regulation (ΔVOX/VOX)
Output voltage accuracy
–30
+30
%
VIN = 12V
–1
Normal
1
%
VIN = 5V
–1
Normal
1
%
5.5V ≤ VIN ≤ 14V
•
–2
Normal
2
%
4.5V ≤ VIN ≤ 5.5V
•
–2
Normal
2
%
SYNCFREQ
Synchronization frequency
SYNCD_MIN
Synchronization signal
minimum duty cycle
•
SYNCD_MAX
Synchronization signal
maximum duty cycle
•
1.2
MHz
40
%
60
%
NOTE:
1. Subject to thermal derating and current limit setting. Design must not exceed the package thermal rating.
4
Rev. 1B
XR77103-G1R2
Electrical Characteristics (Continued)
TA = 25°C, VIN = 12V, EN = VCC, fSW = 1MHz, unless otherwise specified. Limits applying over the full operating temperature
range are denoted by a •.
Symbol
Parameter
Conditions
•
Min
Typ
Max
Units
Power Good Reset Generator
VUVBUCK
Threshold voltage for buck
under voltage
Output falling,
(disabled after tON_HICCUP)
85
Output rising, (PG will be asserted)
90
%
tPG_DEGLITCH
Deglitch time
Rising and falling
11
ms
tON_HICCUP
Hiccup mode on time
VUVBUCKX asserted
12
ms
tOFF_HICCUP
Hiccup mode off time
Once tOFF_HICCUP elapses,
all converters will start up again
15
ms
tRP
Minimum reset period
1
s
PGOOD output low
ISINK = 1mA
•
0.4
V
Input Threshold (SYNC, EN)
VIH
Input threshold high
VINPUT rising
•
VIL
Input threshold low
VINPUT falling
•
5
2.53
V
1.36
V
Rev. 1B
XR77103-G1R2
BST3
VIN3
LX3
LX3
VIN
AGND
EN
SYNC
Pin Configuration
32
31
30
29
28
27
26
25
VOUT3
1
24 PGOOD
COMP3
2
23 NC
NC
3
22 NC
VIN
4
21 NC
GND
5
20 NC
VCC
6
19 DGND
COMP1
7
18 COMP2
VOUT1
8
LX1
LX1
14
15
16
BST2
VIN1
13
VIN2
12
LX2
11
LX2
10
BST1
17 VOUT2
9
Figure 2. XR77103-G1R2 Pinout
Pin Functions
Pin Number
Pin Name
Description
1
VOUT3
Buck 3 feedback pin.
2
COMP3
Compensation pin for Buck 3. Connect a series RC circuit to this pin for compensation.
3
NC
No connect.
4
VIN
IC supply pin. Connect a capacitor as close as possible to this pin.
5
GND
Ground.
6
VCC
Internal supply. Connect a ceramic capacitor from this pin to ground.
7
COMP1
Compensation pin for Buck 1. Connect a series RC circuit to this pin for compensation.
8
VOUT1
Buck 1 feedback pin.
9
BST1
Bootstrap capacitor for Buck 1. Connect a bootstrap capacitor from this pin to LX1.
10
VIN1
Input supply for Buck 1. Connect a capacitor as close as possible to this pin.
11
LX1
Switching node for Buck 1.
12
LX1
Switching node for Buck 1.
13
LX2
Switching node for Buck 2.
14
LX2
Switching node for Buck 2.
15
VIN2
Input supply for Buck 2. Connect a capacitor as close as possible to this pin.
16
BST2
Bootstrap capacitor for Buck 2. Connect a bootstrap capacitor from this pin to LX2.
17
VOUT2
Buck 2 feedback pin.
18
COMP2
Compensation pin for Buck 2. Connect a series RC circuit to this pin for compensation.
19
DGND
20
NC
Digital ground.
No connect.
6
Rev. 1B
XR77103-G1R2
Pin Functions (Continued)
Pin Number
Pin Name
Description
21
NC
No connect.
22
NC
No connect.
23
NC
No connect.
24
PGOOD
25
SYNC
26
EN
27
AGND
28
VIN
IC supply pin. Connect a capacitor as close as possible to this pin.
29
LX3
Switching node for Buck 3.
30
LX3
Switching node for Buck 3.
31
VIN3
Input supply for Buck 3. Connect a capacitor as close as possible to this pin.
32
BST3
Bootstrap capacitor for Buck 3. Connect a bootstrap capacitor from this pin to LX3.
-
E-PAD
Connect to power ground.
Power good output. Open drain output asserted after all converters are sequenced and
within regulation.
External clock input pin. Connect to signal ground when unused.
Enable control input. Set EN high to enable converters.
Analog ground.
7
Rev. 1B
XR77103-G1R2
Typical Performance Characteristics
All data taken at fSW = 1.14MHz, TA = 25°C, no airflow, unless otherwise specified.
1.65
1.20
1.60
1.15
1.55
VOUT (V)
VOUT (V)
1.25
1.10
1.50
1.05
1.45
1.00
1.40
0.95
1.35
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0.0
0.1
0.2
0.3
IOUT (A)
Figure 3. Load Regulation Channel 1,
5VIN, 1.1VOUT
0.4
0.5
0.6
IOUT (A)
0.7
0.8
0.9
1.0
Figure 4. Load Regulation Channel 2,
5VIN, 1.5VOUT
3.6
ENABLE (5V / div)
VOUT (V)
3.5
3.4
Channel 1 (1V / div)
3.3
Channel 2 (1V / div)
3.2
3.1
3.0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
Channel 3 (3V / div)
1.0
(2ms / div)
IOUT (A)
Figure 5. Load Regulation Channel 3,
5VIN, 3.3VOUT
Figure 6. Power-up Sequence
8
Rev. 1B
XR77103-G1R2
Typical Performance Characteristics (Continued)
All data taken at fSW = 1.14MHz, TA = 25°C, no airflow, unless otherwise specified.
100
90
VOUT, AC Coupled, 20MHz
80
Efficiency (%)
(30mV / div)
(200mA / div)
IOUT
70
60
50
40
30
20
10
(100µs / div)
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0.8
0.9
1.0
0.9
1.0
IOUT (A)
Figure 7. 5VIN, 1.1VOUT
Transient Response, 0.5A to 1.0A
Figure 8. Efficiency Channel 1,
5VIN 1.1VOUT
100
90
VOUT, AC Coupled, 20MHz
80
Efficiency (%)
(50mV / div)
(200mA / div)
IOUT
70
60
50
40
30
20
10
(100µs / div)
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
IOUT (A)
Figure 10. Efficiency Channel 2,
5VIN 1.5VOUT
Figure 9. 5VIN, 1.5VOUT
Transient Response, 0.1A to 0.5A
100
90
VOUT, AC Coupled, 20MHz
80
IOUT
Efficiency (%)
(100mV / div)
(200mA / div)
70
60
50
40
30
20
10
(100µs / div)
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
IOUT (A)
Figure 11. 5VIN, 3.3VOUT
Transient Response, 0.1A to 0.5A
Figure 12. Efficiency Channel 3,
5VIN 3.3VOUT
9
Rev. 1B
XR77103-G1R2
Typical Performance Characteristics (Continued)
Thermal Characteristics
fSW = 1.14MHz, TA = 25°C, no airflow, only individual channel operating; inductor losses are included.
0.30
3.5
0.25
3
Power Loss (W)
Power Dissipation in Package (W)
4
2.5
2
1.5
1
D
0.15
0.10
0.05
0.5
0
0.20
0.00
0
0.0
10 20 30 40 50 60 70 80 90 100 110 120
0.1
0.2
0.3
0.4
TAMBIENT (°C)
Figure 13. Package Thermal Derating
0.6
0.7
0.8
0.9
1.0
Figure 14. Channel 1 Power Loss at
VIN = 5V, No Airflow
0.45
0.35
0.40
Power Loss (W)
0.30
Power Loss (W)
0.5
IOUT (A)
0.25
0.20
D
0.15
0.10
0.05
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
0.00
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
0.0
1.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
IOUT (A)
IOUT (A)
Figure 15. Channel 2 Power Loss at
VIN = 5V, No Airflow
Figure 16. Channel 3 Power Loss at
VIN = 5V, No Airflow
10
Rev. 1B
XR77103-G1R2
Functional Block Diagram
28
VIN
Start-up
BGR
4
VIN
6
VCC
Internal
Supply
24
PGOOD
PGOOD
SYNC
OSC
BST1
VIN1
10
VIN2
15
VIN3
31
LX1
LX1
BUCK1
VOUT1
32
30
29
1
2
COMP1
BST3
25
9
12
11
8
7
LX3
LX3
BST2
BUCK3
LX2
VOUT3
COMP3
LX2
BUCK2
VOUT2
COMP2
XR77103-G1R2
EN
AGND DGND GND
26
27
19
5
16
14
13
17
18
EP
Figure 17. Functional Block Diagram
11
Rev. 1B
XR77103-G1R2
Applications Information
Although the device can lock to an external clock running
up to 2.31MHz, doing this will alter the timing characteristics
and degrade thermal performance.
Operation
XR77103-G1R2 is a power management IC with three
step-down buck converters. Both high-side and low-side
MOSFETs are integrated to provide fully synchronous
conversion with higher efficiency. XR77103-G1R2 can
support a 4.5V to 14V input supply, high load current,
and 1.14MHz clocking. The SYNC pin also provides a
means to synchronize the power converter to an external
signal. Input ripple is reduced by operation 180 degrees
out-of-phase among converters. All three buck converters
have peak current mode control which simplifies external
frequency compensation. Buck converters 1, 2, and 3
have nominal peak inductor current limit of 2.5A, 2A, and
2A respectively. The device has a power good comparator
monitoring the output voltage. Soft-start for each converter
is 0.83ms. All outputs start up once the EN pin is set high.
Out-of-Phase Operation
Channels 1 and 3 operate in phase while channel 2 operates
180 degrees out-of-phase with the other two converters
(see Figure 28). This enables the system, having less
input ripple, to lower component cost, save board space,
and reduce EMI.
LX1
LX2
Minimum On-Time tON (min) Considerations
The XR77103 can regulate with pulse widths as low as
95ns. However, to ensure sufficent control range, the
design must use 120ns as the minimum on-time as stated
in the electrical table. Failure to meet this condition can
result in overcharging of the output and VOUT not meeting
specification.
LX3
Figure 18. Out-of-Phase Operation
Power Good
The PGOOD pin is an open drain output. The PGOOD
pin is pulled low when any buck converter is pulled below
85% of the nominal output voltage. The PGOOD is pulled
up when all three buck converters’ outputs are more than
90% of their nominal output voltage and the PGOOD reset
timer expires. The polarity of the PGOOD is active high.
The PGOOD reset time is 1s.
Output Voltage Setting
Output voltage is pre-programmed to VOUT1 = 1.1V,
VOUT2 = 1.5V, and VOUT3 = 3.3V.
Frequency Compensation
In order to properly frequency compensate the device,
the following component selection is recommended:
VIN
(V)
VOUT
(V)
L
(μH)
COUT
(µF)
RCOMP
(kΩ)
CCOMP
(nF)
5.0
1.0
1.5
22 x 3
20
2.2
5.0
1.2
1.5
22 x 3
20
2.2
5.0
1.5
1.5
22 x 2
20
4.7
12/5.0
1.8
1.5
22 x 2
20
4.7
12/5.0
2.5
3.3
22 x 1
20
4.7
12/5.0
3.3
3.3
22 x 1
20
4.7
12
5.0
3.3
22 x 1
20
4.7
Thermal Design
Proper thermal design is critical in controlling device
temperatures and in achieving robust designs. There are
a number of factors that affect the thermal performance.
One key factor is the temperature rise of the devices in
the package, which is a function of the thermal resistances
of the devices inside the package and the power
being dissipated.
The thermal resistance of the XR77103-G1R2 (30°C/W)
is specified in the Operating Conditions section of
this datasheet. The θJA thermal resistance specification is
based on the XR77103-G1R2 evaluation board operating
without forced airflow. Since the actual board design in the
final application will be different, the thermal resistances in
the final design may be different from those specified.
Synchronization
The status of the SYNC pin will be ignored during startup and the XR77103-G1R2’s control will only synchronize
to an external signal after the PGOOD signal is asserted.
When synchronization is applied, the sync pulse frequency
must be higher than the PWM oscillator frequency
(1.2MHz) to allow the external signal to trump the oscillator
pulse reliably. When synchronization is not applied, the
SYNC pin should be connected to the signal ground.
The package thermal derating and power loss curves are
shown in Figures 20 through 26. These correspond to input
voltages of 12V and 5V.
12
Rev. 1B
XR77103-G1R2
Applications Information (Continued)
Layout Guidelines
Proper PCB layout is crucial in order to obtain good thermal
and electrical performance.
For thermal considerations, it is essential to use a number
of thermal vias to connect the central thermal pad to the
ground layer(s).
In order to achieve good electrical and noise performance,
the following steps are recommended:
■ Place
the output inductor close to the LX pins and
minimize the area of the connection. Doing this
on the top layer is advisable.
■ Connect
the central thermal pad to the
power ground connections to as many layers
as possible.
■ The
output filtering capacitor and the input
filtering capacitor shall share the same power
ground connection. Connection to the signal
ground plane shall be done with vias placed at
the output filtering capacitors.
■ Minimize
AC current loops formed by input
filtering capacitors, output filtering capacitors,
output inductors, and the regulator pins.
■ Connect
the GND, AGND, DGND pins to the
signal ground plane.
■ Place
compensation networks close to the pins
and reference them to the signal ground.
■ Place
the pin.
the VCC bypass capacitor close to
13
Rev. 1B
XR77103-G1R2
Applications Information (Continued)
Typical Applications
VOUT3
VIN
LOUT_CH3
VIN
VIN3
COUT_CH3
C2_IN
CIN_CH3
EN
SYNC
C1_IN
CBST_CH3
RGND
VIN3
SYNC 25
NC
NC
4
VIN
NC
5
GND
6
VCC
7
COMP1
COMP2
VOUT1
VOUT2
NC
VIN1
PG
23
22
21
20
19
CP_CH2
18
17
CC_CH2
BST2
VIN2
DGND
24
16
LX2
15
LX2
VIN1
14
13
LX1
XR77103-G1R2
9
VOUT1
AGND 27
EN 26
3
BST1
CC_CH1
LX3 29
VIN 28
NC
8
RC_CH1
VIN3 31
LX3 30
COMP3
LX1
CP_CH1
PGOOD
12
CVCC
VOUT3
2
VIN1
VCC tied to VIN for 5VIN operation
VCC
VIN
RPG
1
11
CP_CH3
CC_CH3
10
RC_CH3
E-PAD 33
BST3 32
VOUT3
VCC
VOUT2
VIN2
VIN2
CIN_CH1
VOUT1
RC_CH2
CIN_CH2
CBST_CH1
CBST_CH2
LOUT_CH1
LOUT_CH2
VOUT2
COUT_CH2
COUT_CH1
Figure 19. Typical Applications Schematic
14
Rev. 1B
XR77103-G1R2
Mechanical Dimensions
TOP VIEW
BOTTOM VIEW
SIDE VIEW
TERMINAL DETAILS
Drawing No.: POD-00000079
Revision: C
15
Rev. 1B
XR77103-G1R2
Recommended Land Pattern and Stencil
TYPICAL RECOMMENDED LAND PATTERN
TYPICAL RECOMMENDED STENCIL
Drawing No.: POD-00000079
Revision: C
16
Rev. 1B
XR77103-G1R2
Order Information
Part Number
Operating Temperature Range
Lead-Free
Package
Packaging
Quantity
–40°C ≤ TJ ≤ 125°C
Yes
32-pin, 4mm x 4mm
TQFN package
Tape and Reel
XR77103ELBTR-G1R2
XR77103ELBTR-G1R2-EVK G.hn
XR77103-G1R2 evaluation board
NOTE: For more information about part numbers, as well as the most up-to-date ordering information and additional information on environmental rating, go to
www.maxlinear.com/XR77103-G1R2.
Revision History
Revision
Date
1A
10/15/19
Initial Release
8/30/22
Updated:
Throughout the document, “VFB1”, “VFB2”, and “VFB3” occurrences replaced with
“VOUT1”, “VOUT2”, and “VOUT3”, respectively.
In “Absolute Maximum Ratings” section, “PGOOD, SYNC” replaced with “PGOOD,
SYNC, VOUT#”.
In “Order Information” table, “XR77103EVB-G1R2” part number replaced with
“XR77103ELBTR-G1R2-EVK G.hn”.
1B
Description
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