XR81112TR-F

XR81112 Universal Clock - High Frequency LVCMOS/LVDS/LVPECL Clock Synthesizer General Description FEATURES The XR81112 is a family of Universal Clock synthesizer devices in a compact QFN-12 package. The devices generate ANY frequency in the range of 10 MHz to 1.5GHz by utilizing a highly flexible delta sigma modulator and a wide ranging VCO. The outputs are configurable for single ended LVCMOS or differential LVDS or LVPECL. The clock outputs have very low phase noise jitter of sub 0.6ps while consuming extremely low power. These devices can be used with standard crystals or an external system clock and can be configured to select from four different frequency multiplier settings to support a wide variety of applications. This family of products have an extremely low power PLL block with core power consumption less than 40% of equivalent devices in the market. • Small footprint 3mm x 3mm QFN package • Configurable - As one differential LVPECL/LVDS output pair or as a single ended LVCMOS output • Crystal oscillator interface which can also be overdriven using a single-ended reference clock • Output frequency range: 10MHz - 1500MHz • Crystal/input frequency: 10MHz to 60MHz, parallel resonant crystal • VCO range: 2GHz - 3GHz • RMS phase jitter @ 156.25MHz, 12KHz - 20MHz: 25MHz • 1.5 pS Output Rise/Fall Time 20% to 80%, see Figure 10 • 100 500 pS Output Duty Cycle see Figure 11 • 45 55 % * Limits applying over the full operating temperature range are denoted by a “•”. © 2014 Exar Corporation 4 / 12 exar.com/XR81112 Rev 1A XR81112 VCC Q Q Pin Configuration 12 11 10 9 VCC XTAL_OUT 2 8 VEE 3 7 OE 4 5 6 NC FSEL1 VEE 1 FSEL0 XTAL_IN Pin Assignments Pin No. Pin Name Type 1 XTAL_IN 2 XTAL_OUT 3 FSEL1 Input (900K: pull-dwn) Output frequency select pin, MSB (LVCMOS/LVTTL input). 4 FSEL0 Input (900K: pull-dwn) Output frequency select pin, LSB (LVCMOS/LVTTL input). 5 VEE Supply 6 NC No Connect 7 OE Input (900K: pull-up) 8 VEE Supply Negative supply pin. 9 VCC Supply Power supply pin. 10 Q Output Positive output. 11 Q Output Inverted output. 12 VCC Supply Power supply pin. © 2014 Exar Corporation Input Description Output Crystal oscillator input. Crystal oscillator output. Negative supply pin. Unused, do not connect. Output enable pin - LVCMOS/LVTTL active high input. Outputs are enabled when OE = high. Outputs are disabled when OE = low. 5 / 12 exar.com/XR81112 Rev 1A XR81112 Functional Block Diagram OE XTAL_IN OSC VCO PDF & LPF Divide by N Q Q XTAL_OUT Divide by M Control Logic FSEL0 Freq #1 FSEL1 Freq #3 Freq #4 © 2014 Exar Corporation Freq #2 6 / 12 exar.com/XR81112 Rev 1A XR81112 Typical Performance Characteristics Figures 1, 2, 3 and 4 show typical phase noise performance plots for 156.25 MHz, 150MHz, 125M, and 100MHz clock outputs respectively. The data was taken using the industry standard Agilent E5052B instrument. The integration range is the widely referenced 12KHz to 20MHz range most often used in WAN applications. Figure 1: 156.25MHz Operation, Phase Noise at 3.3V Figure 2: 150MHz Operation, Phase Noise at 3.3V) © 2014 Exar Corporation 7 / 12 exar.com/XR81112 Rev 1A XR81112 Figure 3: 125MHz Operation, Phase Noise at 3.3V Figure 4: 100MHz Operation, Phase Noise at 3.3V © 2014 Exar Corporation 8 / 12 exar.com/XR81112 Rev 1A XR81112 Application Information 2.5V 2.5V Functional Truth Table 2.5V : The XR81112 Universal Clock can support up to 4 individual output frequency configurations. Once configured, the two frequency select pins, FSLEL[1:0], will determine the output frequency from the device. This allows the XR81112 to support a variety of applications. If the FSEL pins are left floating, the XR81112 will default (with internal pull-down resistors on the FSEL inputs) to the Frequency #1 output. 50: LVPECL Output Output Frequency (MHz) 00 Frequency #1 01 Frequency #2 10 Frequency #3 11 LVPECL Input 50: : Table 1: Output Frequency Selection FSEL[1:0] VCC VCC 50: LVPECL Output LVPECL Input 50: 50: For 3.3V systems RTT = 50: For 2.5V systems RTT = 19: Termination for LVPECL Outputs The termination schemes shown in Figure 5 and Figure 6 are typical for LVPECL outputs. Matched impedance layout techniques should be used for the LVPECL output pairs to minimize any distortion that could impact your maximum operating frequency. Figure 7 is an alternate termination scheme that uses a Y-termination approach. 3.3V 130: 50: RTT Figure 7: XR81112 Alternate LVPECL Output Termination Using Y-termination Termination for LVDS Outputs The termination schemes shown in Figure 8 and Figure 9 are typical for LVDS outputs. LVDS swing is a small , typically 350mV, on 1.2V of common mode. The LVDS output pair needs a 100: resistor across the differential pair as close to the destination as possible. 3.3V 130: 50: LVPECL Output : Figure 6: XR81112 2.5V LVPECL Output Termination Frequency #4 3.3V : LVPECL Input 50: 82: 3.3V 82: 3.3V 50: LVDS Output 100: LVDS Input 50: Figure 5: XR81112 3.3V LVPECL Output Termination Figure 8: XR81112 3.3V LVDS Output Termination © 2014 Exar Corporation 9 / 12 exar.com/XR81112 Rev 1A XR81112 2.5V 2.5V 50: LVDS Output LVDS Input 100: 50: Figure 9: XR81112 2.5V LVDS Output Termination Output Signal Timing Definitions The following diagrams clarify the common definitions of the AC timing measurements. Q 80% 80% VSWING 20% 20% nQ tR tF Figure 10: Output Rise/Fall Time and Swing Q nQ t PW tPERIOD odc = tPW t PERIOD x 100% Figure 11: Output Period and Duty Cycle © 2014 Exar Corporation 10 / 12 exar.com/XR81112 Rev 1A XR81112 Mechanical Dimensions 12-Pin QFN T T © 2014 Exar Corporation 11 / 12 exar.com/XR81112 Rev 1A XR81112 Ordering Information Part Number Package Green Operating Temperature Range Shipping Packaging Marking XR81112-F 12-pin QFN Yes -40°C to +85°C Tube/Tray T112 XR81112EVB Eval Board N/A N/A N/A N/A Revision History Revision Date 1A June 2014 Description Initial release. [ECN1426-29_6/28/2014] For Further Assistance: Email: commtechsupport@exar.com Exar Technical Documentation: http://www.exar.com/techdoc/ Exar Corporation Headquarters and Sales Offices 48720 Kato Road Tel: +1 (510) 668-7000 Fremont, CA 95438 - USA Fax: +1 (510) 668-7001 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. © 2014 Exar Corporation 12 / 12 exar.com/XR81112 Rev 1A