XRA1207IG24TR-F

XRA1207 16-BIT I2C/SMBUS GPIO EXPANDER WITH INTEGRATED LEVEL SHIFTERS SEPTEMBER 2011 REV. 1.0.0 GENERAL DESCRIPTION The XRA1207 is a 16-bit GPIO expander with an I2C/ SMBus interface. After power-up, the XRA1207 has internal 100K ohm pull-up resistors on each I/O pin that can be individually enabled. • 1.65V to 3.6V operating voltage • Integrated Level Shifters • 16 General Purpose I/Os (GPIOs) • 5V tolerant inputs • Maximum stand-by current of 1uA at +1.8V • I2C/SMBus bus interface ■ I2C clock frequency up to 400kHz ■ Noise filter on SDA and SCL inputs ■ Up to 4 I2C Slave Addresses Th da e p an ta rod d sh uc m ee t ( ay t a or no re pr t b no od u e or lon cts de ge ) m re r b e d n (O eing tio BS m ne ) an d in uf th ac is tu re d In addition, the GPIOs on the XRA1207 can individually be controlled and configured. As outputs, the GPIOs can be outputs that are high, low or in three-state mode. The three-state mode feature is useful for applications where the power is removed from the remote devices, but they may still be connected to the GPIO expander. FEATURES As inputs, the internal pull-up resistors can be enabled or disabled and the input polarity can be inverted. The interrupt can be programmed for different behaviors. The interrupts can be programmed to generate an interrupt on the rising edge, falling edge or on both edges. The interrupt can be cleared if the input changes back to its original state or by reading the current state of the inputs. The XRA1207 is an enhanced version of the TCA6416. The XRA1207 is pin and software compatible with the TCA6416. The XRA1207 is available in 24-pin QFN and 24-pin TSSOP packages. • Individually programmable inputs ■ Internal pull-up resistors ■ Polarity inversion ■ Individual interrupt enable ■ Rising edge and/or Falling edge interrupt ■ Input filter • Individually programmable outputs ■ Output Level Control ■ Output Three-State Control • Open-drain active low interrupt output • Active-low reset input • Pin and software compatible with TCA6416 • 3kV HBM ESD protection per JESD22-A114F • 200mA latch-up performance per JESD78B APPLICATIONS • Personal Digital Assistants (PDA) • Cellular Phones/Data Devices • Battery-Operated Devices • Global Positioning System (GPS) • Bluetooth Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com XRA1207 16-BIT I2C/SMBUS GPIO EXPANDER WITH INTEGRATED LEVEL SHIFTERS REV. 1.0.0 FIGURE 1. XRA1207 BLOCK DIAGRAM VCCP (1 .6 5 V – 3 .6 V ) VCC (1 .6 5 V – 3 .6 V ) P0 P1 P2 P3 P4 P5 P6 P7 G P IO s SCL SDA I2C / SM Bus In te rfa c e RESET# IR Q # G P IO C o n tro l R e g is te rs In te g ra te d Level S h ifte rs Th da e p IRQ# VCCP an ta rod sh uc SDA d m ee t ( SCL ay t a or no re pr t b no od u e or lon cts de ge ) m re r b e d n (O eing tio BS m ne ) an d in uf th ac is tu re d A0 G P IO s GND P8 P9 P10 P11 P12 P13 P14 P15 ORDERING INFORMATION PART NUMBER XRA1207IL24-F XRA1207IL24TR-F XRA1207IG24-F XRA1207IG24TR-F PACKAGE NUMBER OF GPIOS OPERATING TEMPERATURE RANGE DEVICE STATUS QFN-24 16 -40°C to +85°C Active QFN-24 16 -40°C to +85°C Active TSSOP-24 16 -40°C to +85°C Active TSSOP-24 16 -40°C to +85°C Active NOTE: TR = Tape and Reel, F = Green / RoHS VCC RESET# FIGURE 2. PIN OUT ASSIGNMENTS 24 23 22 21 20 19 P0 1 P1 2 IRQ# 1 24 VCCP VCC 2 23 SDA RESET# 3 22 SCL P0 4 18 A0 17 P15 XRA1207 24-Pin QFN P2 3 P3 4 P4 5 P5 6 P1 5 P2 6 15 P13 14 P12 P3 7 13 P11 P4 8 17 P12 P5 9 16 P11 P6 10 15 P10 P7 11 14 P9 GND 12 13 P8 P9 P10 P8 20 P15 XRA1207 24-Pin TSSOP 16 P14 9 10 11 12 GND 8 P6 P7 7 21 A0 2 19 P14 18 P13 XRA1207 16-BIT I2C/SMBUS GPIO EXPANDER WITH INTEGRATED LEVEL SHIFTERS REV. 1.0.0 PIN DESCRIPTIONS Pin Description NAME QFN-24 TSSOP-24 TYPE PIN# PIN# DESCRIPTION I2C INTERFACE SDA 20 23 I/O SCL 19 22 I IRQ# 22 1 OD A0 18 21 I These pins select the I2C slave address. See Table 1. RESET# 24 3 I Reset (active LOW) - A longer than 40 ns LOW pulse on this pin will reset the internal registers and all GPIOs will be configured as inputs. 4 5 6 7 8 9 10 11 I/O I/O I/O I/O I/O I/O I/O I/O General purpose I/Os P0-P7. All GPIOs are configured as inputs upon powerup or after a reset. 13 14 15 16 17 18 19 20 I/O I/O I/O I/O I/O I/O I/O I/O General purpose I/O P8-P15. All GPIOs are configured as inputs upon powerup or after a reset. 24 Pwr 1.65V to 3.6V VCC supply voltage for GPIOs. 2 Pwr 1.65V to 3.6V VCC supply voltage for I2C-bus interface. P0 P1 P2 P3 P4 P5 P6 P7 1 2 3 4 5 6 7 8 P8 P9 P10 P11 P12 P13 P14 P15 10 11 12 13 14 15 16 17 I2C-bus serial input clock. Interrupt output (open-drain, active LOW). Th da e p an ta rod d sh uc m ee t ( ay t a or no re pr t b no od u e or lon cts de ge ) m re r b e d n (O eing tio BS m ne ) an d in uf th ac is tu re d GPIOs I2C-bus data input/output (open-drain). ANCILLARY SIGNALS VCCP 21 VCC 23 GND 9 12 Pwr Power supply common, ground. GND Center Pad - Pwr The exposed pad at the bottom surface of the package is designed for thermal performance. Use of a center pad on the PCB is strongly recommended for thermal conductivity as well as to provide mechanical stability of the package on the PCB. The center pad is recommended to be solder masked defined with opening size less than or equal to the exposed thermal pad on the package bottom to prevent solder bridging to the outer leads of the device. Thermal vias must be connected to GND plane as the thermal pad of package is at GND potential. Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain. 3 XRA1207 16-BIT I2C/SMBUS GPIO EXPANDER WITH INTEGRATED LEVEL SHIFTERS REV. 1.0.0 1.0 FUNCTIONAL DESCRIPTIONS 1.1 I2C-bus Interface The I2C-bus interface is compliant with the Standard-mode and Fast-mode I2C-bus specifications. The I2C-bus interface consists of two lines: serial data (SDA) and serial clock (SCL). In the Standard-mode, the serial clock and serial data can go up to 100 kbps and in the Fast-mode, the serial clock and serial data can go up to 400 kbps. Th da e p an ta rod d sh uc m ee t ( ay t a or no re pr t b no od u e or lon cts de ge ) m re r b e d n (O eing tio BS m ne ) an d in uf th ac is tu re d The first byte sent by an I2C-bus master contains a start bit (SDA transition from HIGH to LOW when SCL is HIGH), 7-bit slave address and whether it is a read or write transaction. The next byte is the sub-address that contains the address of the register to access. The XRA1207 responds to each write with an acknowledge (SDA driven LOW by XRA1207 for one clock cycle when SCL is HIGH). The last byte sent by an I2C-bus master contains a stop bit (SDA transition from LOW to HIGH when SCL is HIGH). See Figures 3 - 5 below. For complete details, see the I2C-bus specifications. FIGURE 3. I2C START AND STOP CONDITIONS SDA SCL S P STOP condition START condition FIGURE 4. MASTER WRITES TO SLAVE S SLAVE ADDRESS W A COMM AND BYTE A DATA BYTE A P W h ite b lo c k : h o s t to X R A 1 2 0 x G re y b lo c k : X R A 1 2 0 x to h o s t FIGURE 5. MASTER READS FROM SLAVE S SLAVE ADDRESS W A COMMAND BYTE A S SLAVE ADDRESS White block: host to XRA120x Grey block: XRA120x to host 4 R A nDATA A LAST DATA NA P XRA1207 REV. 1.0.0 1.1.1 16-BIT I2C/SMBUS GPIO EXPANDER WITH INTEGRATED LEVEL SHIFTERS I2C-bus Addressing There could be many devices on the I2C-bus. To distinguish itself from the other devices on the I2C-bus, the XRA1207 has up to 4 I2C slave addresses using the A0 address line. Table 1 below shows the different addresses that can be selected. TABLE 1: I2C ADDRESS MAP I2C ADDRESS GND 0x40 (0100 000X) VCC 0x42 (0100 001X) SCL 0x50 (0101 000X) SDA 0x52 (0101 001X) Th da e p an ta rod d sh uc m ee t ( ay t a or no re pr t b no od u e or lon cts de ge ) m re r b e d n (O eing tio BS m ne ) an d in uf th ac is tu re d 1.1.2 A0 I2C Read and Write A read or write transaction is determined by bit-0 of the slave address. If bit-0 is ’0’, then it is a write transaction. If bit-0 is ’1’, then it is a read transaction. 5 XRA1207 16-BIT I2C/SMBUS GPIO EXPANDER WITH INTEGRATED LEVEL SHIFTERS 1.1.3 REV. 1.0.0 I2C Command Byte An I2C command byte is sent by the I2C master following the slave address. The command byte indicates the address offset of the register that will be accessed. Table 2 below lists the command bytes for each register. TABLE 2: I2C COMMAND BYTE (REGISTER ADDRESS) COMMAND BYTE REGISTER NAME DESCRIPTION READ/WRITE DEFAULT VALUES GSR1 - GPIO State for P0-P7 Read-Only 0xXX 0x01 GSR2 - GPIO State for P8-P15 Read-Only 0xXX 0x02 OCR1 - Output Control for P0-P7 Read/Write 0xFF 0x03 OCR2 - Output Control for P8-P15 Read/Write 0xFF 0x04 PIR1 - Input Polarity Inversion for P0-P7 Read/Write 0x00 0x05 PIR2 - Input Polarity Inversion for P8-P15 Read/Write 0x00 0x06 GCR1 - GPIO Configuration for P0-P7 Read/Write 0xFF 0x07 GCR2 - GPIO Configuration for P8-P15 Read/Write 0xFF 0x08 PUR1 - Input Internal Pull-up Resistor Enable/Disable for P0-P7 Read/Write 0x00 0x09 PUR2 - Input Internal Pull-up Resistor Enable/Disable for P8-P15 Read/Write 0x00 0x0A IER1 - Input Interrupt Enable for P0-P7 Read/Write 0x00 0x0B IER2 - Input Interrupt Enable for P8-P15 Read/Write 0x00 0x0C TSCR1 - Output Three-State Control for P0-P7 Read/Write 0x00 0x0D TSCR2 - Output Three-State Control for P8-P15 Read/Write 0x00 0x0E ISR1 - Input Interrupt Status for P0-P7 Read 0x00 0x0F ISR2 - Input Interrupt Status for P8-P15 Read 0x00 0x10 REIR1 - Input Rising Edge Interrupt Enable for P0-P7 Read/Write 0x00 0x11 REIR2 - Input Rising Edge Interrupt Enable for P8-P15 Read/Write 0x00 0x12 FEIR1 - Input Falling Edge Interrupt Enable for P0-P7 Read/Write 0x00 0x13 FEIR2 - Input Falling Edge Interrupt Enable for P8-P15 Read/Write 0x00 0x14 IFR1 - Input Filter Enable/Disable for P0-P7 Read/Write 0xFF 0x15 IFR2 - Input Filter Enable/Disable for P8-P15 Read/Write 0xFF Th da e p an ta rod d sh uc m ee t ( ay t a or no re pr t b no od u e or lon cts de ge ) m re r b e d n (O eing tio BS m ne ) an d in uf th ac is tu re d 0x00 6 XRA1207 16-BIT I2C/SMBUS GPIO EXPANDER WITH INTEGRATED LEVEL SHIFTERS REV. 1.0.0 1.2 Interrupts The table below summarizes the interrupt behavior of the different register settings for the XRA1207. TABLE 3: INTERRUPT GENERATION AND CLEARING GCR IER REIR FEIR IFR BIT BIT BIT BIT BIT 1 1 1 0 1 1 1 X 0 1 0 1 1 1 0 x x X INTERRUPT CLEARED BY: X No interrupts enabled (default) N/A 0 A rising or falling edge on the input 1 A rising or falling edge on the input and remains in the new state for more than 1075ns Reading the GSR register or if the input changes back to its previous state (state of input during last read to GSR) 0 A rising edge on the input 1 A rising edge on the input and remains high for more than 1075ns 0 A falling edge on the input 1 A falling edge on the input and remains low for more than 1075ns 0 A rising or falling edge on the input 1 1 A rising or falling edge on the input and remains in the new state for more than 1075ns x x No interrupts in output mode 0 Reading the GSR register Th da e p an ta rod d sh uc m ee t ( ay t a or no re pr t b no od u e or lon cts de ge ) m re r b e d n (O eing tio BS m ne ) an d in uf th ac is tu re d 1 INTERRUPT GENERATED BY: 0 1 Reading the GSR register 7 Reading the GSR register N/A XRA1207 16-BIT I2C/SMBUS GPIO EXPANDER WITH INTEGRATED LEVEL SHIFTERS REV. 1.0.0 2.0 REGISTER DESCRIPTION 2.1 GPIO State Register 1 (GSR1) - Read-Only The status of P7 - P0 can be read via this register. A read will show the current state of these pins (or the inverted state of these pins if enabled via the PIR Register). Reading this register will clear an input interrupt (see Table 3 for complete details). Reading this register will also return the last value written to the OCR register for any pins that are configured as outputs (ie. this is not the same as the state of the actual output pin since the output pin can be in three-state mode). A write to this register has no effect. The MSB of this register corresponds with P7 and the LSB of this register corresponds with P0. 2.2 GPIO State Register 2 (GSR2) - Read-Only 2.3 Th da e p an ta rod d sh uc m ee t ( ay t a or no re pr t b no od u e or lon cts de ge ) m re r b e d n (O eing tio BS m ne ) an d in uf th ac is tu re d The status of P15 - P8 can be read via this register. A read will show the current state of these pins (or the inverted state of these pins if enabled via the PIR Register). Reading this register will clear an input interrupt (see Table 3 for complete details). Reading this register will also return the last value written to the OCR register for any pins that are configured as outputs (ie. this is not the same as the state of the actual output pin since the output pin can be in three-state mode). A write to this register has no effect. The MSB of this register corresponds with P15 and the LSB of this register corresponds with P8. Output Control Register 1 (OCR1) - Read/Write When P7 - P0 are defined as outputs, they can be controlled by writing to this register. Reading this register will return the last value written to it, however, this value may not be the actual state of the output pin since these pins can be in three-state mode. The MSB of this register corresponds with P7 and the LSB of this register corresponds with P0. 2.4 Output Control Register 2 (OCR2) - Read/Write When P15 - P8 are defined as outputs, they can be controlled by writing to this register. Reading this register will return the last value written to it, however, this value may not be the actual state of the output pin since these pins can be in three-state mode. The MSB of this register corresponds with P15 and the LSB of this register corresponds with P8. 2.5 Input Polarity Inversion Register 1 (PIR1) - Read/Write When P7 - P0 are defined as inputs, this register inverts the polarity of the input value read from the Input Port Register. If the corresponding bit in this register is set to ’1’, the value of this bit in the GSR Register will be the inverted value of the input pin. If the corresponding bit in this register is set to ’0’, the value of this bit in the GSR Register will be the actual value of the input pin. The MSB of this register corresponds with P7 and the LSB of this register corresponds with P0. 2.6 Input Polarity Inversion Register 2 (PIR2) - Read/Write When P15 - P8 are defined as inputs, this register inverts the polarity of the input value read from the Input Port Register. If the corresponding bit in this register is set to ’1’, the value of this bit in the GSR Register will be the inverted value of the input pin. If the corresponding bit in this register is set to ’0’, the value of this bit in the GSR Register will be the actual value of the input pin. The MSB of this register corresponds with P15 and the LSB of this register corresponds with P8. 2.7 GPIO Configuration Register 1 (GCR1) - Read/Write This register configures the GPIOs as inputs or outputs. After power-up and reset, the GPIOs are inputs. Setting these bits to ’0’ will enable the GPIOs as outputs. Setting these bits to ’1’ will enable the GPIOs as inputs. The MSB of this register corresponds with P7 and the LSB of this register corresponds with P0. 2.8 GPIO Configuration Register 2 (GCR2) - Read/Write This register configures the GPIOs as inputs or outputs. After power-up and reset, the GPIOs are inputs. Setting these bits to ’0’ will enable the GPIOs as outputs. Setting these bits to ’1’ will enable the GPIOs as inputs. The MSB of this register corresponds with P15 and the LSB of this register corresponds with P8. 8 XRA1207 REV. 1.0.0 2.9 16-BIT I2C/SMBUS GPIO EXPANDER WITH INTEGRATED LEVEL SHIFTERS Input Internal Pull-up Enable/Disable Register 1 (PUR1) - Read/Write This register enables/disables the internal pull-up resistors for an input. Writing a ’1’ to these bits will enable the internal pull-up resistors. Writing a ’0’ to these bits will disable the internal pull-up resistors. The MSB of this register corresponds with P7 and the LSB of this register corresponds with P0. 2.10 Input Internal Pull-up Enable/Disable Register 2 (PUR2) - Read/Write This register enables/disables the internal pull-up resistors for an input. Writing a ’1’ to these bits will enable the internal pull-up resistors. Writing a ’0’ to these bits will disable the internal pull-up resistors. The MSB of this register corresponds with P15 and the LSB of this register corresponds with P8. 2.11 Input Interrupt Enable Register 1 (IER1) - Read/Write 2.12 Th da e p an ta rod d sh uc m ee t ( ay t a or no re pr t b no od u e or lon cts de ge ) m re r b e d n (O eing tio BS m ne ) an d in uf th ac is tu re d This register enables/disables the interrupts for an input. After power-up and reset, the interrupts are disabled. Writing a ’1’ to these bits will enable the interrupt for the corresponding input pins. See Table 3 for complete details of the interrupt behavior for various register settings. No interrupts are generated for outputs when GCR bit is 0. The MSB of this register corresponds with P7 and the LSB of this register corresponds with P0. Input Interrupt Enable Register 2 (IER2) - Read/Write This register enables/disables the interrupts for an input. After power-up and reset, the interrupts are disabled. Writing a ’1’ to these bits will enable the interrupt for the corresponding input pins. See Table 3 for complete details of the interrupt behavior for various register settings. No interrupts are generated for outputs when GCR bit is 0. The MSB of this register corresponds with P15 and the LSB of this register corresponds with P8. 2.13 Output Three-State Control Register 1 (TSCR1) - Read/Write This register can enable/disable the three-state mode of an output. Writing a ’1’ to these bits will enable the three-state mode for the corresponding output pins. The MSB of this register corresponds with P7 and the LSB of this register corresponds with P0. 2.14 Output Three-State Control Register 2 (TSCR2) - Read/Write This register can enable/disable the three-state mode of an output. Writing a ’1’ to these bits will enable the three-state mode for the corresponding output pins. The MSB of this register corresponds with P15 and the LSB of this register corresponds with P8. 2.15 Input Interrupt Status Register 1 (ISR1) - Read-Only This register reports the input pins that have generated an interrupt. See Table 3 for complete details of the interrupt behavior for various register settings. The MSB of this register corresponds with P7 and the LSB of this register corresponds with P0. 2.16 Input Interrupt Status Register 2 (ISR2) - Read-Only This register reports the input pins that have generated an interrupt. See Table 3 for complete details of the interrupt behavior for various register settings. The MSB of this register corresponds with P15 and the LSB of this register corresponds with P8. 9 XRA1207 16-BIT I2C/SMBUS GPIO EXPANDER WITH INTEGRATED LEVEL SHIFTERS 2.17 REV. 1.0.0 Input Rising Edge Interrupt Enable Register 1 (REIR1) - Read/Write Writing a ’1’ to these bits will enable the corresponding input to generate an interrupt on the rising edge. See Table 3 for complete details of the interrupt behavior for various register settings. The MSB of this register corresponds with P7 and the LSB of this register corresponds with P0. 2.18 Input Rising Edge Interrupt Enable Register 2 (REIR2) - Read/Write Writing a ’1’ to these bits will enable the corresponding input to generate an interrupt on the rising edge. See Table 3 for complete details of the interrupt behavior for various register settings. The MSB of this register corresponds with P15 and the LSB of this register corresponds with P8. 2.19 Input Falling Edge Interrupt Enable Register 1 (FEIR1) - Read/Write 2.20 Th da e p an ta rod d sh uc m ee t ( ay t a or no re pr t b no od u e or lon cts de ge ) m re r b e d n (O eing tio BS m ne ) an d in uf th ac is tu re d Writing a ’1’ to these bits will enable the corresponding input to generate an interrupt on the falling edge. Writing a ’1’ to these bits will make that input generate an interrupt on the rising edge only. See Table 3 for complete details of the interrupt behavior for various register settings. The MSB of this register corresponds with P7 and the LSB of this register corresponds with P0. Input Falling Edge Interrupt Enable Register 2 (FEIR2) - Read/Write Writing a ’1’ to these bits will enable the corresponding input to generate an interrupt on the falling edge. Writing a ’1’ to these bits will make that input generate an interrupt on the rising edge only. See Table 3 for complete details of the interrupt behavior for various register settings. The MSB of this register corresponds with P15 and the LSB of this register corresponds with P8. 2.21 Input Filter Enable Register 1 (IFR1) - Read/Write By default, the input filters are enabled (IFR = 0xFF). When the input filters are enabled, any pulse that is greater than 1075ns will generate an interrupt (if enabled). Pulses that are less than 225ns will be filtered and will not generate an interrupt. Pulses in between this range may or may not generate an interrupt. Writing a ’0’ to these bits will disable the input filter for the corresponding inputs. With the input filters disabled, any change on the inputs will generate an interrupt (if enabled). See Table 3 for complete details of the interrupt behavior for various register settings. The MSB of this register corresponds with P7 and the LSB of this register corresponds with P0. 2.22 Input Filter Enable Register 2 (IFR2) - Read/Write By default, the input filters are enabled (IFR = 0xFF). When the input filters are enabled, any pulse that is greater than 1075ns will generate an interrupt (if enabled). Pulses that are less than 225ns will be filtered and will not generate an interrupt. Pulses in between this range may or may not generate an interrupt. Writing a ’0’ to these bits will disable the input filter for the corresponding inputs. With the input filters disabled, any change on the inputs will generate an interrupt (if enabled). See Table 3 for complete details of the interrupt behavior for various register settings. The MSB of this register corresponds with P15 and the LSB of this register corresponds with P8. 10 XRA1207 16-BIT I2C/SMBUS GPIO EXPANDER WITH INTEGRATED LEVEL SHIFTERS REV. 1.0.0 ABSOLUTE MAXIMUM RATINGS Power supply voltage 3.6 Volts Supply current 160 mA Ground current 200 mA External current limit of each GPIO 25 mA Total current limit for GPIO[15:8] and GPIO[7:0] 100 mA Total current limit for GPIO[15:0] 200 mA Total supply current sourced by all GPIOs 160 mA -40o to +85oC Storage Temperature -65o to +150oC Power Dissipation Th da e p an ta rod d sh uc m ee t ( ay t a or no re pr t b no od u e or lon cts de ge ) m re r b e d n (O eing tio BS m ne ) an d in uf th ac is tu re d Operating Temperature 200 mW TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%) Thermal Resistance (24-QFN) theta-ja = 38oC/W, theta-jc = 26oC/W Thermal Resistance (24-TSSOP) theta-ja = 84oC/W, theta-jc = 16oC/W 11 XRA1207 16-BIT I2C/SMBUS GPIO EXPANDER WITH INTEGRATED LEVEL SHIFTERS REV. 1.0.0 ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS UNLESS OTHERWISE NOTED: TA = -40O TO +85OC, VCC IS 1.65V TO 3.6V SYMBOL LIMITS LIMITS LIMITS 1.8V ± 10% 2.5V ± 10% 3.3V ± 10% MIN MAX MIN MAX MIN MAX PARAMETER UNITS CONDITIONS Input Low Voltage -0.3 0.3VCC -0.3 0.3VCC -0.3 0.3VCC V Note 1 VIL Input Low Voltage -0.3 0.2 -0.3 0.5 -0.3 0.8 V Note 2 VIH Input High Voltage 1.3 VCC 1.8 VCC 2.3 VCC V Note 1 VIH Input High Voltage 1.4 5.5 1.8 5.5 2.0 5.5 V Note 2 VOL Output Low Voltage 0.4 V V V IOL = 3 mA Th da e p an ta rod d sh uc m ee t ( ay t a or no re pr t b no od u e or lon cts de ge ) m re r b e d n (O eing tio BS m ne ) an d in uf th ac is tu re d VIL 0.4 0.4 VOL VOL Output Low Voltage 0.5 0.5 0.5 Output Low Voltage 0.4 0.4 0.4 VOH Output High Voltage 2.6 1.8 1.2 IOL = 3 mA IOL = 3 mA Note 3 V IOL = 8 mA Note 4 V V V IOL = 6 mA IOL = 4 mA IOL = 1.5 mA Note 5 V V V IOH = -8 mA IOH = -8 mA IOH = -8 mA Note 4 IIL Input Low Leakage Current ±10 ±10 ±10 uA IIH Input High Leakage Current ±10 ±10 ±10 uA CIN Input Pin Capacitance 5 5 5 pF ICC Power Supply Current 50 100 200 uA Test 1 ICC Power Supply Current 150 250 500 uA Test 2 ICCS Standby Current 1 2 5 uA Test 3 RGPIO GPIO pull-up resistance RRESET# Reset# pull-up resistance 60 140 60 140 60 140 kΩ 100kΩ ± 40% 35 85 35 85 35 85 kΩ 60kΩ ± 40% NOTE: The Vcc comes from VCCP pin for the GPIOs and the VCC pin for the other signals; NOTES: 1. For I2C input signals (SDA, SCL); 2. For GPIOs, A0, A1 and A2 signals; 3. For I2C output signal SDA; 4. For GPIOs; 12 XRA1207 16-BIT I2C/SMBUS GPIO EXPANDER WITH INTEGRATED LEVEL SHIFTERS REV. 1.0.0 5. For IRQ# signal; Test 1: SCL frequency is 400 KHz with internal pull-ups disabled. All GPIOs are configured as inputs. All inputs are steady at VCC or GND. Outputs are floating or in the tri-state mode. Test 2: SCL frequency is 400 KHz with internal pull-ups enabled. All GPIOs are configured as inputs. All inputs are steady at VCC or GND. Outputs are floating or in the tri-state mode. Test 3: All inputs are steady at VCC or GND to minimize standby current. If internal pull-up is enabled, input voltage level should be the same as VCC. All GPIOs are configured as inputs. SCL and SDA are at VCC. Outputs are left floating or in tri-state mode. AC ELECTRICAL CHARACTERISTICS SYMBOL Th da e p an ta rod d sh uc m ee t ( ay t a or no re pr t b no od u e or lon cts de ge ) m re r b e d n (O eing tio BS m ne ) an d in uf th ac is tu re d Unless otherwise noted: TA=-40o to +85oC, Vcc=1.65V - 3.6V STANDARD MODE I2C-BUS MIN MAX PARAMETER 0 100 FAST MODE I2C-BUS MIN MAX fSCL Operating frequency TBUF Bus free time between STOP and START 4.7 1.3 µs THD;STA START condition hold time 4.0 0.6 µs TSU;STA START condition setup time 4.7 0.6 µs THD;DAT Data hold time 0 0 ns TVD;ACK Data valid acknowledge 0.6 0.6 µs TVD;DAT SCL LOW to data out valid 0.6 0.6 ns TSU;DAT Data setup time 250 150 ns TLOW Clock LOW period 4.7 1.3 µs THIGH Clock HIGH period 4.0 0.6 µs TF Clock/data fall time 300 300 ns TR Clock/data rise time 1000 300 ns TSP Pulse width of spikes tolerance TD1 I2C-bus GPIO output valid 0.2 0.2 µs TD4 I2C input pin interrupt valid 4 4 µs TD5 I2C input pin interrupt clear 4 4 µs TD15 SCL delay after reset 50 3 13 0 400 UNIT 50 3 kHz ns µs XRA1207 16-BIT I2C/SMBUS GPIO EXPANDER WITH INTEGRATED LEVEL SHIFTERS REV. 1.0.0 FIGURE 6. I2C-BUS TIMING DIAGRAM START condition (S) Protocol Bit 7 MSB (A7) T SU;STA T LOW Bit 0 LSB (R/W) Bit 6 (A6) T HIGH Acknowledge (A) STOP condition (P) 1/F SCL SCL T SP Th da e p an ta rod d sh uc m ee t ( ay t a or no re pr t b no od u e or lon cts de ge ) m re r b e d n (O eing tio BS m ne ) an d in uf th ac is tu re d T BUF SDA TF TR T HD;STA T SU;DAT T HD;DAT T VD;DAT T VD;ACK T SU;STO FIGURE 7. WRITE TO OUTPUT SDA GPIOn SLAVE ADDRESS W A COMMAND BYTE A DATA A T D1 FIGURE 8. GPIO PIN INTERRUPT A C K from slave SDA SLAVE ADDRESS W A COMMAND BYTE A A C K from slave S S LA V E ADDRESS R A A C K from m aste r DATA IN T # TD4 TD5 Px 14 A P XRA1207 16-BIT I2C/SMBUS GPIO EXPANDER WITH INTEGRATED LEVEL SHIFTERS REV. 1.0.0 Th da e p an ta rod d sh uc m ee t ( ay t a or no re pr t b no od u e or lon cts de ge ) m re r b e d n (O eing tio BS m ne ) an d in uf th ac is tu re d PACKAGE DIMENSIONS (24 PIN QFN - 4 X 4 X 0.9 mm) θ Note: the actual center pad is metallic and the size (D2) is device-dependent with a typical tolerance of 0.3mm Note: The control dimension is in millimeter. INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A - 0.039 - 1.00 A1 0.000 0.002 0.00 0.05 A3 0.006 0.010 0.15 0.25 θ 0 14o 0 14o D 0.154 0.161 3.90 4.10 D2 0.087 0.102 2.20 2.60 b 0.007 0.012 0.18 0.30 e 0.020 BSC 0.50 BSC L 0.012 0.020 0.30 0.50 k 0.008 - 0.20 - 15 XRA1207 16-BIT I2C/SMBUS GPIO EXPANDER WITH INTEGRATED LEVEL SHIFTERS Th da e p an ta rod d sh uc m ee t ( ay t a or no re pr t b no od u e or lon cts de ge ) m re r b e d n (O eing tio BS m ne ) an d in uf th ac is tu re d PACKAGE DIMENSIONS (24 PIN TSSOP - 4.4 mm) Note: The control dimension is in millimeter. INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.031 0.047 0.80 1.20 A1 0.002 0.006 0.05 0.15 A2 0.031 0.041 0.80 1.05 b 0.007 0.012 0.19 0.30 C 0.004 0.008 0.09 0.2 D 0.303 0.311 7.70 7.90 E 0.240 0.264 6.10 6.70 E1 0.169 0.177 4.30 4.50 e 0.0256 BSC 0.65 BSC L 0.018 0.030 0.45 0.75 α 0° 8° 0° 8° 16 REV. 1.0.0 XRA1207 16-BIT I2C/SMBUS GPIO EXPANDER WITH INTEGRATED LEVEL SHIFTERS REV. 1.0.0 REVISION HISTORY REVISION September 2011 1.0.0 DESCRIPTION Final Datasheet. Th da e p an ta rod d sh uc m ee t ( ay t a or no re pr t b no od u e or lon cts de ge ) m re r b e d n (O eing tio BS m ne ) an d in uf th ac is tu re d DATE NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2011 EXAR Corporation Datasheet September 2011. Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. 17