XRP2997IDBTR-F

XRP2997 2A DDRI/II/III/IV Bus Termination Regulator August 2017 Rev. 1.2.1 GENERAL DESCRIPTION APPLICATIONS • DDR I/II/III/IV Memory Termination The XRP2997 is a Double Data Rate (DDR) termination voltage regulator supporting all power requirements of DDR I, II, III and IV memories and is capable of sinking or sourcing 2A continuously. Tightly regulating its output voltage within ±20mV, the XRP2997 converts input voltages as low as 1.1V while the output voltage is adjustable through an external resistor divider or by forcing the VREF pin voltage. It maintains a fast line and load transient response and only requires an output capacitance of 22µF to operate. An enable function via an external MOSFET and a soft start feature allow for a controlled implementation of power-up sequencing. • Active Termination Buses • Audio-Video Equipments • Video-Graphics Cards FEATURES • DDR1, DDR2, DDR3 and DDR4 Support − 0.75VTT Generation − ±20mV Output Voltage Offset • 2 Amps Continuous Current Sourcing & Sinking − 1.1V to 5.5V Wide Input Voltage Range • Adjustable Output Voltage Built-in source/sink overcurrent, overtemperature and under-voltage lockout protections insure safe operation under abnormal operating conditions. • Suspend to RAM(STR), Enable & Soft Start Functions • Stable with 22µF Ceramic Capacitor The XRP2997 meets JEDEC SSTL-2, SSTL-18, HSTL, SCSI-1 and SCSI-3 specifications for DDR SDRAM memories. • UVLO, Over Temperature and Over Current Protections The XRP2997 is offered in a RoHS compliant, “green”/halogen free 8-pin Exposed Pad SOIC package. • Pin/Function Compatible with SP2996B • Minimal External Components • RoHS Compliant “Green”/Halogen Free 8-Pin SOIC Package TYPICAL APPLICATION DIAGRAM Fig. 1: XRP2997 DDRIII VTT Application Diagram 1/9 Rev. 1.2.1 XRP2997 2A DDRI/II/III/IV Bus Termination Regulator ABSOLUTE MAXIMUM RATINGS OPERATING RATINGS These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. Operating Temperature Range ................. -40°C to +85°C Thermal Resistance θJA ...................................... 60°C/W Thermal Resistance θJC ...................................... 16°C/W VIN, VREF, VCNTL .......................................... -0.3V to 6.0V Junction Temperature Range.................. -40°C to +150°C Storage Temperature ............................ -65°C to +150°C Lead Temperature (Soldering, 10 sec) ................... 260°C ELECTRICAL SPECIFICATIONS Specifications are for an Operating Ambient Temperature of TA = 25°C only; limits applying over the full Operating Junction Temperature range are denoted by a “•”. Minimum and Maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TA = 25°C, and are provided for reference purposes only. Unless otherwise indicated, VIN = 1.8V/1.5V, VCNTL = 3.3V, VREF = 0.5xVIN, COUT = 22µF (ceramic), TA= 25°C. Parameter VIN, Input Voltage Range VCNTL, Input Voltage Range Min. ∆VLOR, Load Regulation Max. Units Conditions 1.1 1.8/1.5 5.5 V Keep VCNTL≥VIN during power on and power off sequences (note 4) 2.375 3.3 5.5 V Keep VCNTL≥VIN during power on and power off sequences (note 4) V IOUT = 0mA -20 +20 mV IOUT = 0mA (note 1) -20 +20 mV IOUT = 0.1mA to +2A -20 +20 mV IOUT = 0.1mA to -2A VOUT, Output Voltage VOS, Output Voltage Offset Typ. VREF IQ, Quiescent Current 2 90 µA VREF < 0.2V, VOUT = OFF ICNTL, Operating Current of VCNTL 1 2.5 mA IOUT = 0mA 1 µA VREF = 1.25V IREF, Bias Current of VREF IIL, Current Limit 0 2.4 RDSCHG, Output Discharge Resistance A Source: VOUT=0.33xVREF Sink: VOUT=0.95xVIN (note 3) Ω VREF=0V, VOUT=0.3V 160 °C 3.3V ≤ VCNTL ≤ 5V, guaranteed by design (note 4) 30 °C Guaranteed by design 3 18 25 Thermal Protection TSD, Thermal Shutdown Temperature Thermal Shutdown Hysteresis Shutdown Specifications VTRIGGER, Shutdown Threshold 0.6 V 0.2 Note Note Note Note 1: 2: 3: 4: Output ON VREF = 0V  1.25V Output OFF VREF = 1.25V  0V VOS offset is the voltage measurement defined as VOUT subtracted from VREF. Load regulation is measured at constant junction temperature, using pulse testing with a short ON time. Current limit is measured by applying a short duration current pulse. In order to safely operate yo2ur system, VCNTL must be > VIN. 2/9 Rev. 1.2.1 XRP2997 2A DDRI/II/III/IV Bus Termination Regulator BLOCK DIAGRAM Fig. 2: XRP2997 Block Diagram PIN ASSIGNMENT Fig. 3: XRP2997 Pin Assignment PIN DESCRIPTION Name Pin Number VIN 1 2 Exposed Pad GND Description Power Input Voltage Ground Signal 3 Reference Input Voltage. This input can also be used as an enable signal; pulling this pin low shuts down the XRP2997. Refer to typical application circuit. VOUT 4 Output Voltage NC 5, 7, 8 VCNTL 6 VREF NC Voltage for the driver circuit and all analog blocks ORDERING INFORMATION(1) Part Number XRP2997IDBTR-F Operating Temperature Range Lead-Free -40°C≤TA≤+85°C Yes (2) Package Packing Method Exposed pad HSOIC-8 Option 1 Tape & Reel NOTE: 1. Refer to www.exar.com/XRP2997 for most up-to-date Ordering Information 2. Visit www.exar.com for additional information on Environmental Rating. 3/9 Rev. 1.2.1 XRP2997 2A DDRI/II/III/IV Bus Termination Regulator TYPICAL PERFORMANCE CHARACTERISTICS All data taken at VIN = 1.8V/1.5V, VCNTL = 3.3V, VREF = 0.5xVIN, COUT = 22µF (ceramic), TA= 25°C, unless otherwise specified - Schematic and BOM from Application Information section of this datasheet. Fig. 4: Turn on and turn off vs. Temperature Fig. 5: Output Voltage vs. Temperature Fig. 6: Current limit (sourcing) vs. Temperature Fig. 7: Current limit (sinking) vs. Temperature 4/9 Rev. 1.2.1 XRP2997 2A DDRI/II/III/IV Bus Termination Regulator Fig. 8: VIN=1.5V, VREF=0.75V source response Fig. 9: VIN=1.8V, VREF=0.9V source response Fig. 10: VIN=2.5V, VREF=1.25V source response Fig. 11: VIN=1.5V, VREF=0.75V sink response Fig. 9: VIN=1.8V, VREF=0.9V sink response Fig. 10: VIN=2.5V, VREF=1.25V sink response 5/9 Rev. 1.2.1 XRP2997 2A DDRI/II/III/IV Bus Termination Regulator Fig. 14: VIN=1.5V, VREF=0.75V source short circuit Fig. 15: VIN=1.8V, VREF=0.9V source short circuit Fig. 11: VIN=2.5V, VREF=1.25V source short circuit Fig. 12: VIN=1.5V, VREF=0.75V sink short circuit Fig. 13: VIN=1.8V, VREF=0.9V sink short circuit Fig. 14: VIN=2.5V, VREF=1.25V sink short circuit 6/9 Rev. 1.2.1 XRP2997 2A DDRI/II/III/IV Bus Termination Regulator APPLICATION INFORMATION recommended value of 47µF is recommended for optimum transient response performance. INPUT CAPACITOR CIN LAYOUT CONSIDERATIONS Select the input capacitor CIN for voltage rating, RMS current rating and capacitance. The voltage rating should be at least 50% higher than the regulator’s maximum input voltage. The value of this capacitor, its charge, should be selected in order to be able to supply enough current to the XRP2997 in the event of a transient increase of source current required. A minimum value of 10µF is advised while a The XRP2997 is offered in the 8-pin exposedpad SOIC package in order to facilitate power dissipation (heat dissipation). Power dissipation can be maximized by soldering the exposed pad to a large land area on top layer of PCB and by using vias to connect the exposed pad to an interlayer(s) or bottom layer. All capacitors should be placed as close as possible to the respective pins. 7/9 Rev. 1.2.1 XRP2997 2A DDRI/II/III/IV Bus Termination Regulator PACKAGE SPECIFICATION 8-PIN HSOIC (EXPOSED PAD) OPTION 1 XRP2997_DS_081717 8/9 Rev. 1.2.1 XRP2997 2A DDRI/II/III/IV Bus Termination Regulator REVISION HISTORY Revision Date Description 1.0.0 07/22/2011 Initial release of datasheet 1.1.0 01/09/2012 Corrected part number in ordering information 1.1.1 03/29/2012 Corrected turn on threshold from 0.8V to 0.6V. Typographical error. 1.2.0 10/29/2012 Reformat of datasheet Updated typical application schematics (figure 1) Addition of CIN selection under Application Information section 1.2.1 8/17/2017 Added DDR IV. Updated to MaxLinear logo. Updated format, ordering information and package drawing. FOR FURTHER ASSISTANCE Email: mailto:customersupport@exar.com mailto:powertechsupport@exar.com Corporate Headquarters: 5966 La Place Court Suite 100 Carlsbad, CA 92008 Tel.:+1 (760) 692 0711 Fax: +1 (760)444-8598 www.maxlinear.com High Performance Analog: 48720 Kato Road Fremont, CA 94538 – USA Tel.: +1 (510) 668-7000 Fax: +1 (510) 668-7030 www.exar.com The content of this document is furnished for informational use only, is subject to change without notice, and should not be construed as a commitment by MaxLinear, Inc.. MaxLinear, Inc. assumes no responsibility or liability for any errors or inaccuracies that may appear in the informational content contained in this guide. Complying with all applicable copyright laws is the responsibility of the user. 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