XRP6272IDBTR-F

XRP6272 2A 5V-Adjustable Low Dropout Voltage Regulator Se pte mber 10, 2021 R e v. 1.2.2 GENERAL DESCRIPTION APPLICATIONS • Networking Equipments The XRP6272 is a low dropout voltage regulator capable of a constant output current up to 2 Amps. A wide 1.8V to 6V input voltage range allows for single supply operations f rom industry standard 1.8V, 2.8V, 3.3V, and 5V power rails as well as the 5.8V rail. • RF Circuitry Power Supplies • Set-top box Equipments • Portable Equipments With better than ±2% output voltage accuracy, low output noise and high Power Supply Rejection Ratio (PSRR), the XRP6272 is perfectly suited for powering RF circuitries. Optimized for use with small low cost ESR ceramic output capacitors and featuring a low 30µA quiescent current, this device is also adequate for use in battery powered port able equipments. The XRP6272 operates by default as a 5V fixed output voltage regulator while usage of an external resistors divider allows adjustable out voltages as low as 0.7V. An Enable function, Power Good flag and out put noise reduction pin complete the feature set. FEATURES • Guaranteed 2A Output Current − Low 550mV Dropout at 3.3V/2A • 1.8V to 6V Single Input Voltage Range − Fixed 5V and Adjustable Output Voltage − ±2% Output Voltage Accuracy • 30µA Quiescent Current • Power Good and Enable Functions • 70dB Power Supply Rejection Ratio • Low Output Noise Built-in current limit and thermal protections insure safe operations under abnormal operating conditions. • 0.01µA Shutdown Current The XRP6272 is offered in RoHS compliant, “green”/halogen free 5-pin TO-252 and 8- pin exposed pad SOIC packages. • RoHS compliant “Green”/Halogen Free 5-pin TO-252 and 8-pin Exposed pad SOIC Packages • Current Limit and Thermal Protection TYPICAL APPLICATION DIAGRAM Fig. 1: XR P6272 Application Diagram 1 XRP6272 2A 5V-Adjustable Low Dropout Voltage Regulator ABSOLUTE MAXIMUM RATINGS OPERATING RATINGS The se are stress ratings only and functional operat i on o f the de vice at the se ratings or any othe r above those indicated in the operation sections of th e s pe ci fi cat i ons be low is not implied. Ex posu re t o a bsol ut e m ax im um rating conditions for e xtended periods of time may af fe ct re liability. Input Voltage Range VIN ............................. 1.8V to 6V Ope rating Tempe rature Range ................ -40°C to 85°C The rmal R esistance θ JA (5-Pin TO-252) ....................................100°C /W θ JC (5-Pin TO-252) ....................................... 8°C /W θ JA (8-pin HSOIC ) ...................................... 60°C /W θ JC (8-pin HSOIC ) ...................................... 15°C /W VIN, EN, BP ..................................................... 7.0V Storage Tempe rature...........................-65°C to 150°C Powe r Dissipation ............................ Inte rnally Limited Lead Tempe rature (Solde ring, 10 se c)................. 260°C Junction Tempe rature ..................................... 150°C ESD Rating (HBM - Human Body Model) ..................2k V ESD Rating (MM - Machine Mode l)........................ 500V ELECTRICAL SPECIFICATIONS Spe cifications with standard type are for an Operating Junction Temperature of T J = 25°C onl y . M i ni m um an d M ax im um lim its are guaranteed through test, design, or statistical correlation. Typical values represent the m os t l ik e l y p aram e t ri c norm at T J = 25°C , and are provided for re ference purposes only. Unless otherwise indicated, VIN = VOUT + 1V, C IN = 4. 7 µ F , C OUT = 4.7µF or 10µF (Note 1), CBYP = 22nF, T J = 25°C . Parameter Input Voltage O utput Voltage Tolerance C ontinuous O utput C urre nt Min. -2 2 Ground Current Standby C urre nt Line R egulation Load Regulation O utput Curre nt Limit C urre nt Fold Back 2.2 Dropout Voltage (Note 2) R e fere nce Voltage Tolerance ADJ Pin C urrent ADJ Pin Threshold Enable Turn-On Threshold Enable Turn-Off Threshold 0.686 0.05 1.6 Shutdown Pin Current Shutdown Ex it Delay Time Max O utput Discharge Resistance to GND during Shutdown PGO O D R ise Threshold PGO O D Hystere sis PGO O D Delay PGO O D Sink Capability R ipple Reje ction O utput Noise Voltage Te m perature Coefficient The rmal Shutdown Temperature 220DSR00 Typ. 1.8 Max. Units 6.0 +2 V 30 30 0.01 50 50 0.5 3 5 3.0 15 15 3.9 1.0 960 700 550 900 700 480 0.7 10 0.1 600 0.714 100 0.2 0 0.4 0.5 100 3 0.5 % A µA µA mV mV mV µA µs Ω 90 10 93 % 5 0.4 % ms V dB µVrm s 2 VEN ≥ 1.6V, I OUT = 300mA VEN = 0 VIN = VOUT + 1V to 6V, I OUT =1m A I OUT =1m A to 2A I OUT I OUT I OUT I OUT = = = = 2A, 2A, 2A, 2A, VOUT VOUT VOUT VOUT =1.2V =1.8V =3.3V =5.0V V nA V V V 100 50 150 I OUT = 1m A VIN ≥ 2.3V VEN ≥ 1.6V, No Load A A 20 0.2 70 24 Conditions VADJ = VREF O utput ON O utput OFF VEN = 0 I PGOOD = 10m A f=1KHz, R ipple=0.5Vp-p C BP = 22nF, f=10Hz ~100KHz ppm /ᵒC ᵒC VIN = VOUT + 1V Rev. 1.2.2 XRP6272 2A 5V-Adjustable Low Dropout Voltage Regulator Parameter The rmal Shutdown Hysteresis Min. Typ. Max. 20 Units Conditions ᵒC Note 1: In the case of VOUT ≤ 1.8V, C OUT = 10μF is re commended. Note 2: Dropout Voltage is defined as input voltage m inus output voltage whe n the o ut put v o l t age d rops b y 1 % of i t s nom inal value at VIN = VOUT + 1V. Note 3: VIN (min) is the higher value of (VOUT + Dropout Voltage) or 1.8V. BLOCK DIAGRAM Fig. 2: XR P6272 Block Diagram PIN ASSIGNMENT Fig. 3: XR P6272 Pin Assignment 220DSR00 3 Rev. 1.2.2 XRP6272 2A 5V-Adjustable Low Dropout Voltage Regulator PIN DESCRIPTION Name SOIC-8 TO-252 Description EN 1 1 Enable Pin. Minim um 1.6V to e nable the device. Maximum 0.4V to shutdown the device. VIN 2 2 Powe r Input Pin. Must be closely decoupled to GND pin with a 4.7μF or greater ce ramic capacitor. VO UT 3 4 R e gulator O utput pin. ADJ 4 5 Adjustable Pin. O utput Voltage can be set by external feedback re sistors whe n using a resistive divide r. Or, connect ADJ to GND for VO UT = 5V, set by internal feedback re sistors. GND 5, 8 3 BP 6 - PGO O D 7 - GND Ex posed Pad Tab Ground Signal Bypass pin. C onnect a 22nF capacitor to GND to re duce output noise. Bypass pin can be left floating if not necessary. Powe r Good open Drain Output. C onnect to GND. ORDERING INFORMATION Part Number Operating Temperature Range Package Packing Method Lead-Free XR P6272ITC5TR-F -40°C ≤ T A ≤ +85°C 5-pin TO-252 Tape & R e el Ye s XR P6272IDBTR-F -40°C ≤ T A ≤ +85°C 8-pin HSOIC Tape & R e el Ye s NO TES: For the most up-to-date information and additional information on e nvironmental rating, go to www.m ax line ar.com/XRP6272. 220DSR00 4 Rev. 1.2.2 XRP6272 2A 5V-Adjustable Low Dropout Voltage Regulator TYPICAL PERFORMANCE CHARACTERISTICS All data taken at VIN = VOUT + 1V, T J = T A = 25°C , C IN = 4.7µF, C OUT = 4.7µF or 10µF (Note 1) unless otherwise specified. Fig. 4: GND C urre nt vs. VIN at VOUT=1.8V, No Load Fig. 5: GND C urre nt vs. VIN at VOUT=3.3V, No Load Fig. 6: GND C urre nt vs. VIN at VOUT=1.8V, 300mA Fig. 7: GND C urre nt vs. VIN at VOUT=3.3V, 300mA Fig. 8: GND C urre nt vs. Temp. at VOUT=1.8V, No Load Fig. 9: GND C urre nt vs. Temp. at VOUT=3.3V, No Load 220DSR00 5 Rev. 1.2.2 XRP6272 2A 5V-Adjustable Low Dropout Voltage Regulator Fig. 10: Dropout Voltage at VOUT = 1.8V Fig. 11: Dropout Voltage at VOUT = 3.3V Fig. 12: Dropout Voltage at VOUT = 5.0V Fig. 13: Load Transient Response at VOUT=1.8V, VIN=2.8V Fig. 14: Load Transient Response at VOUT=3.3V, VIN=4.3V Fig. 15: Load Transient Response at VOUT=5V, VIN=6V 220DSR00 6 Rev. 1.2.2 XRP6272 2A 5V-Adjustable Low Dropout Voltage Regulator Fig. 16: Enable Startup at VOUT = 1.8V Fig. 17: Shutdown at VO UT = 1.8V Fig. 18: Enable Startup at VOUT = 5V Fig. 19: Shutdown at VO UT = 5V Fig. 20: C urrent Foldback at VOUT = 1.8V Fig. 21: C urrent Foldback at VOUT = 3.3V 220DSR00 7 Rev. 1.2.2 XRP6272 2A 5V-Adjustable Low Dropout Voltage Regulator Fig. 22: PSRR C urve an output ceramic capacitor of at least 4.7µF or 10µF (for VOUT ≤ 1.8V) is recommended. An input capacitor of 4.7µF is recommended. APPLICATION INFORMATION The XRP6272 is a low-dropout voltage regulator with low quiescent current, low noise and high PSRR. It can support load current up to 2A. It incorporates current-limit and thermal protection features. X5R or X7R ceramic capacitors are recommended as they have the best temperature and voltage characteristics. T YPICAL APPLICATION SCHEMATIC NOISE BYPASS CAPACITOR A 22nF bypass capacitor at BP pin can reduc e output voltage noise. This pin can be left floating if it is unnecessary. THEORY OF OPERATION SHUTDOWN By connecting EN pin to GND, the XRP6272 can be shutdown to reduce the supply current to 0.01μA (typ.). In this mode, the output voltage of XRP6272 is equal to 0V. PROGRAMMING T HE OUTPUT VOLTAGE XRP6272’s internal feedback resistors set t he output voltage VOUT to 5V when the ADJ pin is connected to GND. Alternatively; the output voltage is adjustable via the external feedback resistor network R1 and R2 by calculating t he following formula: 𝑉𝑉𝑂𝑂𝑈𝑈𝑇𝑇 = 𝑉𝑉𝑅𝑅𝑅𝑅𝑅𝑅 × �1+ C URRENT LIMIT The XRP6272 includes current limit protec tion feature, which monitors and controls the maximum output current. If the output is overloaded or shorted to ground, this can protect the device from being damaged. R1 � R2 where, VREF is the reference voltage set internally at 0.7V nominal. T HERMAL PROTECTION The XRP6272 includes a thermal protection feature that protects the IC by turning of f t he pass transistor when the maximum junction temperature T J exceeds 150ºC. INPUT & OUTPUT C APACITORS XRP6272 is optimized for use with ceramic capacitors. To ensure stability of t he dev ice, 220DSR00 8 Rev. 1.2.2 XRP6272 2A 5V-Adjustable Low Dropout Voltage Regulator 𝑃𝑃𝐷𝐷(𝑀𝑀𝑀𝑀𝑀𝑀) = (𝑇𝑇𝐽𝐽(𝑀𝑀𝑀𝑀𝑀𝑀) − (𝑇𝑇𝐴𝐴) )⁄ 𝜃𝜃𝐽𝐽𝐽𝐽 POWER DISSIPATION The power dissipation across the device can be calculated as: where, T J(MAX) is the maximum junction temperature, T A is the ambient temperature and ΘJA is the thermal resistance between junction to ambient. In order to insure the best thermal flow, proper mounting of the IC is required. 𝑃𝑃𝐷𝐷 = 𝐼𝐼𝑂𝑂𝑂𝑂𝑂𝑂 × (𝑉𝑉𝐼𝐼𝐼𝐼 - 𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂 ) The total junction temperature is calculated as: 𝑇𝑇𝐽𝐽 = 𝑇𝑇𝐴𝐴 + 𝑃𝑃𝐷𝐷 × 𝜃𝜃𝐽𝐽𝐽𝐽 LAYOUT C ONSIDERATION where, T J is the junction temperature, T A is the ambient temperature and ΘJA is the thermal resistance between junction to ambient. 1. Connect the bottom-side pad to a large ground plane for good thermal conductiv ity and to reduce the thermal resistance of t he device. There is a temperature rise associated with this power dissipated while operating in a given ambient temperature. If the c alculated junction temperature exceeds maximum junction temperature specification, then the built-in thermal protection feature is triggered as described previously. 2. The input capacitor CIN and output capacitor COUT must be placed as close as possible t o the pins VIN and VOUT respectively. 3. Use short wires to connect the power supply to pins VIN and GND on the board. To insure reliable performance, the maximum allowable power dissipation for a given ambient temperature must be considered and it can be calculated as follows: 220DSR00 9 Rev. 1.2.2 XRP6272 2A 5V-Adjustable Low Dropout Voltage Regulator TYPICAL APPLICATIONS APPLICATION 1 Fig. 23: 5V to 3.3V / 2A APPLICATION 2 Fig. 24: 5.8V to 5V R F Stage Low Noise Powe r Supply APPLICATION 3 Fig. 25: 2.7V Min to 1.8V / 2A Powe r Supply 220DSR00 10 Rev. 1.2.2 XRP6272 2A 5V-Adjustable Low Dropout Voltage Regulator MECHANICAL DIMENSIONS TO-252-5L 220DSR00 11 Rev. 1.2.2 XRP6272 2A 5V-Adjustable Low Dropout Voltage Regulator RECOMMENDED LAND PATTERN AND STENCIL TO-252-5L 220DSR00 12 Rev. 1.2.2 XRP6272 2A 5V-Adjustable Low Dropout Voltage Regulator MECHANICAL DIMENSIONS AND RECOMMENDED LAND PATTERN Exposed Pad 8-Pin SOIC 220DSR00 13 Rev. 1.2.2 XRP6272 2A 5V-Adjustable Low Dropout Voltage Regulator REVISION HISTORY Revision Date 1.1.0 1.2.0 10/14/2011 11/30/2011 1.2.1 1.2.2 Description Initial release of Data Sheet. C orre cte d pin assignment package drawing. Updated to MaxLinear logo. Updated Ordering Information. Updated:  TO -252-5L POD’s Mechanical Dimensions. Se pte mber 10, 2021  Ex posed Pad 8-Pin SOIC POD’s Mechanical Dimensions. A dded:  TO -252-5L POD’s R ecommended Land Pattern and Stencil.  Ex posed Pad 8-Pin SOIC POD’s Recommended Land Pattern. 11/01/2019 Corporate Headquarters: 5966 La Place Court Suite 100 Carlsbad, CA 92008 Tel.:+1 (760) 692-0711 Fax: +1 (760) 444-8598 www.maxlinear.com The content of this document is furnished for informational use only, is subject to change without notice, and should not be construed as a commitment by MaxLinear, Inc.. MaxLinear, Inc. assumes no responsibility or liability for any errors or inaccuracies that may appear in the informational content contained in this guide. Complying with all applicable copyright laws is the responsibility of the user. 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MaxLinear, Inc. may have patents, patent applications, trademarks, copyrights, or other intellectual property rights covering subject matter in this document. Except as expressly provided in any written license agreement from MaxLinear, Inc., the furnishing of this document does not give you any license to these patents, trademarks, copyrights, or other intellectual property. MaxLinear, the MaxLinear logo, any MaxLinear trademarks (MxL, Full-Spectrum Capture, FSC, G.now, AirPHY, Puma, and AnyWAN), and the MaxLinear logo on the products sold are all property of MaxLinear, Inc. or one of MaxLinear’s subsidiaries in the U.S.A. and other countries. All rights reserved. Other company trademarks and product names appearing herein are the property of their respective owners. © 2021 MaxLinear, Inc. All rights reserved. 220DSR00 14 Rev. 1.2.2