XRT5683AIP-F

XR-T5683A ...the analog plus PCM Line Interface Chip company TM October 2010 FEATURES
TTL Compatible Interface
Single 5V Supply
Device Can Be Used as a Line Interface Unit Without Clock Recovery
Receiver Input Can Be Either Balanced or Unbalanced APPLICATIONS
T1, T2, E1 & E2 Rates, PCM Line Interface
Up To 8.448Mbps Operation In Both Tx and Rx Directions
Network Multiplexing and Terminating Equipment GENERAL DESCRIPTION The XR-T5683A is a PCM line interface chip consisting of both transmit and receive circuitry. This device is offered in a plastic dual in-line (PDIP) or in a surface mount package (SOIC). The maximum bit rate of the chip is 8.448Mbps, and the signal level to the receiver can be attenuated by -10dB cable loss at one-half the bit rate. At nominal supply voltage operation, the typical current consumption is 40mA. ORDERING INFORMATION Package Operating Temperature Range XR-T5683AIP 18 Lead 300 Mil PDIP -40°C to +85°C XR-T5683AID 18 Lead 300 Mil JEDEC SOIC -40°C to +85°C Part No. BLOCK DIAGRAM 1 RXDATA- 2 RXDATA+ 3 RVCC 9 RGND 7 Peak Detector PDC Positive Threshold Comparator TTLBuffer TTLBuffer Negative Threshold Comparator 11 RPOS 8 RCLK 4 TTLBuffer TE 10 RNEG BIAS 6 TANK BIAS BIAS 5 BIAS TVCC 18 Open Collector Driver TPOS 17 13 TXDATA+ TCLK 16 15 TXDATA- TNEG 12 TGND 14 Open Collector Driver Figure 1. Block Diagram Rev. 2.0.2 2010 EXAR Corporation, 48720 Kato Road, Fremont, CA 94538  (510) 668-7000  FAX (510) 668-7017 1 XR-T5683A PIN CONFIGURATION PDC RXDATARXDATA+ TE BIAS TANK BIAS RGND RCLK RVCC 1 18 2 17 3 16 4 15 5 14 6 13 7 12 8 11 9 10 TVCC TPOS TCLK TXDATATGND TXDATA+ TNEG RPOS RNEG PDC RXDATARXDATA+ TE BIAS TANK BIAS RGND RCLK RVCC 18 Lead PDIP (0.300”) 1 18 2 17 3 16 4 15 5 14 6 13 7 12 8 11 9 10 TVCC TPOS TCLK TXDATATGND TXDATA+ TNEG RPOS RNEG 18 Lead SOIC (JEDEC, 0.300”) PIN DESCRIPTION Pin # Symbol Type Description 1 PDC 2 RXDATA- I Receive Analog Input Positive. Line analog input. 3 RXDATA+ I Receive Analog Input Negative. Line analog input. 4 TE O Tank Excitation Output. This output connects to one side of the tank circuitry. 5 BIAS O Bias. This output is to be connected to the center tap of the receive transformer. 6 TANK BIAS O Tank Bias. The tank circuitry is biased via this output. 7 RGND 8 RCLK 9 RVCC 10 RNEG O Receive Negative Data. Negative pulse data output to the terminal equipment (active low). 11 RPOS O Receive Positive Data. Positive pulse data output to the terminal equipment (active low). 12 TNEG I Transmit Negative Data. TNEG is valid while TCLK is high. 13 TXDATA+ O Transmit Positive Output. Transmit bipolar signal is driven to the line via a transformer. 14 TGND 15 TXDATA- O Transmit Negative Output. Transmit bipolar signal is driven to the line via a transformer. 16 TCLK I Transmit Clock. Timing element for TPOS and TNEG. 17 TPOS I Transmit Positive Data. TPOS is valid while TCLK is high. 18 TVCC Peak Detector Capacitor. This pin should be connected to a 0.1µF capacitor. Receiver Ground. To minimize ground interference a separate pin is used to ground the receive section. O Recovered Receive Clock. Recovered clock signal to the terminal equipment. Receive Supply Voltage. 5V supply voltage to the receive section. Transmit Ground. Transmit Supply Voltage. 5V supply voltage to the transmit section. Rev. 2.0.2 2 XR-T5683A ELECTRICAL CHARACTERISTICS Test Conditions: VCC = 5.0V
5%, TA = 25°C, Unless Otherwise Specified. Parameters Min. Typ. Max. Unit Conditions 4.75 5 5.25 V 40 55 mA Total Current to Pin 9 & Pin 18 Transmitter Outputs Open 500 700 µA Measured at Pin 4, VCC = 5V 0.3 0.6 V Measured at Pin 8, IOL = 1.6mA V Measured at Pin 8, IOH = -400µA V Measured at Pin 10 & 11, IOL = 1.6mA V Measured at Pin 10 & 11, IOH = -400µA DC Electrical Characteristics Supply Voltage Supply Current Receiver Section Tank Drive Current 300 Clock Output Low Clock Output High 3.0 Data Output Low Data Output High 3.6 0.3 0.6 3.0 3.6 0.6 0.8 1.0 V Measured at Pin 13 & 15, IOL = 40mA 0 100 µA Measured in Off State, Output Pull-up to + 20V VCC V Measured at Pin 12, 16 & 17, IOL= 40mA, VOL = 1.0V Input Low Voltage 0.8 V Measured at Pin 12, 16 & 17, Output Off Input Low Current -1.6 mA Measured at Pin 12, 16 & 17, Input Low Voltage = 0. 4V Input High Current 40 µA Measured at Pin 12, 16 & 17, Input High Voltage = 2.7V Output Low Current 40 mA Measured at Pin 13 & 15, VOL = 1.0V 6.6 Transmitter Section Driver Output Low Output Leakage Current Input High Voltage 2.2 AC Electrical Characteristics Receiver Section Input Level Vpp Measured Between Pin 2 & 3 Loss Input Signal Alarm Level 1.6 Vpp Measured Between Pin 2 & 3, Alarm on Pull Data Output High Input Impedance at 8,448MHz 2.5 kΩ Measured Between Pin 2 & 3, With Sinewave Input % Measured at Pin 8 at 2.0V ns Measured at Pin 8, CL = 15pF Clock Duty Cycle 6 35 Clock Rise & Fall Time Data Pulse Width 50 65 20 35 50 75 % of clock period Measured at Pin 10 & 11, at 1V DC Level, Cable Loss = 0 Notes Bold face parameters are covered by production test and guaranteed over operating temperature range. Rev. 2.0.2 3 XR-T5683A ELECTRICAL CHARACTERISTICS (CONT’D) Parameters Min. Typ. Max. Unit Conditions 65 ns Measured at Pin 13 & 15, See Figure 6 AC Electrical Characteristics (Cont’d) Transmitter Section Pulse Width at 8.448MHz 53 Output Rise Time 12 25 ns See Figure 5 Output Fall Time 12 25 ns See Figure 5 Output Pulse Imbalance 2.5 ns At 50% Output Level Specifications are subject to change without notice Notes Bold face parameters are covered by production test and guaranteed over operating temperature range. ABSOLUTE MAXIMUM RATINGS Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . +20V .. Storage Temperature . . . . . . . . . . . . . -65 . °C to +150°C SYSTEM DESCRIPTION The incoming bipolar PCM signal which is attenuated and distorted by the cable is applied to the threshold comparator and the peak detector . The peak detector generates a DC reference for the threshold comparator for data and clock extraction. An external tank circuit tuned to the appropriate frequency is added for the later operation. The clock signal, data (+) and data (-) all go through a similar level shifter to be converted into TTL level to be compatible for digital processing. In the transmit direction, the output drivers consist of two identical TTL inputs with open collector output stages. Rev. 2.0.2 4 The maximum low level current these output stages can sink is 40mA. With full width data (NRZ) applied to the inputs together with a synchronized clock, the output will generate a bipolar signal when driving a center-tapped transformer. A block diagram of the XR-T5683A is shown in Figure 1. The clock recovery uses an external tank circuit. The receive data will create an excitation for the tank circuitry which in turn will create a recovered, received clock (RCLK). XR-T5683A Table 1 shows typical expected jitter tolerance. The following measurements have been done at a transmission rate of T1 (1.544MHz). (See Figure 2). Jitter 1.544Mbs in UI Jitter 1.544Mbs in UI 10Hz >10UI 5kHz 1.3UI 100Hz >10UI 8kHz 0.8UI 500Hz >10UI 10kHz 0.7UI 1kHz 6.5UI 32kHz 0.5UI 2kHz 3.3UI 50kHz 0.45UI 3kHz 2.1UI 77kHz 0.45UI 4kHz 1.5UI - - VCC = +5V
5%, TA = 25°C Table 1. Jitter Tolerance at 1.544Mbps with 6db Cable Loss Jitter Generator HP3785B (transmitter side) 6db Cable Attenuation RXDATA+ XR-T5683A RXDATARX RPOS TPOS RCLK TCLK RNEG TNEG Clock Clock Phase Shift Circuit XR-T5683A TX TXDATA+ TXDATA- Pattern Generator HP3781B Jitter Analyzer HP3785B (Receive Side) Figure 2. Jitter Measurement Set-up Rev. 2.0.2 5 XR-T5683A RXDATA+ RCLK Output at Pin 8 RPOS Output at Pin 11 RNEG Output at Pin 10 Figure 3. Receiver Timing Diagram With 1-1-1-1-1-1 Pattern TCLK Clock to Pin 16 TPOS to Pin 17 TNEG to Pin 12 Bipolar Signal at Transformer Output Figure 4. Transmitter Input Timing Diagram Rev. 2.0.2 6 XR-T5683A VCC = 5V 100 0.1µF Output Pin 13 & 15 CI=15pF2 Pin 9 & 18 8.448MHz Pulse Generator Input 0V XR-T5683A Pin 12,16,171 Pin 7 & 14 0V Notes 1 Inputs that are not connected to pulse generator will be tied to V CC via 1K resistor. 2 C1 includes probe and jig capacitance. Figure 5. Test Circuit 59ns