XRT59L91ID-F

XRT59L91 Single-Chip E1 Line Interface Unit October 1999-1 FEATURES l Complete E1 (CEPT) line interface unit (Transmitter and Receiver) l Supports both Local- and Remote-Loop back Operations l Generates transmit output pulses that are compliant with the ITU-T G.703 Pulse Template for 2.048Mbps (E1) rates l Logic Inputs accept either 3.3V or 5.0V levels l Operates over the Industrial Temperature Range l Ultra Low Power Dissipation l +3.3V Supply Operation l On-Chip Pulse Shaping for both 75Ω and 120Ω Line Drivers l Receiver can either be transformer or capacitively-coupled to the line l Detects and Clears LOS (Loss of Signal) per ITU-T G.775 l Compliant with the ITU-T G.823 Jitter Tolerance Requirements l APPLICATIONS Compliant with the ITU-T G.703 EOS Overvoltage protection requirements l PDH Multiplexers l SDH Multiplexers l Digital Cross-Connect Systems l DECT (Digital European Cordless Telephone) Base Stations l CSU/DSU Equipment. l Test Equipment GENERAL DESCRIPTION The XRT59L91 is an optimized single-chip analog E1 line interface unit (LIU) fabricated using low power, 3.3V CMOS technology. The LIU IC consists of both a Transmitter and a Receiver function. The Transmitter accepts a TTL or CMOS level signal from the Terminal Equipment; and outputs this data to the line via bipolar pulses that are compliant to the ITU-T G.703 pulse template for E1. The Receiver accepts an attenuated bipolar line signal (from the remote terminal equipment) and outputs this data to the (near-end) terminal equipment via CMOS level signals. The receiver input can be transformer or capacitivelycoupled to the line. The receiver input is transformercoupled to the line, using the 2:1 step-down transformer. The transmitter is coupled to the line using a 1:2 step-up transformer. This same configuration is applicable for both balanced (120Ω) and unbalanced (75Ω) interfaces. ORDERING INFORMATION Part No. Package XRT59L91ID 16 LD JEDEC SOIC (300 mil) Operating Temperature Range -40°C to +85°C Rev. 1.0.0 EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 • (510) 668-7000 • FAX (510) 668-7017 XRT59L91 RxLO S RTIP RRing LLoop TTIP Recei Receive Equaliz ve Equalizer er Peak Peak Detector/ Slice Detector/ Slicer r LO SS LO Detect Detector or Receive Receive O utput Interfac O utput Interface e Loca Local Loop lBack Loop Back M MUX UX Rem ot Rem ote Loop e Loop Back MBack MUX UX PulsePulse Shaping Circui Circuit Shaping t Transm it Transm it Input Interfac Input Interface e TRing Figure 1. XRT59L91 Block Diagram Rev. 1.0.0 2 RxPO S RxNEG RLoop TxPO S TxNEG TxClk XRT59L91 PIN CONFIGURATION 1 T xC lk 16 TVSS T xP O S T R in g T xN E G TVDD L L oo p T T IP R L o op RVDD R xP O S RVSS R xN E G R R ing R xL O S 8 9 R T IP PIN DESCRIPTION Pin# Symbol Type 1 TxClk I Description Transmitter Clock Input: If the user operates the LIU in the “clocked” mode, then the “Transmit Section” of the LIU will use the falling edge of this signal to sample the data at the TxPOS and TxNEG input pins. Note: If the user operates the LIU in the “clockless” mode, then the Terminal Equipment should not apply a clock signal to this input pin. 2 TxPOS I Transmit – Positive Data Input: The exact signal that should be applied to this input pin depends upon whether the user intends to operate the “Transmit Section” (of the device) in the “Clocked” or “Clockless” Mode. Clocked Mode The Terminal Equipment should apply bit-wide NRZ pulses on this input pin, whenever the Terminal Equipment needs to transmit a “positivepolarity” pulse onto the line via TTIP and TRing output pins. The XRT59L91 device will sample this input pin upon the falling edge of the TCLK signal. Clockless Mode The Terminal Equipment should apply RZ pulses to this input pin, anytime the Terminal Equipment needs to transmit a “positive-polarity” pulse onto the line via TTIP and TRing output pins. Rev. 1.0.0 3 XRT59L91 PIN DESCRIPTION Pin# Symbol Type 3 TxNEG I Description Transmit – Negative Data Input: The exact signal that should be applied to this input pin depends upon whether the user intends to operate the “Transmit Section” (of the device) in the “Clocked” or “Clockless” Mode. Clocked Mode The Terminal Equipment should apply bit-wide NRZ pulses on this input pin, whenever the Terminal Equipment needs to transmit a “negative-polarity” pulse onto the line via TTIP and TRing output pins. The XRT59L91 device will sample this input pin upon the falling edge of the TClk signal. Clockless Mode The Terminal Equipment should apply RZ pulses to this input pin, anytime the Terminal Equipment needs to transmit a “negativepolarity” pulse onto the line via TTIP and TRing output pins. 4 LLoop I Local Loopback Input Select: This input pin permits the user to configure the XRT59L91 device to operate in the “Local Loopback” Mode; in order to support Diagnostic Operations. When the XRT59L91 device is operating in the Local Loopback Mode, then TTIP and TRing output signals will be (internally) routed to RTIP and RRing input signals. Setting this input pin “high” configures the XRT59L91 device to operate in the “Local Loopback” Mode. Setting this input pin “low” configures the XRT59L91 device to operate in the “Normal” Mode. Note: Pulling both the “LLoop” and “RLoop” input pins to VDD, simultaneously, will cause the XRT59L91 device to operate in the “InCircuit Test” Mode. In this mode, all output pins will be tri-stated. 5 RLoop I Remote Loopback Input Select: This input pin permits the user to configure the XRT59L91 device to operate in the “Remote Loopback” Mode; in order to support Diagnostic Operations. When the XRT59L91 device is operating in the Remote Loopback Mode, then the RxPOS and RxNEG output pins will be (internally) routed to the TxPOS and TxNEG input pins. Setting this input pin “high” configures the XRT59L91 device to operate in the “Remote Loopback” Mode. Setting this input pin “low” configures the XRT59L91 device to operate in the “Normal” Mode. Note: Pulling both the “LLoop” and “RLoop” input pins to VDD, simultaneously, will cause the XRT59L91 device to operate in the “InCircuit Test” Mode. In this mode, all output pins will be tri-stated. Rev. 1.0.0 4 XRT59L91 PIN DESCRIPTION Pin# Symbol Type 6 RxPOS O Description Receive Positive Pulse Output: This output pin will pulse “high” whenever the XRT59L91 device has received a “Positive Polarity” pulse, in the incoming line signal, at RTIP/RRing inputs. 7 RxNEG O Receive Negative Pulse Output: This output pin will pulse “high” whenever the XRT59L91 device has received a “Negative Polarity” pulse, in the incoming line signal, at RTIP/RRing inputs. 8 RxLOS O Receive Loss of Signal Output Indicator: This output pin toggles “high” if the XRT59L91 device has detected a “Loss of Signal” condition in the incoming line signal. 9 RTIP I Receive TIP Input: This input pin, along with RRing is used to receive the bipolar line signal from the “Remote E1 Terminal”. 10 RRing I Receive Ring Input: This input pin, along with RTIP is used to receive the bipolar line signal from the “Remote E1 Terminal”. 11 RVSS - Receiver Ground Pin 12 RVDD - Receiver Power Supply Pin: 3.3V + 5% 13 TTIP O Transmit TIP Output: The XRT59L91 device will use this pin, along with TRing, to transmit a bipolar line signal, via a 1:2 step-up transformer. 14 TVDD - Transmitter Power Supply Pin: 3.3V + 5% 15 TRing O Transmit Ring Output: The XRT59L91 device will use this pin, along with TTIP, to transmit a bipolar line signal, via a 1:2 step-up transformer. 16 TVSS - Transmitter Ground Pin Rev. 1.0.0 5 XRT59L91 AC ELECTRICAL CHARACTERISTICS 25°C Unless otherwise specified: TA= VDD=3.3V±5%, unless otherwise specified. Parameter Symbol Min Typ Max Unit T1 - 488 - ns TClk Clock Period TClk Duty Cycle T2 47 50 53 % Transmit Data Setup Time TSU 50 - - ns Transmit Data Hold Time Transmit Data Prop. Delay Time THO T3 30 - - ns - 50 - ns - 50 - ns - - 40 ns - RZ data Mode - NRZ data Mode (clock mode) TClk Rise Time(10%/90%) TR TClk Fall Time(90%/10%) TF - - 40 ns Receive Data Rise Time Rtr - - 40 ns Receive Data Fall Time Rtf - - 40 ns Receive Data Prop. Delay Rpd - 160 - ns Receive Data Pulse Width Rxpw 210 244 450 ns DC ELECTRICAL CHARACTERISTICS 25°C Unless otherwise specified: TA=-, VDD=3.3V±5%, unless otherwise specified. Parameter Symbol Min Typ Max Unit Power Supply Voltage VDD 3.13 3.3 3.46 V Input High Voltage VIH 2.0 - 5.0 V Input Low Voltage VIL -0.5 - 0.8 V Output High Voltage @ IOH = -4mA VOH 2.4 - - V Output Low Voltage @ IOL = 4mA VOL - - 0.4 V IL - - ± 10 µA Input Leakage Current (except Input pins with pull-up resistor Input Capacitance CI - 5.0 - pF Output Load Capacitance CL - - 25 pF Power Consumption including the line power dissipation, tranmission and receive paths all active Unless otherwise specified: TA=-40 to 85°C, VDD=3.3V±5%, unless otherwise specified. Parameter Power Consumption Symbol Min Typ Max Unit Conditions PC - 130 145 mW 75Ω load, operating at 50% Mark Density Power Consumption PC - 115 130 mW 120Ω load, operating at 50% Mark Density Power Consumption PC - 170 185 mW 75Ω load, operating at 100% Mark Density Power Consumption PC - 140 155 mW 120Ω load, operating at 100% Mark Density Power Consumption PC - 25 30 mW Transmitter in Powereddown mode Rev. 1.0.0 6 XRT59L91 RECEIVER ELECTRICAL CHARACTERISTICS TA=-40 to 85°C, VDD=3.3V±5%, unless otherwise specified. Parameter Min Typ Max Unit Test Conditions Receiver Loss of Signal: Threshold to Assert Threshold to Clear Time Delay Hysteresis Receiver Sensitivity 12 11 10 11 20 15 5 13 255 - dB dB bit dB dB Interference Margin Input Impedance -18 - -14 5 - dB KΩ Jitter Tolerance: 20Hz 700Hz 10KHz —100KHz 10 5 0.3 - - UIpp Return Loss: 51KHz —102KHz 102KHz—2048KHz 2048KHz—3072KHz 14 20 16 - - dB dB dB per ITU-G.703 Test Conditions Cable attenuation @ 1024KHz per ITU-G.775 Below nominal pulse amplitude of 3.0V for 120Ω and 2.37V for 75Ω applications. With -18dB interference signal added. With 6dB cable loss TRANSMITTER ELECTRICAL CHARACTERISTICS TA=-40 to 85°C, VDD=3.3V±5%, unless otherwise specified. Parameter AMI Output Pulse Amplitude: Min Typ Max Unit 75Ω Application 120Ω Application 2.13 2.70 2.37 3.00 2.60 3.30 V Output Pulse Width Output Pulse Width Ratio Output Pulse Amplitude Ratio 224 0.95 0.95 244 1.00 1.00 264 1.05 1.05 ns - 10 16 12 - - dB dB dB Output Return Loss: 51KHz —102KHz 102KHz—2048KHz 2048KHz—3072KHz ABSOLUTE MAXIMUM RATINGS Storage Temperature ○ Operating Temperature Supply Voltage ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ -65°C to + 150°C ○ ○ -40°C to + 85°C ○ -0.5V to + 6.0V Rev. 1.0.0 7 Use transformer with 1:2 ratio and 9.1Ω resistor in series with each end of primary. per ITU-G.703 per ITU-G.703 per ETSI 300 166 and CH PTT XRT59L91 SYSTEM DESCRIPTION 1.1 The XRT59L91 device is a single channel E1 transceiver that provides an electrical interface for 2.048Mbps applications. XRT59L91 includes a receive circuit that converts an ITU-T G.703 compliant bipolar signal into a TTL compatible logic levels. Each receiver also includes an LOS (Loss of Signal) detection circuit. Similarly, in the Transmit Direction, the Transmitter converts TTL compatible logic levels into a G.703 compatible bipolar signal. The Transmitter may be operated in either a “Clocked” or “Clockless” Mode. The Transmit Input Interface accepts either “clocked” or “clockless” data from the Terminal Equipment. The manner in which the Terminal Equipment should apply data to the XRT59L91 device depends upon whether the device is being operated in the “clocked” or “clockless” mode. 1.2.1 Operating the Transmitter in the Clocked Mode The user can configure the XRT59L91 device to operate in the “Clocked” mode by simply applying a 2.048MHz clock signal to the “TxClk” input pin. The XRT59L91 device contains detectioncircuitry that sense activity on the “TxClk” line. If this circuit senses activity on the “TxClk” line, then the XRT59L91 will automatically be operating in the “Clocked” Mode. The XRT59L91 device consists of both a Transmit Section and a Receive Section; each of these sections will be discussed in detail below. 1.0 The Transmit Section In general, the purpose of the “Transmit Section” (within the XRT59L91 device) is to accept TTL/CMOS level digital data (from the Terminal Equipment), and to encode it into a format such that it can: In the Clocked Mode, a 2.048 mHz clock should be applied toTxClk input pin and NRZ data at the TxPOS and TxNEG input pins. The “Transmit Input Interface” circuit will sample the data, at the TxPOS and TxNEG input pins, upon the falling edge of TxClk, as illustrated below. 1. Be efficiently transmitted over coaxial- or twistedpair cable at the E1 data rate; and 2. Be reliably received by the Remote Terminal Equipment at the other end of the E1 data link. 3. Comply with the ITU-T G.703 pulse template requirements, for E1 applications. The circuitry that the Transmit Section (within the XRT59L91 device) uses to accomplish this goal is discussed below. The Transmit Section of the XRT59L91 device consists of the following blocks: l l The Transmit Input Interface Transmit Input Interface Pulse Shaping Block Rev. 1.0.0 8 XRT59L91 tSU tHO TxPO S TxNEG TClk Figure 2. Illustration on how the XRT59L91 Device Samples the data on the TXPOS and TXNEG input pins In general, if the XRT59L91 device samples a “1” on the TxPOS input pin, then the “Transmit Section” of the device will ultimately generate a positive polarity pulse via the TTIP and TRing output pins (across a 1:2 transformer). Conversely, if the XRT59L91 device samples a “1” on the “TxNEG” input pin, then the “Transmit Section” of the device will ultimately generate a negative polarity pulse via the TTIP and TRing output pins (across a 1:2 transformer). 1.2.1 Operating the Transmitter in the “Clockless” Mode The user can configure the XRT59L91 device to operate in the “Clockless” mode by doing the following: l Not applying a clock signal to the TXClk input, and either pulling this pin to VDD or letting it float. By applying RZ (Return to Zero) data to the TxPOS and TxNEG input pins, as illustrated below. l B it P e rio d D a ta 1 R Z P u lse w id th sh o u ld co n fo rm to G .7 0 3 T e m p la te 1 0 N o p u lse is to b e a p p lie d in th e se co n d h a lf o f th e b it p e rio d 1 1 0 1 T xP O S T xN E G T xC lk N o A ctivity in T xC lk L in e Figure 3. IIlustration on how the Terminal Equipment should apply data to the “Transmit Section” of the XRT59L91 Device, when operating in the “Clockless” Mode Rev. 1.0.0 9 XRT59L91 Figure 3, indicates that when the user is operating the XRT59L91 device in the “Clockless” Mode, then the Terminal Equipment must do the following. l l 1.3 The Pulse Shaping Circuit The purpose of the “Transmit Pulse Shaping” circuit is to generate “Transmit Output” pulses that comply with the ITU-T G.703 Pulse Template Requirements for E1 Applications. Not apply a signal on the “TxClk” line. When applying a pulse (to either the TxPOS or TxNEG input pin), apply an RZ pulse to the appropriate input pin. This RZ pulse should only have a width of one-half the bit-period. Addition, the RZ pulse should occupy only the first half of the bit-period. The TxPOS and TxNEG input pins must be at 0V, during the second half of every bitperiod. An illustration of the “ITU-T G.703 Pulse Template Requirements” is presented below in Figure 4. 269ns (244 + 25) 194ns V = 100% Nominal Pulse 50% 244ns 0% 219ns (244 - 25) 10% 10% 20% Figure 4. Illustration of the ITU-T G.703 Pulse Template for E1 Application Rev. 1.0.0 10 XRT59L91 1.2 With input signal as described above, the XRT59L91 device will take each mark (which is provided to it via the “Transmit Input Interface” block, and will generate a pulse that complies with the pulse template, presented in Figure 4 (when measured on the secondary-side of the Transmit Output Transformer). Interfacing the Transmit Section of the XRT59L91 device to the Line ITU-T G.703 specifies that the E1 line signal can be transmitted over coaxial cable and terminated with 75Ω or transmitted over twisted-pair and terminated with 120Ω. In both applications (e.g., 75Ω or 120Ω), the user is advised to interface the Transmitter to the Line, in the manner as depicted in Figures 5 and 6, respectively. U1 2 TxPOS 13 TxPOS 1 R1 2 J1 TTIP 9.1 BNC 1 1:2 5 4 8 1 3 TxNEG TxNEG 2 PE-65835 1 TxLineClk 15 TxClk 1 R2 2 TRing 9.1 XRT59L91 Figure 5. Illustration of how to interface the Transmit Section of the Ω” Applications) XRT59L91 device to the Line (for “75Ω Rev. 1.0.0 11 XRT59L91 U1 2 T xP O S 13 T xP O S 1 R1 2 T T IP 9 .1 1 1 :2 5 T T IP 3 T xN E G T xN E G 4 8 T R IN G P E -65 8 35 1 T xL in eC lk 1 15 T xC lk R2 2 T R ing 9 .1 X R T 59 L 9 1 Figure 6. Illustration of how to interface the Transmit Section of the XRT59L91 Ω” Applications) device to the Line (for “120Ω Notes: 1. Figures 5 and 6 indicate that for both “75Ω and “120Ω” applications, the user should connect a 9.1Ω resistor, in series, between the TTIP/TRing outputs and the transformers. 2. Figure 5 and 6 indicate that the user should a “1:2 STEP-UP” Transformer. Rev. 1.0.0 12 XRT59L91 Transmit Transformer Recommendations Parameter Value Turns Ratio 1:2 Primary Inductance Isolation Voltage Leakage Inductance The Following Transformers Are Recommended For Use: Part Num ber PE-65835 TTI 7154-R TG26-1205 Vendor Pulse Transpower Technologies, Inc. HALO Isolation Package Type Note: More transformers will be added to this list as we take the time to evaluate these transformers. Magnetic Supplier Information Pulse Transpower Technologies Corporate Office 12220 World Trade Drive San Diego, CA 92128 Tel: (619)-674-8100 FAX: (619)-674-8262 Corporate Office 9410 Prototype Drive, Ste #1 Reno, NV 89511 Tel: (800)511-7308 or (775)852-0140 Fax: (775)852-0145 www.trans-power.com Europe 1 & 2 Huxley Road The Surrey Research Park Guildford, Surrey GU2 5RE United Kingdom Tel: 44-1483-401700 FAX: 44-1483-401701 HALO Electronics HALO Electronics P.O. Box 5826 Redwood City, CA 94063 Tel: (650)568-5800 FAX: (650)568-6161 Asia 150 Kampong Ampat #07-01/02 KA Centre Singapore 368324 Tel: 65-287-8998 FAX: 65-280-0080 Rev. 1.0.0 13 XRT59L91 2.0 The Receive Section 2.1 Interfacing the Receive Section to the Line The Receive Section of the XRT59L91 device consists of the following blocks: The design of the XRT59L91 device permits the user to transformer-couple or capacitive-couple the Receive Section to the line. Additionally, as mentioned earlier, the specification documents for E1 specify 75Ω termination loads, when transmitting over coaxial cable, and 120Ω loads, when transmitting over twistedpair. Figures 7 through 9 present the various methods that the user can employ in order to interface the Receiver (of the XRT59L91 device) to the line. l l l l The “Receive Equalizer” block The “Peak Detector” and “Slicer” block The “LOS Detector” block The “Receive Output Interface” block U1 R xP O S 6 R xP O S R T IP 9 J1 BNC 2 1 7 5 RL R xN E G 1 8.7 4 8 P E-6 58 3 5 1 L oss o f Sig na l 8 R xL O S 1 2 R xN E G 1 :2 10 R R in g X RT5 9L91 Figure 7. Recommended Schematic for Interfacing the Receive Section of the XRT59L91 Ω Applications (Transformer-Coupling) Device to the Line for 75Ω Rev. 1.0.0 14 XRT59L91 U1 R xP O S 6 9 R xP O S R T IP 1 1 R xN E G 7 1 :2 5 R T IP RL R xN E G 3 0 .1 4 8 R R IN G P E -6 5 8 3 5 2 L o s s o f S ig n a l 10 8 R xL O S R R in g XRT59L91 Figure 8. Recommended Schematic for Interfacing the Receive Section of the XRT59L91 Ω Applications (Transformer-Coupling) Device to the Line for 120Ω Note: Figures 7 and 8 indicate that the user should use a “2:1 STEP-DOWN” transformer, when interfacing the re ceiver to the line. U1 C1 R xP O S 6 R xP O S R T IP 9 1 2 1 R1 2 R T IP 37 .4 0.1uF 1 R xN E G 7 R2 R xN E G 37 .4 2 C2 Lo ss of S ig nal 8 10 R xLO S 1 2 R R in g 0.1uF XRT59L91 Figure 9. Recommended Schematic for Interfacing the Receive Section of the XRT59L91 Ω Applications (Capacitive-Coupling) Device to the Line for 75Ω Rev. 1.0.0 15 R R IN G XRT59L91 2.2 The “Receive Equalizer” Block After the XRT59L91 device has received the incoming line signal, via the RTIP and RRing input pins, the first block that this signal will pass through is the Receive Equalizer block. amplification (which attempts to counter the frequency-dependent loss that the line signal has experienced). By doing this, the Receive Equalizer is attempting to restore the shape of the line signal so that the received data can be recovered reliably. As the line signal is transmitted from a given “Transmitting” terminal, the pulse shapes (at that location) are basically “square”. As this line signal travels from the “transmitting terminal” (via the coaxial cable or twisted pair) to the receiving terminal, it will be subjected to “frequency-dependent” loss. In other words, the higher frequency components of the signal will be subjected to a greater amount of attenuation than will the lower frequency components. If this line signal travels over reasonably long cable lengths, then the shape of the pulses (which were originally square) will be distorted and cause inter-symbol interference to increase. 2.3 The “Peak Detector and Slicer Block After the incoming line signal has passed through the Receive Equalizer block, it will be routed to the “Slicer” block. The purpose of the “Slicer” block is to quantify a given bit-period (or symbol) within the incoming line signal as either a “1” or a “0”. 2.4 The “LOS Detector” Block The LOS Detector block, within the XRT59L91 was specifically designed to comply with the “LOS Declaration/Clearance” requirements per ITU-T G.775. As a consequence, the XRT59L91 device will declare an LOS Condition, (by driving the “RxLOS” output pin “high”) if the received line signal amplitude drops to – 35dB or below. Further, the XRT59L91 device will clear the LOS Condition if the signal amplitude rises back up to –12dB or above. Figure 10 presents an illustration of G.775 spec for declaring and clearing LOS. The purpose of this block is to equalize the incoming distorted signal, due to cable loss. In essence, the Receive Equalizer block accomplishes this by subjecting the received line signal to “frequency-dependent” 0 dB Maximum Cable Loss for E1 LOS Signal Must be Cleared -6 dB -9dB LOS Signal may be Cleared or Declared -35dB LOS Signal Must be Declared Figure 10. Illustration of G.775 Spec. Rev. 1.0.0 16 XRT59L91 Timing Requirements associated with Declaring and Clearing the LOS Indicator. clear the LOS indicator within 10 to 255 UI after restoration of the incoming line signal. Figure 11 illustrates the LOS Declaration and Clearance behavior, in response to first, the “Loss of Signal” event and then afterwards, the restoration of the signal. The XRT59L91 device was designed to meet the ITUT G.775 specification timing requirements for declaring and clearing the LOS indicator. In particular, the XRT59L91 device will declare LOS, between 10 and 255 UI (or E1 bit-periods) after the actual time the LOS condition occurred. Further, the XRT59L91 device will L in e S igisn a l R e sto re d A ctu a l O ccu o f Lrre O Sn ce C o n d itio n R X IN 10 U I 255 U I T im e R a n g e LfoOrS D e cla ra tio n 10 U I 255 U I L O S O u tp u t P in 0 UI 0 UI G .7 7 5 C o m p lia n ce T im e R a n g e Lfo O rS C le a ran ce N ote : F o r E 1 , 1 U I = 4 8 8 n s G .7 7 5 C o m p lia n ce Figure 11. The Behavior of the LOS Output Indicator, in response to the Loss of Signal, and the Restoration of the Signal 2.5 The “Receive Output Interface” Block The purpose of the “Receive Output Interface” block is to interface directly with the “Receiving Terminal Equipment”. The “Receive Output Interface” block outputs the data (which has been recovered from the incoming line signal) to the “Receive Terminal Equipment” via the “RxPOS and RxNEG output pins. RRing input pins, then the Receive Output Interface will output a pulse at the “RxPOS” output pin. Similarly, if the “Receive Section” of the XRT59L91 device has received a “Negative-Polarity” pulse, via the RTIP and RRing input pins, then the Receive Output Interface will output a pulse at the “RxNEG” output pin. If the “Receive Section” of the XRT59L91 device has received a “Positive-Polarity” pulse, via the RTIP and Rev. 1.0.0 17 XRT59L91 3.0 Diagnostic Features Mode) into the XRT59L91 device via the TxPOS, TxNEG and TxCLK input pins. This data will be processed through the “Transmit Terminal Input Interface” and the “Pulse Shaping” circuit. Finally, this data will be output to the line via the TTIP and TRing output pins. Additionally, this data (which is being output via the TTIP and TRing output pins) will be looped back into the “Receive Equalizer” block. As a consequence, this data will also be processed through the entire “Receive Section” of the XRT59L91 device. After this “post-loopback” data has been processed through the “Receive Section” it will output, to the “Near-End Receiving Terminal Equipment” via the “RxPOS and RxNEG output pins. In order to support diagnostic operations, the XRT59L91 supports the following loopback modes: l l Local Loopback Remote Loopback Each of these loopback modes will be discussed below. 3.1 The Local Loop-Back Mode When the XRT59L91 device is configured to operate in the “Local Loop-back” Mode, the XRT59L91 device will ignore any signals that are input to the RTIP and RRing input pins. The “Transmitting Terminal Equipment” will transmit data (and clock, for “Clocked” Figure 12, illustrates the path that the data takes (within the XRT59L91 device), when the chip is configured to operate in the “Local Loop-back” Mode. R xLO S R TIP R ece ive E qua lizer P eak D etector/ S licer LO S D etector R ece ive O utput Interface R R ing LLoop R xP O S R xN E G Local Loop B ack MUX Local Loop B ack P ath R em ote Loop B ack MUX TTIP R Loop TxP O S P ulse S haping C ircu it Tra nsm it Input Interface TxN E G TxC lk TR ing Figure 12. Illustration of the “Local Loop-back” within the XRT59L91 Device Rev. 1.0.0 18 XRT59L91 The user can configure the XRT59L91 device to operate in the “Local Loop-back” Mode, by pulling the “LLoop” input pin (pin 4) to VDD. 3.2 “RxPOS” and “RxNEG” output pins. Additionally, this data will also be internally looped back to the “Transmit Input Interface” block within the “Transmit Section”. At this point, this data will be routed through the remainder of the “Transmit Section” of the XRT59L91 device and will be transmitted out onto the line via the “TTIP” and “TRing” output pins. The Remote Loop Back Mode When the XRT59L91 device is configured to operate in the “Remote Loop-back” Mode, the XRT59L91 device will ignore any signals that are input to the TxPOS and TxNEG input pins. The XRT59L91 device will receive the incoming line signals, via the RTIP and RRing input pins. This data will be processed through the entire Receive Section (within the XRT59L91) and will output to the “Receive Terminal Equipment” via the Figure 13, illustrates the path that the data takes (within the XRT59L91 device) when the chip is configured to operate in the “Remote Loop-back” Mode. R xLO S R TIP R R ing R xP O S R eceive R eceive E q ualize r E q ualize r Lo cal Lo cal Lo op B ack Lo op B ack MUX MUX LL oop P e ak D ete ctor/ P e ak D ete ctor/ S licer S licer LO S LO S D etector D etector R em o te Loop B a ck P a th R eceive O utpu t R eceive O utpu t In terface In terface R em o te R em o te Lo op B ack Lo op B ack MUX MUX TTIP R xN E G R Loop TxP O S P u lse S ha ping P u lse S ha ping C ircuit C ircuit Transm it In put Transm it In put In terface In terface TxN E G TxC lk TR ing Figure 13. Illustration of the “Remote Loop-back” path, within the XRT59L91 Device It should be noted that during “Remote Loop-back” operation, any data which is input via the RTIP and RRING input pins, will also be output to the Terminal Equipment, via the RxPOS and RxNEG output pins. Rev. 1.0.0 19 XRT59L91 Method 1: Connect the Transmit Data input pins (e.g., TxPOS and TxNEG) to a logic “1”; or allow them to float. (These input pins have an internal “pull-up” resistor). 4.0 Shutting off the Transmitter The XRT59L91 device permits the user to shut the “Transmit Driver” within the Transmit Section of the chip. This feature can be useful for system redundancy design considerations or during diagnostic testing. The user can activate this feature by either of the following ways. Method 2: Connect the “TxClk” input pin to a logic “0” (e.g., GND) and continue to apply data via the TxPOS and TxNEG input pins. NRZ M ode (Clock M ode) T1 TR T2 T C lk TS U T xP O S o r TNEG TF TH O T3 T XPW V TX O U T T T IP / T R ing RZ M ode (None-Clock M ode) T xP O S o r TNEG T XPW T3 V TX O U T T T IP / T R ing Figure 14. Transmit Timing Diagram Rev. 1.0.0 20 XRT59L91 R T IP / R R in g R p d R xp w R xP O S R tr R tf R xN E G Figure 15. Receive Timing Diagram APPLICATIONS INFORMATION Figures 16, 17 and 18, provide example schematics on how to interface the XRT59L91 device to the line, under the following conditions: l l l Receiver is Transformer-coupled to a 75Ω unbalanced line. Receiver is Transformer-coupled to a 120Ω balanced line. Receiver is Capacitive-coupled to a 75Ω unbalanced line Rev. 1.0.0 21 XRT59L91 U1 2 T xP O S T xP O S T TIP 13 1 R1 9 .1 3 1 T xLin eC lk BNC 1 1 :2 5 4 8 1 T xN E G T xC lk 2 T xN E G J1 2 T R in g 15 1 R2 P E -6 5 83 5 2 9 .1 6 R xP O S R xP O S R TIP J2 9 BNC 1 1 1 :2 5 4 8 1 R3 7 1 8.7 R xN E G 2 R xN E G 2 8 L oss o f S ig n a l R xL O S R R in g 10 P E -6 5 83 5 XRT59L91 Figure 16. Illustration on how to interface the XRT59L91 Device to the Line Ω unbalanced line) (Receiver is Transformer-coupled to a 75Ω Rev. 1.0.0 22 XRT59L91 U1 2 Tx P O S Tx P O S TT IP 13 1 R1 2 9 .1 3 Tx N E G 1 Tx LIn e C lk 1 1 :2 5 4 8 TT IP Tx N E G Tx C lk TR in g 15 1 R2 2 TR IN G P E -6 5 83 5 9 .1 6 RxPOS RxPOS R T IP 9 2 1 1 :2 5 4 8 R3 7 RxNEG 3 0.1 RxNEG 1 8 L os s of S ign a l R x LO S R T IP R R in g 10 P E -6 5 83 5 XRT59L91 Figure 17. Illustration on how to interface the XRT59L91 Device to the Line Ω balanced line) (Receiver is Transformer-coupled to a 120Ω Rev. 1.0.0 23 R R IN G XRT59L91 U1 2 T xP O S 3 1 T xL in e C lk T TIP 13 R1 1 J1 2 BNC 9 .1 1 1 :2 5 4 8 R2 P E -6 5 83 5 1 T xN E G T xC lk 2 T xN E G T xP O S T R ing 15 1 2 9 .1 J2 BNC C1 6 R xP O S R xP O S R TIP 9 1 2 R3 2 1 3 7 .4 1 0 .1 u F 1 2 7 R xN E G R4 R xN E G 3 7 .4 C2 R xL O S R R ing 10 1 2 2 8 L o ss o f S ig n al 0 .1 u F XRT59L91 Figure 18. Illustration on how to interface the XRT59L91 Device to the Line Ω unbalanced line) (Receiver is Capacitive-coupled to a 75Ω Rev. 1.0.0 24 XRT59L91 Rev. 1.0.0 25 XRT59L91 Notes Rev. 1.0.0 26 XRT59L91 Notes Rev. 1.0.0 27 XRT59L91 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for in accuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 1999 EXAR Corporation Datasheet October 1999 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. Rev. 1.0.0 28