XRT6164AIDTR-F

XRT6164A Digital Line Interface Transceiver October 2007 FEATURES z Single 5V Supply z Compatible with CCITT G.703 64Kbps CoDirectional Interface Recommendation When Used With Either XRT6165 or XRT6166 z Low Power z Converts Balanced CMOS Transmit and Receive Signals Propagated Over Two Twisted Pair Cables to TTL Compatible Dual-Rail Data z z Receive Data Comparator Threshold Storage Provides Ping-Pong Operation Capability z Loss of Signal Alarm z Dual Matched Driver Outputs APPLICATIONS z Data Adaption Unit (DAU) z General Purpose TTL Compatible Line Interface Links Remote Equipment Equipped With CCITT G.703 64Kbps Co-Directional Interfaces Over Distances Up to 500 Meters Without Equalization GENERAL DESCRIPTION The XRT6164A is a CMOS analog chip intended for general purpose line interface applications at bit rates up to 1.544Mbps (T1). It contains both receive and transmit circuitry in a 16-pin dual-in-line plastic (PDIP) package. The receiver is designed for short line applications having a cable loss up to 10dB measured at the half bit rate. The transmitter has open collector line driver outputs that are capable of handling up to 40mA. When used in conjunction with either XRT6165 or XRT6166, the chip set provides a 64Kbps codirectional interface as specified in CCITT G.703. ORDERING INFORMATION Part No. Package XRT6164AIP XRT6164AID 16-Lead 300 Mil PDIP 16-Lead 300 Mil JEDEC SOIC Operating Temperature Range -40° C to +85° C -40° C to +85° C Rev. 3.0.1 EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 • (510) 668-7000 • FAX (510) 668-7017 XRT6164A Block DIagram PEAK CAP RX+I/P RX-I/P TCM CON Positive Data Comparator 14 16 1 15 Peak Detector S+R 5 S-R TTL Buffer Threshold Generator Negative Data Comparator TCM Control 12 TTL Buffer 3 RX ALARM 2 I/P BIAS TTL Buffer VCCA 13 GNDA 4 Bias Open Collector Driver TX+I/P 11 10 TX + O/P TX-I/P 6 8 TX - O/P Open Collector Driver VCCD 9 GNDD 7 Figure 1. XRT6164A Block Diagram Rev. 3.0.1 2 XRT6164A PIN CONFIGURATION 16 Lead PDIP (0.300”) 16 Lead SOIC (Jedec, 0.300”) PIN DESCRIPTION Pin# 1 2 3 4 5 6 7 8 Symbol Type RX-I/P I I/P BIAS O RX ALARM O GNDA S-R O TX-I/P I GNDD TX-O/P O 9 VCCD 10 TX+O/P 11 TX+I/P 12 S+R 13 V CCA 14 PEAKCAP 15 TCM CON charge 16 RX+I/P O I O I I Description Receiver Negative CMOS Input. Line analog input. Receive Input Bias. Connects to center tap of input transformer secondary winding. Loss of Signal Alarm. Active low. Analog Ground. Receive Negative Data Output. Output from negative CMOS input pulses (active low). Transmit Negative Input Data. Input for negative output driver (active high). Digital Ground. Transmit Negative Output Driver. Open collector, drives output transformer primary. +5V +/-5% Digital Supply. Transmit Positive Output Driver. Open collector, drives output transformer primary. Transmit Positive Input Data. Input for positive output driver (active high). Receive Positive Data Output. Output from positive CMOS input pulses (active low). +5V +/-5% Analog Supply. Peak Detector Capacitor. Stores peak detector voltage. Time Compression Multiplex Control. When active, disconnects peak detector and discharge paths (active low). Receiver Positive CMOS Input. Line analog input. Rev. 3.0.1 3 XRT6164A ELECTRICAL CHARACTERISTICS Test Conditions: V CC = 5V +/- 5%, T A = 25°C, Unless Otherwise Specified Parameters DC Electrical Characteristics Supply Voltage Analog Supply Current Digital Supply Current Receiver Input Signal Dynamic Range Input Impedance Input Slicing Threshold Input Bias Voltage Loss of Signal Alarm Threshold Loss of Signal Alarm Level Hysteresis Peak Detector Leakage Data Output Low Data Output High Alarm Output Low Alarm Output High Min. Typ. 4.75 5 7 17 5.25 10 22 V mA mA 1 2.2 10 Vp dB kΩ % V mVp dB 20 50 1.45 150 1.5 -80 AC Electrical Characteristics Receiver Input Level Output Rise Time Output Fall Time µA V V V V 0.4 3.0 0.4 V CC 0.5 TCM Input Low Voltage Transmitter Input Low Voltage Input High Voltage Output Low Voltage Output Low Current Output Leakage Current Max. Units Measured from Pins 1 or 16 with Respect to Pin 2 Maximum Cable Loss Range Measured Between Pins 1 and 16 Percent of Peak Input Signal Amplitude Measured at Pin 2 Measured from Pins 1 or 16 with Respect to Pin 2 Difference Between Alarm-on and Alarm-off Levels Measured at Pins 5 or 12, I OUT = +1.6mA Measured at Pins 5 or 12, I OUT = -40µA Measured at Pin 3; I OUT = +1.6mA Measured at Pin 3; I OUT = -40µA 0.8 V +5µA Measured at Pin 15; I IN Min = -500µA, I IN Max = 0.8 V V V mA µA Measured at Pins 6, 11; I IN = -700µA Measured at Pins 6, 11; I IN = +5µA Measured at Pins 8, 10; I OUT = -40mA Measured at Pins 8, 10; V OUT = 1V Measured at Pins 8, 10; V OUT = 10V Outputs in off state Vp ns ns Pin 1, 16 with Respect to Pin 2 1 Pins 5, 12; C L = 15pF, 10% to 90% Pins 5, 12; C L =15pF, 90% to 10% 2.2 1.2 40 -100 1 Conditions 2.2 80 80 Notes: 1. Higher input voltages are possible if a resistive input attenuator is used. Bold face parameters are covered by production test and guaranteed over operating temperature range. Rev. 3.0.1 4 XRT6164A ELECTRICAL CHARACTERISTIC (CONT’D) Parameters Min. Typ. Max. Units Conditions AC Electrical Characteristics (Cont’d) Transmitter Output Rise Time 80 ns Pins 8, 10; R L = Output Fall Time 80 ns Pins 8, 10; R L = Rising Edge Delay 100 ns Pins 8, 10; R L = (I/P to O/P) Falling Edge Delay 100 ns Pins 8, 10; R L = (I/P to O/P) 130, C L = 15pF, 10% to 90% 130, C L = 15pF, 90% to 10% 130, C L = 15pF, 50% to 50% 130, C L = 15pF, 50% to 50% Notes: Bold face parameters are covered by production test and guaranteed over operating temperature range. Specifications are subject to change without notice ABSOLUTE MAXIMUM RATINGS Supply Voltage ......................................... 20V Storage Temperature .............. -65°C to +150°C Transpower Technologies, Inc. 24 Highway 28, Suite 202 Crystal Bay, NV 89402-0187 Tel. (702) 831-0140 Fax. (702) 831-3521 Magnetic Supplier Information: Pulse Telecom Product Group P.O. Box 12235 San Diego, CA 92112 Tel. (619) 674-8100 Fax. (619) 674-8262 Rev. 3.0.1 5 XRT6164A SYSTEMDESCRIPTION Since the receive data comparator bias voltage is stored during transmit mode, it is immediately available when receive mode resumes. The XRT6164A is a general purpose line interface chip that contains the receive and transmit circuitry necessary to convert TTL logic levels to a CMOS signal both to and from a twisted pair cable. Transmitter The XRT6164A transmitter section contains two matched open collector output drivers that are capable of driving the line transformer directly with a current up to 40mA. The transmitter output drivers include diode clamps to ensure non-saturating operation. Transmitter digital inputs, which are active-low, are TTL-compatible. External resistors are used between the transmitter outputs and the output transformer primary to set the output pulse amplitude. Receiver The XRT6164A receiver section converts a balanced CMOS signal that has been attenuated and distorted by up to 10dB of twisted pair cable to active-low TTLcompatible logic levels. The cable is transformer coupled to the receiver differential inputs (RX+IP, RX-IP) which are biased through the input transformer secondary winding by a voltage generated on-chip (I/P BIAS). The CMOS receive signal is applied to a peak detector, and to a pair of data comparators. The peak detector output voltage charges an external capacitor connected to PEAK CAP. This voltage generates a data comparator bias level that is approximately 50% of the peak input pulse amplitude. APPLICATION INFORMATION Figure 2 shows a general line driver application circuit using the XRT6164A. This device converts CMOS transmit and receive signals in the 64Kbps to 1.544Mbps range to active-low TTL-compatible logic levels. CMOS signals that have been attenuated and distorted by twisted pair cable are transformer-coupled to the line side of the XRT6164A as shown on the left side of Figure 2. Suggested transformers for both the input and output applications are the Pulse types PE65535 or TTI-7147 for 64Kbps use and the PE-65835 for 1.544Mbps applications. Thus, data slicing is automatically accomplished at the optimum level over the full cable loss range. TTLcompatible output stages buffer the receiver digital outputs (S+R, S-R) and provide active low signals corresponding to received positive and negative input pulses. Loss of input signal is detected by a comparator that monitors input signal level. An active-low TTL-compatible logic level (RX ALARM) indicates signal loss. Comparator hysteresis prevents chatter on this output. Ping-pong operation is made possible by the time compression multiplex control input (TCM CON). A logic 0 applied to this pin during transmission stores the peak detector output voltage by disconnecting the peak detector storage capacitor charge and discharge paths. The right side of Figure 2 shows the TTL-compatible digital inputs and outputs. Please refer to the pin description section of this data sheet for detailed information about each signal. Rev. 3.0.1 6 XRT6164A XRT6164A Figure 2. XRT6164A Line Driver Application Rev. 3.0.1 7 XRT6164A 16 LEAD PLASTIC DUAL-IN-LINE (300 MIL PDIP) Rev. 1.00 INCHES SYMBOL A A1 A2 B B1 C D E E1 e eA eB L α MAX MILLIMETERS MIN MAX 0.145 0.210 0.015 0.070 0.115 0.195 0.014 0.024 0.030 0.070 0.008 0.014 0.745 0.840 0.300 0.325 0.240 0.280 0.100 BSC 0.300 BSC 0.310 0.430 0.115 0.160 0° 15° 3.68 5.33 0.38 1.78 2.92 4.95 0.36 0.56 0.76 1.78 0.20 0.38 18.92 21.34 7.62 8.26 6.10 7.11 2.54 BSC 7.62 BSC 7.87 10.92 2.92 4.06 0° 15° MIN Note: The control dimension is the inch column Rev. 3.0.1 8 XRT6164A 16 LEAD SMALL OUTLINE (300 MIL JEDEC SOIC) Rev. 1.00 INCHES SYMBOL A A1 B C D E e H L α MAX MILLIMETERS MIN MAX 0.093 0.104 0.004 0.012 0.013 0.020 0.009 0.013 0.398 0.413 0.291 0.299 0.050 BSC 0.394 0.419 0.016 0.050 2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 10.10 10.50 7.40 7.60 1.27 BSC 10.00 10.65 0.40 1.27 MIN 0° 8° 0° Note: The control dimension is the millimeter column Rev. 3.0.1 9 8° XRT6164A NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2007 EXAR Corporation Datasheet October 2007 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. Rev. 3.0.1 10