XRT6165CDTR-F

XR-T6165 ...the analog plus company TM Codirectional Digital Data Processor Dec 2010 FEATURES APPLICATIONS
Low Power CMOS Technology
CCITT G.703 Compliant 64kbps Codirectional Interface
All Receiver and Transmitter Inputs and Outputs are TTL Compatible
Performs the Digital and Analog Functions for a Complete 64kbps Data Adaption Unit (DAU) When Used With the XR-T6164
Transmitter Inhibits Bipolar Violation Insertion for Transmission of Alarm Conditions
Alarm Output Indicates Loss of Received Bipolar Violations
Up to 125µs Variance of Data Transfer Timing in Both Transmit and Receive Paths Allows Operation in Plesiochronous Networks
Both Receiver and Transmitter Perform Byte Insertion or Deletion in Response to Local Clock Slips GENERAL DESCRIPTION The XR-T6165 is a CMOS device which contains the digital circuitry necessary to interface both directions of a 64kbps data stream to 2.048Mbps transmit and receive PCM time-slots. The XR-T6165 and the companion XR-T6164 line interface chip together form a CCITT G.703 compliant 64kbps codirectional interface. sections. The transmitter transforms 8 bit serial data from a 2.048Mbps time-slot into an encoded 64kbps data stream. The receiver , which performs the reverse operation, decodes the 64kbps data, extracts a clock signal, and then outputs the data to a 2.048Mbps time-slot. The XR-T6165 provides features which allow the repetitions and deletions of both received and transmitted data as clock skews and transients occur. The XR-T6165 contains separate transmit and receive ORDERING INFORMATION Part No. Package Operating Temperature Range XR-T6165CD 24 Lead 300 Mil JEDEC SOIC 0°C to +70°C XR-T6165ID 24 Lead 300 Mil JEDEC SOIC –40°C to +85°C Rev. 2.04 3121 EXAR Corporation, 48720 Kato Road, Fremont, CA 94538  (510) 668-7000  (510) 668-7010 1 XR-T6165 PCMIN 15 TX2MHz 16 TS1T 8 TS2T 9 TTSEL 12 (17)1 D (18)1 8 Bit Input Register CLK 8 Bit Latch Time Slot Mux LOAD 14 ALARMIN 13 Byte Insertion 8 (14)1 CLK 8 Bit Output Register LOAD TX256kHz Byte Deletion 8 Q Control Circuitry (16)1 Octet Counter Violation Insertion Coding Logic (15)1 Note 1 Number in brackets are for SOIC package D CLK Q 10 T+R D CLK Q 11 T-R Figure 1. XR-T6165 Transmit Section Block Diagram S+R 1 S-R 2 BLS 3 RX2MHz 4 TS1R 18 TS2R 19 RTSEL 20 BLANK 5 RXCK2MHz 7 Byte Sync Detection CLK Violation Loss Alarm (24)1 22 ALARM Data Decoder CLK Register Select Logic (20)1 (21)1 (22)1 Time Slot Mux D Q D Q 8 Bit Reg 0 CLK 8 Bit Reg 1 CLK REG 0 SEL REG 1 SEL Time Slot 128kHz Recovered CLK Clock Recovery Note 1 Number in brackets are for SOIC package Figure 2. XR-T6165 Receiver Section Block Diagram Rev. 2.02 2 (23)1 21 PCMOUT XR-T6165 PIN CONFIGURATION S+R S-R BLS RX2MHz BLANK VDD RXCK2MHz TS1T TS2T T+R T-R NC 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 ALARM PCMOUT RTSEL TS2R TS1R VSS TX2MHz PCMIN TX256kHz ALARMIN TTSEL NC 24 Lead SOIC (JEDEC, 0.300”) PIN DESCRIPTION ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ DIP Pin # SOIC Pin # Symbol Type Description 1 1 S+R I Positive AMI Data to Receiver. Positive data from the XR-T6164 receive-side. Active low. 2 2 S-R I Negative AMI Data to Receiver. Negative data from the XR-T6164 receive-side. Active low. 3 3 BLS I Byte Locking Supervision. When active, causes blanking of PCMOUT under received alarm conditions. Active low. 4 4 RX2MHz I Receiver 2.048MHz Clock. Used to clock out PCM data. 5 5 BLANK I PCMOUT Data Blanking. When active, forces PCMOUT data to all ones (AIS). Active high. 6 6 VDD 7 7 RXCK2MHz I 2.048MHz Clock. Used by receiver clock recovery circuit. 8 8 TS1T I Transmitter time-slot 1 Input. 9 9 TS2T I Transmitter time-slot 2 Input. 10 10 T+R O Transmit Positive AMI Data Output. Data to XR-T6164 positive transmitter input. Active low 11 11 T-R O Transmit Negative AMI Data Output. Data to XR-T6164 negative transmitter input. Active low. 12 NC No Connect. 13 NC No Connect. 12 14 TTSEL I Transmit time-slot Select. When high, TS1T is selected; when low, TS2T is selected. 13 15 ALARMIN I Alarm Input. When active, inhibits insertion of violations used for octet timing in transmitter output. Active high 14 16 TX256kHz I Transmitter 256kHz Clock. Used to output 64kbps encoded data. +5V +10% Power Source. Rev. 2.04 3 XR-T6165 PIN DESCRIPTION (CONT’D) ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ DIP Pin # SOIC Pin # Symbol Type Description 15 17 PCMIN I Transmit PCM Input. Data read from the system PCM bus. 16 18 TX2MHz I Transmitter 2.048MHz Clock. Clocks PCM data in PCMIN. 17 19 VSS 18 20 TS1R I Receiver time-slot 1 Input. 19 21 TS2R I Receiver time-slot 2 Input. 20 22 RTSEL I Receive time-slot Select. When high, TS1R is selected; when low, TS2R is selected. 21 23 PCMOUT O Received PCM Output Data. Data sent to the system PCM bus. 22 24 ALARM O Octet Timing Alarm. When active, indicates loss of received bipolar violations that are used for octet timing. Active high. Ground. Rev. 2.04 4 XR-T6165 ELECTRICAL CHARACTERISTICS Test Conditions: VDD = 5V + 10%, TA = 25°C, Unless Otherwise Specified Symbol Parameter Min. Typ. Max. Unit Conditions DC Electrical Characteristics VIH Logic 1 VIL Logic 0 VDD Supply IDD Supply Current IIL Input Leakage 2.4 V 4.5 V 5.5 V 500 VOL VOH 0.4 µA Dynamic Supply Current 1 µA 0.4 V At 1.6mA V At 0.4mA 20 ns All Outputs 2.4 AC Electrical Characteristics General tr, tf Output Rise/Fall Time Receiver tRS RX2MHz Rising Edge to TS Rising Edge Set Up Time 0 tRXL 100 ns Figure 3 tRH RX2MHz Rising Edge to TS Falling Edge Hold Time 0 tRXL 100 ns Figure 3 10 ns Figure 3 10 ns Figure 3 10 ns Figure 3 tDRS TS Rising Edge to Leading Edge of PCMOUT D0 Bit Delay tDRH TS Falling Edge to Trailing Edge of PCMOUT D7 Bit Hold Time tRXD RX2MHz Rising Edge to PCMOUT Bits D1 Through D6 Rising Edge Delay 0 tPW PCMOUT Pulse Width 488 ns Figure 3 tRXH RX2MHz High Time 244 ns Figure 3 tRXL RX2MHz Low Time 244 ns Figure 3 RX2MHz Period 488 ns +100ppm tRXCLK Transmitter tTS TS Rising Edge to TX2MHz Set Up Time 20 tTXL 100 ns Figure 4 tTH TS Falling Edge to TX2MHz Hold Time 0 tTXL 100 ns Figure 4 tDS PCMIN Edge to TX2MHz Set Up Time 100 ns Figure 4 tDH PCMIN Edge to TX2MHz Hold Time 100 ns Figure 4 tTXH TX2MHz High Time ns Figure 4 244 Rev. 2.04 5 XR-T6165 ELECTRICAL CHARACTERISTICS (CONT’D) Symbol Parameter Min. Typ. Max. Unit Conditions AC Electrical Characteristics (Cont’d) Transmitter (Cont’d) TX2MHz Low Time 244 ns Figure 4 TX2MHz Period 488 ns Figure 4 tKXH TX256kHz High Time 1.95 µs tKXL TX256kHz Low Time 1.95 µs 3.9063 µs tTXL tTXCLK tKXCLK TX256kHz Period Specifications are subject to change without notice ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . . -65 . °C to +150°C Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20V .. Operating Temperature . . . . . . . . . . . . . 0°C to +70°C Magnetic Supplier Information: Transpower Technologies, Inc. 24 Highway 28, Suite 202 Crystal Bay, NV 89402-0187 Tel. (702) 831-0140 Fax. (702) 831-3521 Pulse Telecom Product Group P.O. Box 12235 San Diego, CA 92112 Tel. (619)674-8100 Fax. (619)674-8262 Rev. 2.04 6 XR-T6165 tRS tRXCLK tRXH tRXL tRH RX2MHz tDRS tDRH time-slot tPW tRXD PCMOUT D0 D1 D2 D3 D4 D5 D6 D7 Figure 3. Receive Time-slot Timing tTS tTXH tTXL tTH tTXCLK TX2MHz time-slot tDS tDH PCMIN D0 D1 D2 D3 D4 D5 D6 D7 Figure 4. Transmit Time-slot Timing tKXCLK tKXH tKXL Tr Tf VIH 50% Clock VIH 50% VIL 50% VIL Figure 5. Clock Timing Rev. 2.04 7 XR-T6165 transmitter output as specified by CCITT G.703. Transmission of octet timing is performed by feeding the seventh and eighth data bits in each word to the same Transmitter transmitter output. This function may be inhibited by setting ALARMIN (pin 13) high to transmit an alarm Figure 1 shows the XR-T6165 transmitter section block condition. Should skew occur between the TX2MHz and diagram. The transmitter converts eight bit bursts or TX256kHz clocks signals, or during an adjustment of the octets of 2.048Mbps serial data present in a PCM timing of the time-slot signal, circuitry is included to delete time-slot to a coded continuous 64kbps data stream. or repeat complete words of data. This could happen, for During operation, data input is controlled by external clock and time-slot signals, and the 64kbps data output is example, when changing from one time-slot position to another. A byte repetition or insertion occurs once if no timed by an external 256kHz clock. Since the input and new PCM data is received. A byte repetition just occurs output rates may not be exactly equal because of slight once. If no new PCM data is received, the T+R and T-R clock rate dif ferences, periodic slips can occur . Therefore, circuitry is included to delete or repeat octets, if outputs stay high. A byte deletion occurs when the transmitter receives a new byte of data before the necessary. Transmitter operation is as follows. Pin previous byte is transferred from the storage latch to the numbers, refer to the DIP package. output register. Under this condition, the stored data is PCM data is applied to PCMIN (pin 15), a 2.048MHz local overwritten. clock is applied to TX2MHz (pin 16), and a time-slot signal Receiver is applied through the time-slot multiplexer . This multiplexer allows the transmitter to be hard wired totwo Figure 2 shows the block diagram of the XR-T6165 time-slot positions. A time-slot signal is applied to receiver section. The receiver converts coded multiplexer inputs TS1T (pin 8) or TS2T (pin 9), and a continuous 64kbps data to eight bit bursts of 2.048Mbps time-slot select logic level is applied to TTSEL (pin 12). A serial data suitable for insertion in a PCM time-slot. high level at TTSEL selects TS1T while a low level During operation, data input is timed by a clock that is enables TS2T. The time-slot is an envelope derived extracted from the input signal, while output is controlled externally from TX2MHz that covers eight clock pulses. by external locally supplied clock and time-slot signals. The rising edge of the time-slot signal should be made to Since the data input and output rates may not be exactly coincide with the falling edge of TX2MHz. Eight bits of equal, circuitry is included to delete or repeat eight bit data PCM data are clocked into the transmitter input register blocks, if necessary. Receiver operation is as follows. on the rising edge of TX2MHz while the selected time-slot A line interface chip such as the receive section of the signal is high. The input register data is then transferred XR-T6164 converts the encoded bipolar 64kbps signal to to a storage latch. dual-rail active-low logic levels. These signals are Transmission of 64kbps data is controlled by the 256kHz applied to the XR-T6165 receiver S+R (pin 1) and S-R local clock that is applied to TX256kHz (pin 14). It is not (pin 2) inputs. A 128kHz clock, which is derived from the necessary for this clock to be synchronized with any other received signal, is used to decode this data, and then to signals that are applied to the transmitter . The output clock it into one of two storage registers. T wo registers process begins by transferring data from the storage latch are used so that one may be receiving continuous data at to the output shift register after transmission of the 64kbps while the other is sending eight bit bursts at a previous eight bits of data is complete. Four periods of 2.048Mbps rate to PCMOUT (pin 21) while the receiver TX256kHz are required to encode each data bit. A “logic time-slot signal is high. The time-slot is an envelope 0” applied to PCMIN is coded as 0101 while a “logic 1” is derived externally from RX2MHz that covers eight clock coded as 0011. This data is output on either T+R (pin 10) pulses. The rising edge of the time-slot signal should be or T -R (pin 1 1) according to the AMI (alternate mark made to coincide with the rising edge of RX2MHz. Eight inversion) coding rule. Note that the T+R and-R T outputs bits of PCM data are clocked out of the receiver register as well as the corresponding XR-T6164 transmitterinputs on the rising edge of RX2MHz while the time-slot signal is (TX+I/P, TX-I/P) are all active-low. Therefore, a “logic 0” high. A two input multiplexer at the time-slot input allows is coded as a 1010 and a “logic 1” as a100 1 at the bipolar the receiver to be hard wired to two time-slot positions. SYSTEM DESCRIPTION Rev. 2.04 8 XR-T6165 Slip control logic is included in the receiver to accommodate rate differences between input and output data. The 64kbps input rate is determined by the remote transmitter, while the PCMOUT rate is set by RX2MHz which is a local clock. If thisclock is slow, an octet will be deleted periodically, while the last octet will be repeated under fast conditions. Octet timing is maintained during Recovery of the 128kHz timing signal is performed by a variable length counter which is clocked by the 2.048 MHz these operations. signal applied to RXCK2MHz (pin 7). This clock is not required to be synchronized with any other signals that are applied to the XR-T6165. However , the RX2MHz APPLICATION INFORMATION clock (pin 4) may also be used for this function. Positive input data transitions are used tosynchronize this counter with the data. If synchronization is lost, the counter length 64kbps Codirectional Interface is shortened, and the clock recovery circuit enters a seek mode until a transition is found. Figure 6 shows a codirectional interface circuit using the time-slot signals are applied to TS1R (pin 18) and TS2R (pin 19) and the active time-slot is selected by TSEL R (pin 20). A high level applied to RTSEL selects TS1R and a low level selects TS2R. Data appearing at PCMOUT is framed by the read time-slot signal and is guaranteed glitch free. Octet timing ensures that bit grouping is maintained when XR-T6165 with the XR-T6164 line interface. The the data is converted from a 64kbps continuous stream to XR-T6164 first converts the bipolar 64kbps transmit and eight bit 2.048Mbps bursts. Bipolar violations are used to receive signals to active-low TTL compatible data identify the last bit in each eight bit octet. In the absence of required by the XR-T6165. The XR-T6165 then performs these violations, for example when receiving a the digital functions that are necessary to interface this transmitted alarm condition (transmitter ALARMIN is 64kbps continuous data to a 2.048Mbps PCM time-slot. high), the circuit will continue to operate in The 64kbps signals that have been attenuated and synchronization with respect to the last received violation. distorted by the twisted pair cable are During this time, the data present at PCMOUT is still transformer-coupled to the line side of the XR-T6164 as correct as long as synchronization based on the last shown on the left side of Figure 6. A suggested received violation is still valid, and the BLS input (pin 3) is transformer for both the input and output applications is held high. However , if BLS is low and an octet timing the pulse type PE-65535. violation is not received, receiver output data is blanked by forcing PCMOUT to a high level. Also, if eight The right side ofFigure 6 shows the XR-T6164 LOS (Loss successive octet timing violations are not received, the of Signal) output and the XR-T6165 digital inputs and ALARM output (pin 22) goes to a high level. A high level outputs. All of these pins are TTL compatible. Please applied to the BLANK input (pin 5) will also force refer to the pin description section of this data sheet for PCMOUT to an all-ones state. detailed information about each signal. Rev. 2.04 9 XR-T6165 T6164 LOS Output +5V +5V XR-T6165 6 0.1µF 0.1µF VDD ALARM 0.1µF 64kbps Data from Line TIP 9 13 16 1:2 480 1 RING PE-65535 TTI-17147 TIP RX+I/P 2 RING PE-65535 TTI-17147 V D A C C C C RX-I/P T C M C O N 3 R X A L A R M S+R 12 5 S-R 1 S+R 2 S-R I/P BIAS 14 PEAK CAP 0.1µF 64kbs Data +5V to Line 1:2 V 15 0.1µF 300 300 0.1µF 22 21 PCMOUT 3 BLS Receive RX2MHz 4 Side 18 TS1R 19 TS2R 20 RTSEL 5 BLANK 7 RXCK2MHz Loss of TX Sync Data to PCM BUS Blank O/P for Alarm 2.048MHz Clock time-slot 1 time-slot 2 time-slot Select Forces all Ones 2.048MHz Clock XR-T6164 10 TX+O/P 8 TX-O/P TX+I/P G N D A G N D D 4 TX-I/P 11 6 10 11 PCMIN T+R T-R Transmit Side TX2MHz TS1T TS2T TTSEL 7 17 VSS TX256kHz ALARMIN Figure 6. Typical Codirectional Application Circuit Rev. 2.04 10 15 16 8 9 12 14 13 Data from PCM BUS 2.048MHz Clock time-slot 1 time-slot 2 time-slot Select 256kHz Clock Inhibit Violations XR-T6165 Transmitter Code Conversion Figure 7 shows the transmitter code conversion process that CCITT G.703 specifies for a 64kbps codirectional interface. Step 3 - A binary 0 is coded as a 1010. Step 4 - The binary signal is converted into a three-level signal by alternating the polarity of consecutive blocks. Step 1 - A 64kbps bit period is divided into four unit intervals. Step 5 - The alternation in polarity of the blocks is violated every eighth block. The violation block marks the last bit in an octet. Step 2 - A binary 1 is coded as a 1100. Bit Number 7 8 1 2 3 4 5 6 7 8 1 64kbps data 1 0 0 1 0 0 1 1 1 0 1 Steps 1-3 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Step 4 Step 5 Violation Violation Octet Timing Figure 7. Transmitter Code Conversion for a 64kbps Bipolar Line Signal Rev. 2.04 11 XR-T6165 pulses respectively of either polarity. Note that this mask is for the pulse measured at the XR-T6164 transmitter Figure 6) when output (application circuit shown in terminated with a 120Ω resistor. Codirectional Interface Pulse Masks 2.0 Î Î Î Î Î Î Î Î 3.12µs (3.9 -0.78) 3.51µs (3.9 -0.39) 3.9µs 0.1 0.1 0.5 2.0 V 1.0 0.10.1 Figure 8 and Figure 9 show the CCITT G.703 64kbps codirectional interface pulse masks for single and double 0 4.29µs (3.9 + 0.39) 6.5µs (3.9 + 2.6) 7.8µs (3.9 + 3.9) 0 0.1 0.1 0.5 Î Î Î Î Î Î Î Î 7.02µs (7.8 - 0.78) 7.41µs (7.8 - 0.39) 7.8µs 0.2 0.2 0.2 V 1.0 0.10.1 Figure 8. Mask for a Single Pulse 8.19µs (7.8 + 0.39) 10.4µs (7.8 + 2.6) 11.7µs (7.8 + 3.9) Figure 9. Mask for Double Pulse Rev. 2.04 12 XR-T6165 24 LEAD SMALL OUTLINE (300 MIL JEDEC SOIC) D 24 13 E H 12 C A Seating Plane e B A1 L INCHES SYMBOL MILLIMETERS MIN MAX MIN A 0.093 0.104 2.35 2.65 A1 0.004 0.012 0.10 0.30 B 0.013 0.020 0.33 0.51 C 0.009 0.013 0.23 0.32 D 0.598 0.614 15.20 15.60 E 0.291 0.299 7.40 7.60 e 0.050 BSC MAX 1.27 BSC H 0.394 0.419 10.00 10.65 L 0.016 0.050 0.40 1.27 Rev. 2.04 14 XR-T6165 Notes Rev. 2.04 15 XR-T6165 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 3121 EXAR Corporation Datasheet EFD 3121 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. Rev. 2.04 16