XRT6166ID-F

XR-T6166 ...the analog plus company TM Codirectional Digital Data Processor Dec 2010 APPLICATIONS FEATURES
CCITT G.703 Compliant 64kbps Codirectional Interface
Low Power CMOS Technology
All Receiver and Transmitter Inputs and Outputs are TTL Compatible
Transmitter Inhibits Bipolar Violation Insertion for Transmission of Alarm Conditions
Alarm Output Indicates Loss of Received Bipolar Violations
Tolerance of 125µs Variance of Data Transfer Timing in Both Transmit and Receive Paths Allows Operation in Plesiochronous Networks
Both Receiver and Transmitter Perform Byte Insertion or Deletion in Response to Local Clock Slips and Provide Outputs Indicating Slip Logic Activity
Performs the Digital and Analog Functions for a Complete 64kbps Data Adaption Unit (DAU) When Used With the XR-T6164 GENERAL DESCRIPTION stream. The receiver , which performs the reverse operation, decodes the 64kbps data, extracts a clock signal, and then outputs the data to a 2.048Mbps time-slot. The XR-T6166 provides features which allow the repetitions and deletions of both received and transmitted data as clock skews and transients occur . These slip occurrences are indicated by byte insertion and deletion flags. Outputs are also provided for The XR-T6166 contains separate transmit and receive sections. The transmitter transforms 8 bit serial data from extracted receive clock and clock recovery circuit loss of lock. a 2.048Mbps time-slot into an encoded 64kbps data The XR-T6166 is a CMOS device which contains the digital circuitry necessary to interface both directions of a 64kbps data stream to 2.048Mbps transmit and receive PCM time-slots. The XR-T6166 and the companion XR-T6164 line interface chip together form a CCITT G.703 compliant 64kbps codirectional interface. ORDERING INFORMATION Part No. XR-T6166CD XR-T6166ID Package 28 Lead 300 Mil JEDEC SOIC 28 Lead 300 Mil JEDEC SOIC Operating Temperature Range 0°C to +70°C –40°C to 85°C Rev. 2.03 2010 EXAR Corporation, 48720 Kato Road, Fremont, CA 94538  (510) 668-7000  (510) 668-7010 1 XR-T6166 PCMIN 19 D TX2MHz 20 TS1T 10 TS2T 12 TTSEL 15 8 Bit Input Register CLK Byte Deletion 8 11 BDT 18 BIT D CLK Q 13 T+R D CLK Q 14 T-R 8 Bit Latch time-slot Mux Load Byte Insertion 8 CLK 8 Bit Output Register Load Q Control Circuitry TX256kHz 17 ALARMIN Octet Counter Violation Insertion Coding Logic 16 Figure 1. XR-T6166 Transmitter Section Block Diagram Byte Sync Detection CLK S+R 2 S-R 3 BLS 4 RX2MHz 5 TS1R 23 Violation Loss Alarm 24 RTSEL 27 BLANK 6 time-slot Mux Register Select Logic Time Slot Mux 8 Bit Reg 0 CLK Q Q 8 Bit Reg 1 CLK REG 0 SEL REG 1 SEL time-slot 28 PCMOUT Byte Insertion 26 BIR Byte Deletion 25 BDR D 128kHz Recovered Clock RXCK2MHz 9 ALARM Data Decoder CLK D TS2R 1 Clock Recovery 7 22 Figure 2. XR-T6166 Receiver Section Block Diagram Rev. 2.03 2 RXCKOUT CS XR-T6166 PIN CONFIGURATION ALARM S+R S-R BLS RX2MHz BLANK RXCKOUT VDD RXCK2MHz TS1T BDT TS2T T+R T-R 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 PCMOUT RTSEL BIR BDR TS2R TS1R CS VSS TX2MHz PCMIN BIT TX256kHz ALARMIN TTSEL 28 Lead SOIC (Jedec, 0.300”) PIN DESCRIPTION Pin # Symbol Type Description 1 ALARM O Octet Timing Alarm. When active, indicates loss of received bipolar violations that are used for octet timing. Active high. 2 S+R I Positive AMI Data to Receiver. Positive data from the XR-T6164 receive-side. Active low. 3 S-R I Negative AMI Data to Receiver. Negative data from the XR-T6164 receive-side. Active low. 4 BLS I Byte Locking Supervision. When active, causes blanking of PCMOUT under received alarm conditions. Active low. 5 RX2MHz I Receiver 2.048MHz Clock. Used to clock out PCM data. 6 BLANK I PCMOUT Data Blanking. When active, forces PCMOUT data to all ones (AIS). Active high. 7 RXCKOUT O 128kHz Extracted Clock. Clock recovered from received data. 8 VDD 9 RXCK2MHz I 2.048MHz Clock. Used by receiver clock recovery circuit. 10 TS1T I Transmitter Time-slot 1 Input. 11 BDT O Transmitter Byte Deletion Flag. Active when a transmit byte is deleted. Active high. 12 TS2T I Transmitter Time-slot 2 Input. 13 T+R O Transmit Positive AMI Data Output. Data to XR-T6164 positive transmitter input. Active low. 14 T-R O Transmit Negative AMI Data Output. Data to XR-T6164 negative transmitter input. Active low. 15 TTSEL I Transmit Time-slot Select. When high, pin 10 is selected; when low, pin 12 is selected. 16 ALARMIN I Alarm Input. When active, inhibits insertion of violations used for octet timing in transmitter output. Active high. +5V
10% Power Source. Rev. 2.03 3 XR-T6166 PIN DESCRIPTION (CONT’D) Pin # Symbol Type Description 17 TX256kHz I Transmitter 256kHz Clock. Used to output 64kbps encoded data. 18 BIT O Transmitter Byte Insertion Flag. Active when a transmit byte is repeated. Active high. 19 PCMIN I Transmitter PCM Input. Data read from the system PCM bus. 20 TX2MHz I Transmitter 2.048MHz Clock. Clocks PCM data in PCMIN. 21 VSS 22 CS O Clock Seek. Indicates that clock recovery circuit has loss of lock with received data. Active high. 23 TS1R I Receiver Time-slot 1 Input. 24 TS2R I Receiver Time-slot 2 Input. 25 BDR O Receiver Byte Deletion Flag. Active when received data byte is deleted. Active high. 26 BIR O Receiver Byte Insertion Flag. Active when a received data byte is repeated. Active high. 27 RTSEL I Receive Time-slot Select. When high, pin 23 is selected; when low, pin 24 is selected. 28 PCMOUT O Received PCM Output Data. Data sent to the system PCM bus. Ground. Rev. 2.03 4 XR-T6166 ELECTRICAL CHARACTERISTICS Test Conditions: VDD = 5V
10%, TA = 25°C, Unless Otherwise Specified Symbol Parameter Min. Typ. Max. Unit Conditions DC Electrical Characteristics VIH Logic 1 VIL Logic 0 VDD Supply IDD Supply Current IIL Input Leakage 2.4 V 4.5 V 5.5 V µA 500 VOL VOH 0.4 Dynamic Supply Current 1 µA 0.4 V At 1.6mA mA At 0.4mA 20 ns All Outputs 2.4 AC Electrical Characteristics General tr, tf Output Rise/Fall Time Receiver tRS RX2MHz Rising Edge to TS Rising Edge Set Up Time 0 tRXL100 ns Figure 3 tRH RX2MHz Rising Edge to TS Falling Edge Hold Time 0 tRXL100 ns Figure 3 10 ns Figure 3 10 ns Figure 3 10 ns Figure 3 tDRS TS Rising Edge to Leading Edge of PCMOUT D0 Bit Delay tDRH TS Falling Edge to Trailing Edge of PCMOUT D7 Bit Hold Time tRXD RX2MHz Rising Egde to PCMOUT Bits D1 Through D6 Rising Edge Delay tPW PCMOUT Pulse Width 488 ns Figure 3 tRXH RX2MHz High Time 244 ns Figure 3 tRXL RX2MHz Low Time 244 ns Figure 3 RX2MHz Period 488 ns
100ppm tRXCLK 0 Transmitter tTS TS Rising Edge to TX2MHz Set Up Time 20 tTXL100 ns Figure 5 tTH TS Falling Edge to TX2MHz Hold Time 0 tTXL100 ns Figure 5 tDS PCMIN Edge to TX2MHz Set Up Time 100 ns Figure 5 tDH PCMIN Edge to TX2MHz Hold Time 100 ns Figure 5 tTXH TX2MHz High Time 244 ns Figure 5 tTXL TX2MHz Low Time 244 ns Figure 5 TX2MHz Period 488 ns
100ppm tTXCLK Rev. 2.03 5 XR-T6166 ELECTRICAL CHARACTERISTICS (CONT’D) Symbol Parameter Min. Typ. Max. Unit Conditions AC Electrical Characteristics (Cont’d) Transmitter (Cont’d) tKXH TX256kHz High Time 1.95 µs tKXL TX256kHz Low Time 1.95 µs 3.9063 µs tKXCLK TX256kHz Period tBDTH BDT High Time 488 ns tBITH BIT High Time 12.5 µs tALH ALARMIN High Time 15.6 µs Specifications are subject to change without notice ABSOLUTE MAXIMUM RATINGS Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V ... Operating Temperature . . . . . . . . . . . . .0°C to +70°C Storage Temperature . . . . . . . . . . . . -65°C to +150°C Magnetic Supplier Information: Transpower Technologies, Inc. 24 Highway 28, Suite 202 Crystal Bay, NV 89402-0187 Tel. (702) 831-0140 Fax. (702) 831-3521 Pulse Telecom Product Group P.O. Box 12235 San Diego, CA 92112 Tel. (619) 674-8100 Fax. (619) 674-8262 Rev. 2.03 6 XR-T6166 tRS tRXL tRXH tRXCLK tRH RX2MHz tDRS tDRH time-slot tPW tRXD PCMOUT D0 D1 D2 D3 D4 D5 D6 D7 Figure 3. Receive Time-slot Timing tRCKS S+R S-R tRCKP RXCKOUT Figure 4. Extracted Clock Timing tTS tTXH tTXL tTH tTXCLK TX2MHz time-slot tDS tDH PCMIN D0 D1 D2 D3 D4 D5 D6 D7 Figure 5. Transmit Time-slot Timing tKXCLK tKXH tKXL Tr Tf VIH 50% Clock VIL VIH 50% 50% VIL Figure 6. Clock Timing Rev. 2.03 7 XR-T6166 seventh and eighth data bits in each word to the same transmitter output. This function may be inhibited by setting ALARMIN (pin 16) high to transmit an alarm condition. SYSTEM DESCRIPTION Transmitter Should skew occur between the TX2MHz and TX256kHz clocks signals, or during an adjustment of the timing of the time-slot signal, circuitry is included to delete or repeat complete words of data. This could happen, for example, when changing from one time-slot position to another . Outputs are provided to indicate when a data byte is inserted or deleted. A byte repetition or insertion occurs once if no new PCM data is received. The BIT flag (pin 18) is active during the transmission of inserted data. A byte repetition just occurs once. If no new PCM data is received, the T+R and T -R outputs stay high. A byte deletion occurs when the transmitter receives a new byte PCM data is applied to PCMIN (pin 19), a 2.048MHz local of data before the previous byte is transferred from the clock is applied to TX2MHz (pin 20), and a time-slot signal storage latch to the output register. Under this condition, is applied through the time-slot multiplexer . This the stored data is overwritten and the BDT flag (pin 1) is multiplexer allows the transmitter to be hard wired totwo active. time-slot positions. A time-slot signal is applied to multiplexer inputs TS1T (pin 10) or TS2T (pin 12), and a Receiver time-slot select logic level is applied to TTSEL (pin 15). A high level at TTSEL selects TS1T while a low level Figure 2 shows the block diagram of the XR-T6166 enables TS2T. The time-slot is an envelope derived receiver section. The receiver converts coded continuous externally from TX2MHz that covers eight clock pulses. 64kbps data to eight bit bursts of 2.048Mbps serial data The rising edge of the time-slot signal should be made to suitable for insertion in a PCM time-slot. During coincide with the falling edge of TX2MHz. Eight bits of operation, data input is timed by a clock that is extracted PCM data are clocked into the transmitter input register from the input signal, while output is controlled by external on the rising edge of TX2MHz while the selected time-slot locally supplied clock and time-slot signals. Since the signal is high. The input register data is then transferred data input and output rates may not be exactly equal, to a storage latch. circuitry is included to delete or repeat eight bit data Transmission of 64kbps data is controlled by the 256kHz blocks, if necessary. Receiver operation is as follows. Figure 1 shows the XR-T6166 transmitter section block diagram. The transmitter converts eight bit bursts or octets of 2.048Mbps serial data present in a PCM time-slot to a coded continuous 64kbps data stream. During operation, data input is controlled by external clock and time-slot signals, and the 64kbps data output is timed by an external 256kHz clock. Since the input and output rates may not be exactly equal because of slight clock rate dif ferences, periodic slips can occur . Therefore, circuitry is included to delete or repeat octets, if necessary. Transmitter operation is as follows. local clock that is applied to TX256kHz (pin 17). It is not necessary for this clock to be synchronized with any other signals that are applied to the transmitter . The output process begins by transferring data from the storage latch to the output shift register after transmission of the previous eight bits of data is complete. Four periods of TX256kHz are required to encode each data bit. A “logic 0” applied to PCMIN is coded as 0101 while a “logic 1” is coded as 0011. This data is output on either T+R (pin 13) or T -R (pin 14) according to the AMI (alternate mark inversion) coding rule. Note that the T+R and-R T outputs as well as the corresponding XR-T6164 transmitterinputs (TX+I/P, TX-I/P) are all active-low . Therefore, a “logic 0” is coded as a 1010 and a “logic 1” as a 1100 at the bipolar transmitter output as specified by CCITT G.703. Transmission of octet timing is performed by feeding the Rev. 2.03 8 A line interface chip such as the receive section of the XR-T6164 converts the encoded bipolar 64kbps signal to dual-rail active-low logic levels. These signals are applied to the XR-T6166 receiver S+R (pin 2) and S-R (pin 3) inputs. A 128kHz clock, which is derived from the received signal, is used to decode this data, and then to clock it into one of two storage registers. T wo registers are used so that one may be receiving continuous data at 64kbps while the other is sending eight bit bursts at a 2.048Mbps rate to PCMOUT (pin 28) while the receiver time-slot signal is high. The time-slot is an envelope derived externally from RX2MHz (pin 5) that covers eight clock pulses. The rising edge of the time-slot signal should be made to coincide with the rising edge of RX2MHz. Eight bits of PCM data are clocked out of the receiver register on the rising edge of RX2MHz while the XR-T6166 time-slot signal is high. A two input multiplexer at the time-slot input allows the receiver to be hard wired to two time-slot positions. time-slot signals are applied to TS1R (pin 23) and TS2R (pin 24) and the active time-slot is selected by R TSEL (pin 27). A high level applied to RTSEL selects TS1R and a low level selects TS2R. Data appearing at PCMOUT is framed by the read time-slot signal and is guaranteed glitch free. Recovery of the 128kHz timing signal is performed by a variable length counter which is clocked by the 2.048MHz signal applied to RXCK2MHz (pin 9). This clock is not required to be synchronized with any other signals that are applied to the XR-T6166. However , the RX2MHz clock may also be used for this function. Positive input data transitions are used to synchronize this counter with the data. If synchronization is lost, the counter length is shortened, and the clock recovery circuit enters a seek mode until a transition is found. This mode is identified by a high level at the CS output (pin 22). The extracted 128kHz signal is available at RXCKOUT (pin 7). applied to the BLANK input (pin 6) will also force PCMOUT to an all-ones state. Slip control logic is included in the receiver to accommodate rate differences between input and output data. The 64kbps input rate is determined by the remote transmitter, while the PCMOUT rate is set by RX2MHz which is a local clock. If thisclock is slow, an octet will be deleted periodically, while the last octet will be repeated under fast conditions. Octet timing is maintained during these operations. Outputs are provided to indicate when an octet is inserted or deleted. The BIR flag (pin 26) is high when PCMOUT data is repeated, and the BDR flag (pin 25) is high when the receiver deletes an octet. APPLICATION INFORMATION 64kbps Codirectional Interface Figure 7 shows a codirectional interface circuit using the XR-T6166 with the XR-T6164 line interface. The Octet timing ensures that bit grouping is maintained when XR-T6164 first converts the bipolar 64kbps transmit and the data is converted from a 64kbps continuous stream to receive signals to active-low TTL compatible data eight bit 2.048Mbps bursts. Bipolar violations are used to required by the XR-T6166. The XR-T6166 then performs identify the last bit in each eight bit octet. In the absence of the digital functions that are necessary to interface this 64kbps continuous data to a 2.048Mbps PCM time-slot. these violations, for example when receiving a The 64kbps signals that have been attenuated and transmitted alarm condition (transmitter ALARMIN is distorted by the twisted pair cable are high), the circuit will continue to operate in synchronization with respect to the last received violation. transformer-coupled to the line side of the XR-T6164 as shown on the left side of Figure 7. A suggested During this time, the data present at PCMOUT is still transformer for both the input and output applications is correct as long as synchronization based on the last the pulse type PE-65535. received violation is still valid, and the BLS input (pin 4) is The right side ofFigure 7 shows the XR-T6164 LOS (Loss of Signal) output and the XR-T6166 digital inputs and outputs. All of these pins are TTL compatible. Please refer to the Pin Description section of this data sheet for detailed information about each signal. held high. However , if BLS is low and an octet timing violation is not received, receiver output data is blanked by forcing PCMOUT to a high level. Also, if eight successive octet timing violations are not received, the ALARM output (pin 1) goes to a high level. A high level Rev. 2.03 9 XR-T6166 T6164 LOS Output +5V +5V XR-T6166 8 0.1µF 0.1µF TIP 16 1:2 RX+I/P 480 1 RING 2 PE-65535 0.1µF TTI-17147 64kbps Data To Line TIP 14 RX-I/P PCMOUT VDD BIR BDR RXCKOUT 0.1µF 64kbps Data To Line 9 V 13 15 V T C C C C C M D A C O N 3 R 12 X S+R A L 5 A R S-R M CS Receive Side 2 3 BLS RX2MHz S+R TS1R TS2R S-R RTSEL I/P BIAS BLANK PEAK CAP 0.1µF RXCK2MHz XR-T6164 BDT +5V 1:2 RING PE-65535 TTI-17147 ALARM 300 300 0.1µF 10 8 TX+O/P TX-O/P TX+I/P G N D D G N D A 4 TX-I/P 11 6 13 14 BIT T+R T-R Transmit Side PCMIN TX2MHz TS1T TS2T 7 21 VSS TTSEL TX256kHz ALARMIN Figure 7. Typical Codirectional Application Circuit Rev. 2.03 10 1 28 26 25 7 22 4 5 23 24 27 6 9 11 18 19 20 10 12 15 17 16 Loss of TX Sync Data to PCM Bus Byte Repeat Flag Byte Delete Flag Recovered CLK CLK Seek Flag Blank O/P for Alarm 2.048MHz Clock time-slot 1 time-slot 2 time-slot Select Forces All Ones 2.048MHz Clock Byte Delete Flag Byte Insert Flag Data from PCM Bus 2.048MHz Clock time-slot 1 time-slot 2 time-slot Select 256kHz Clock Inhibit Violations XR-T6166 Step 2 - A binary 1 is coded as a 1100. Transmitter Code Conversion Step 3 - A binary 0 is coded as a 1010. Figure 8 shows the transmitter code conversion process that CCITT G.703 specifies for a 64kbps codirectional interface. Step 4 - The binary signal is converted into a three-level signal by alternating the polarity of consecutive blocks. Step 5 - The alternation in polarity of the blocks is violated every eighth block. The violation block marks the last bit in an octet. Step 1 - A 64kbps bit period is divided into four unit intervals. Bit Number 7 8 1 2 3 4 5 6 7 8 1 64kbps data 1 0 0 1 0 0 1 1 1 0 1 Steps 1-3 ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ Step 4 Step 5 Violation Violation Octel Timing Figure 8. Transmitter Code Conversion for a 64kbps Bipolar Line Signal Rev. 2.03 11 XR-T6166 Codirectional Interface Pulse Masks 0.1 0.1 0.5 0 Ì Ì Ì Ì Ì Ì Ì Ì is for the pulse measured at the XR-T6164 transmitter Figure 5) when output (application circuit shown in terminated with a 120Ω resistor. 3.12µs (3.9 -0.78) 3.51µs (3.9 -0.39) 3.9µs 0.2 2.0 2.0 V 1.0 0.1 0.1 Figure 9 and Figure 10 show the CCITT G.703 64kbps codirectional interface pulse masks for single and double pulses respectively of either polarity. Note that this mask 4.29µs (3.9 + 0.39) 6.5µs (3.9 + 2.6) 7.8µs (3.9 + 3.9) 0 0.1 0.1 0.5 ÌÌ Ì ÌÌ Ì ÌÌ 7.02µs (7.8 - 0.78) 7.41µs (7.8 - 0.39) 7.8µs 0.2 2.0 2.0 V 1.0 0.1 0.1 Figure 9. Mask for a Single Pulse 8.19µs (7.8 + 0.39) 10.4µs (7.8 + 2.6) 11.7µs (7.8 + 3.9) Figure 10. Mask for a Double Pulse Rev. 2.03 12 XR-T6166 28 LEAD SMALL OUTLINE (300 MIL JEDEC SOIC) D 28 15 E H 14 C A Seating Plane B e A1 L INCHES SYMBOL MILLIMETERS MIN MAX MIN A 0.093 0.104 2.35 2.65 A1 0.004 0.012 0.10 0.30 B 0.013 0.020 0.33 0.51 C 0.009 0.013 0.23 0.32 D 0.697 0.713 17.70 18.10 E 0.291 0.299 7.40 7.60 e 0.050 BSC MAX 1.27 BSC H 0.394 0.419 10.00 10.65 L 0.016 0.050 0.40 1.27 Rev. 2.03 13 XR-T6166 Notes Rev. 2.03 14 XR-T6166 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contains herein are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2010 EXAR Corporation Datasheet December 2010 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. Rev. 2.03 15