áç
XRT71D04
4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
APRIL 2001
REV. 1.1.1
GENERAL DESCRIPTION
The XRT71D04 is a four channel, single chip Jitter Attenuator, that meets the Jitter transfer characteristic
requirements specified in the ETSI TBR-24, Bellcore
GR-499 and GR-253 standards.
In addition, the XRT71D04 also meets the Jitter and
Wander specifications described in the ANSI
T1.105.03b 1997, Bellcore GR-253 and GR-499 standards for Desynchronizing and Pointer adjustments in
the DS3 to STS-SPE mapping applications.
• Meets output jitter requirement as specified by
ETSI TBR24
• Meets the Jitter and Wander specifications
described in T1.105.03b,GR-253 and GR-499 standards
• Selectable buffer size of 16 and 32 bits
• Jitter attenuator can be disabled
• Available in a 80 pin TQFP package
• Single 3.3V or 5.0V supply.
• Operates over - 400 C to 850 C temperature range.
FEATURES
• Meets the E3/DS3/STS-1 jitter requirements
APPLICATIONS
• E3/DS3 Access Equipment
• No external components required
• Compliant with jitter transfer template outlined in
ITU G.751, G.752, G.755, GR-499-CORE,1995
GR-253-CORE standards
• STS-SPE to DS3 Mapper
• DSLAMs
FIGURE 1. BLOCK DIAGRAM (ONE CHANNEL)
MCLK_n
Timing Control Block /
Phase locked Loop
STS1_n
ICT
DS3/E3_n
DJA_n
Write Clock
RClk_n
RClkES
RPOS_n
RNEG_n
FSS
RRCLK_n
Read Clock
RRPOS_n
16/32 Bit FIFO
RRNEG_n
FL_n
Channel 0
Channel 1
Channel 2
MODE_CTRL
Channel 3
HOST
Microprocessor Serial
Interface
Reset
XRT71D04
n = 0, 1, 2, 3
CS
SDI
SDO SClk
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
XRT71D04
4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
áç
REV. 1.1.1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
AVDD
NC
GND
RRCLK_1
RRPOS_1
RRNEG_1
NC
RCLKES
NC
VDD
DS3/E3_2
SDO
FSS
NC
RRNEG_2
RRPOS_2
RRCLK_2
GND
NC
AVDD
FIGURE 2. PIN OUT OF THE XRT71D04
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
XRT71D04
AGND
FL_2
STS1_2
DJA_2/CS
MCLK_2
GND
RCLK_2
RPOS_3
RNEG_3
VDD
RNEG_2
RPOS_2
RCLK_3
GND
MCLK_3
DJA_0/SCLK
DS3/E3_0
STS1_0
FL_0
AGND
AVDD
NC
GND
RRCLK_0
RRPOS_0
RRNEG_0
RRCLKES
NC
Reset
DS3/E3_1
VDD
MODE_CTRL
ICT
HOST
FLRST
RRNEG_3
RRPOS_3
RRCLK_3
GND
AVDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
AGND
FL_1
STS1_1
DS3/E3_3
DJA_3
MCLK_1
GND
RCLK_1
RPOS_1
RNEG_1
VDD
RNEG_0
RPOS_0
RCLK_0
GND
MCLK_0
DJA_1/SDI
STS1_3
FL_3
AGND
ORDERING INFORMATION
PART NUMBER
PACKAGE
OPERATING TEMPERATURE RANGE
XRT71D04IV
80 Pin TQFP
-40oC to +85oC
THERMAL INFORMATION
Theta - JA = ° C/W
Theta JC = ° C/W
2
áç
XRT71D04
4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR STS-1 TO DS3 DESYNCHRONIZER
REV. 1.1.1
TABLE OF CONTENTS
GENERAL DESCRIPTION .................................................................................................. 1
FEATURES ................................................................................................................................................... 1
APPLICATIONS ............................................................................................................................................. 1
Figure 1. Block Diagram (one channel) ................................................................................................. 1
Figure 2. Pin Out of the XRT71D04 ........................................................................................................ 2
ORDERING INFORMATION ..................................................................................................................... 2
TABLE OF CONTENTS...................................................................................................................................... I
PIN DESCRIPTIONS ........................................................................................................... 3
ELECTRICAL CHARACTERISTICS ................................................................................... 9
Figure 3. Input/Output Timing ................................................................................................................ 9
Figure 4. Timing Diagram for the Microprocessor Serial Interface .................................................. 10
SYSTEM DESCRIPTION ................................................................................................... 12
Figure 5. A typical Channel_n of the XRT71D04 configured to operate in the Hardware Mode . 12
Figure 6. A typical Channel_n of the XRT71D04 configured to operate in the Host Mode ........... 13
1.0 Jitter Attenuator PLL .............................................................................................................................. 13
1.1 BACKGROUND INFORMATION ......................................................................................................................................13
1.1.1 Definition of Jitter ..........................................................................................................................................13
1.1.2 SONET STS-1 to DS3 Mapping ....................................................................................................................13
1.2 JITTER TRANSFER CHARACTERISTICS .........................................................................................................................13
Figure 7. Category 1 DS3 Jitter Transfer Mask .................................................................................. 14
1.2.1 Jitter Tolerance .............................................................................................................................................14
1.2.2 Jitter Generation............................................................................................................................................14
1.2.3 Jitter Attenuation ...........................................................................................................................................14
1.2.4 SONET STS-1 DS3 Mapping .......................................................................................................................14
Figure 8. XRT71D04 Desynchronizer Block Diagram ........................................................................ 15
1.3 XRT71DO4 JITTER TRANSFER CHARACTERISTICS ......................................................................................................16
TABLE 1: XRT71D04 JITTER TRANSFER FUNCTION .................................................................................. 16
TABLE 2: XRT71D04 MAXIMUM JITTER TOLERANCE ................................................................................. 17
2.0 Operating Modes .................................................................................................................................... 17
2.1 HARDWARE MODE .....................................................................................................................................................17
TABLE 3: FUNCTIONS OF DUAL MODE PINS IN HARDWARE MODE CONFIGURATION ..................................... 17
2.2 HOST MODE:............................................................................................................................................................17
TABLE 4: ADDRESS AND BIT FORMATS OF THE COMMAND REGISTERS ...................................................... 18
3.0 Microprocessor Serial Interface ............................................................................................................ 18
3.1 SERIAL INTERFACE OPERATION..................................................................................................................................18
3.1.1 Bit 1—R/W (Read/Write) Bit ..........................................................................................................................18
3.1.2 Bits 2 through 6—A0, A1, A2 ,A3, and A4 ....................................................................................................18
3.1.3 Bit 7—A5 .......................................................................................................................................................18
3.1.4 Bit 8—A6 .......................................................................................................................................................18
3.1.5 Read Operation .............................................................................................................................................18
3.1.6 Write Operation .............................................................................................................................................18
Figure 9. Microprocessor Serial Interface Data Structure ................................................................. 19
3.1.7 Simplified Interface Option ............................................................................................................................19
Figure 10. Timing Diagram for the Microprocessor Serial Interface ................................................ 19
ORDERING INFORMATION ............................................................................................. 20
PACKAGE DIMENSIONS ................................................................................................. 20
REVISION HISTORY ..................................................................................................................................... 21
I
XRT71D04
4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
áç
REV. 1.1.1
PIN DESCRIPTIONS
PIN DESCRIPTION
PIN #
NAME
TYPE
1
AVDD
****
2
NC
3
GND
****
4
RRCLK_0
O
DESCRIPTION
Analog Power Supply = 5V±5% or 3.3V±5%
No Connection
Digital Ground
Received Recovered Output (De-jittered) Clock - channel 0:
Output is the de-jittered or smoothed clock if the jitter attenuator is enabled. The
de-jittered data, RRPOS/RRNEG are clocked to this signal.
If RRCLKES is “low”, RRPOS/RRNEG will be updated at the falling edge of
RRCLK.
If RRCLKES is “high”, RRPOS/RRNEG will be updated at the rising edge of
RRCLK.
5
RRPOS_0
O
Received Recovered Positive Data (De-Jittered) Output - channel 0:
De-jittered positive data output. Updated on the rising or falling edge of RRCLK,
depending upon the state of the RRCLKES input pin (or bit-field setting).
6
RRNEG_0
O
Received Recovered Negative Data (De-Jittered) Output - channel 0:
De-jittered negative data output. Updated on the rising or falling edge of RRCLK,
depending upon the state of the RRCLKES input pin (or bit-field setting).
7
RRCLKES
8
NC
9
Reset
I
Reset Input. (Active-Low):
A high-low transition will re-center the internal FIFO, and will clear the Command
Registers (for Host Mode operation). Resetting this pin may corrupt data within
the device.
For normal operation, pull this pin to VDD.
Internal 50 K Ohm pull-up resistor.
10
DS3/E3_1
I
DS3/E3 Select Input - channel 1:
I
Received Recovered Clock Edge Select Input:
Hardware Mode:
1. When RRCLKES = “0”, then RRPOS and RRNEG are updated on the falling
edge of RRCLK
2. When RRCLKES = “1”, then RRPOS and RRNEG are updated on the rising
edge of RRCLK
NOTE: This applies to all channels.
Host Mode
Connect this pin to GND when the 71D04 is configured in the Host Mode.
Internal 50 K Ohm pull-down resistor.
No Connection
This pin along with the STS-1 mode select pin selects the operating mode. The
following table provides the configuration:
XRT71D04 Operating Mode
STS-1
DS3/E3
0
0
DS3 (44.736 MHz)
0
1
E3 (34.368 MHz)
1
0
STS-1 (51.84 MHz)
1
1
E3 (34.368 MHz)
Internal 50 K Ohm pull-down resistor.
11
VDD
****
Digital Power Supply = 5V±5% or 3.3V±5%
3
áç
XRT71D04
4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
REV. 1.1.1
PIN DESCRIPTION
PIN #
NAME
TYPE
DESCRIPTION
12
MODE_CTRL
I
Mode Control:
When “High” in Multimode, all channels are independent. When “Low”, the Master Channel (channel_0) controls DS3/E3_n, STS1_n, RCLKES, FSS and
MCLK_n. DJA is NOT affected.
Internal 50 K Ohm pull-up resistor.
13
ICT
I
In Circuit Testing Input. (Active low):
With this pin tied to ground, all output pins will be in high impedance mode for incircuit-testing.
For normal operation this input pin should be tied to VDD.
Internal 50 K Ohm pull-up resistor.
14
HOST
I
Host/Hardware Mode Select:
An active-high input enables the Host mode. Data is written to the command registers to configure the XRT71D04.
In the Host mode, the states of discrete input pins are inactive.
An active-low input enables the Hardware Mode.In this mode, the discrete inputs
are active.
Internal 50 K Ohm pull-down resistor.
15
FLRST
I
FIFO Limit Reset
Hardware Mode
Whenever the FIFO is within 2 bits of either underflow or overflow, the FL_n will
be set high.
This pin allows the user to reset the state of FL_n, (FIFO Limit) output pin.
This pin when pulsed “High”, resets the the FL_n output pin, (toggles to GND).
NOTE: The FL_n could be set “High” again if the FIFO is within 2 bits of either
underflow or overflow.
Host Mode
Reading the FL_n bits in the status registers clears this FL_n pin. Master Reset
also clears the FL_n output.
This pin is tied to GND. FLRST has no effect in this mode.
Internal 50 K Ohm pull-down resistor.
16
RRNEG_3
O
Received Recovered Negative Data (De-Jittered) Output - channel 3:
See description of pin 6
17
RRPOS_3
O
Received Positive Data (De-Jittered) Output - channel 3:
See description of pin 5
18
RRCLK_3
O
Received Recovered Output (De-jittered) Clock - channel 3:
See description of pin 4
19
GND
O
20
AVDD
****
Analog Power Supply = 5V±5% or 3.3V±5%
21
AGND
****
Analog Ground
22
FL_0
O
Digital Ground
FIFO Limit - channel 0:
This output pin is driven high whenever the internal FIFO comes within two-bits of
being either underflow or overflow.
4
XRT71D04
4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
áç
REV. 1.1.1
PIN DESCRIPTION
PIN #
NAME
TYPE
23
STS1_0
I
DESCRIPTION
SONET STS1 Mode Select - channel 0:
This pin along with the DS3/E3_0 select pin configures the XRT71D04 either in
E3, DS3 or STS-1 mode.
A table relating to the setting of the pins is given below:
XRT71D04 Operating Mode
STS-1
DS3/E3
0
0
DS3 (44.736 MHz)
0
1
E3 (34.368 MHz)
1
0
STS-1 (51.84 MHz)
1
1
E3 (34.368 MHz)
This input pin is active only in the Hardware Mode.
24
DS3/E3_0
I
DS3/E3 Select Input - channel 0:
See description pin 10.
Internal 50 K Ohm pull-down resistor.
25
DJA_0/SCLK
I
Harware Mode
Disable Jitter Attenuator Input - Channel 0:
An active-high disables the Jitter Attenuator. The RPOS/RNEG and RCLK will be
passed through without jitter attenuation.
Host Mode
Microprocessor Serial Interface Clock Signal:
This signal will be used to (1) sample the data, on the SDI pin, on the rising edge
of this signal. Additionally, during “Read” operations, the Microprocessor Serial
Interface will update the SDO output on the falling edge of this signal.
Internal 50 K Ohm pull-down resistor.
26
MCLK_3
I
Master Clock Input - channel 3:
Reference clock for internal PLL. 44.736MHz+/-20ppm or 34.368MHz+/-20ppm.
This clock must be continuous and jitter free with duty cycle between 30 to 70%.
It is permissible to use the EXCLK signal orSTS1 clock.
Internal 50 K Ohm pull-up resistor.
27
GND
****
28
RCLK_3
I
Digital Ground
Received Clock (Jittery) - channel 3:
Clock input RCLK3 should be connected to the recovered clock.
Internal 50 K Ohm pull-up resistor.
29
RPOS_2
I
Received Positive Data (Jittery) Input: - channel 2:
Data that is input on this pin is sampled on either the rising or falling edge of
RCLK depending on the setting of the RCLKES pin (pin 10).
If RCLKES is “high”, then RPOS will be sampled on the falling edge of RCLK.
If RCLKES is “low”, then RPOS will be sampled on the rising edge of RCLK.
Internal 50 K Ohm pull-up resistor.
30
RNEG_2
I
Received Negative Data (Jittery) - channel 2:
The input jittery negative data is sampled either on the rising or falling edge of
RCLK depending on the setting of RCLKES.
If RCLKES is “high”, then RNEG will be sampled on the falling edge of RCLK.
If RCLKES is “low”, then RPOS will be sampled on the rising edge of RCLK.
This pin is typically tied to the “RNEG” output pin of the LIU.
Internal 50 K Ohm pull-up resistor.
31
VDD
****
Digital Power Supply = 5V±5% or 3.3V±5%
5
áç
XRT71D04
4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
REV. 1.1.1
PIN DESCRIPTION
PIN #
NAME
TYPE
32
RNEG_3
I
DESCRIPTION
Received Negative Data (Jittery) - channel 3:
See description of pin 30.
Internal 50 K Ohm pull-up resistor.
33
RPOS_3
I
Received Positive Data (Jittery) Input: - channel 3:
See description of pin 29.
Internal 50 K Ohm pull-up resistor.
34
RCLK_2
I
Received Clock (Jittery) - channel 2:
See description of pin 28.
Internal 50 K Ohm pull-up resistor.
35
GND
****
36
MCLK_2
I
Digital Ground
Master Clock Input - channel 2:
See description of pin 26.
Internal 50 K Ohm pull-up resistor.
37
DJA_2/CS
I
Harware Mode
Disable Jitter Attenuator Input - Channel 2:
See description of pin 25
Host Mode
Chip Select Input:
An active-low input enables the serial interface.
Internal 50 K Ohm pull-down resistor.
38
STS1_2
I
SONET STS1 Mode Select - channel 2:
See description of pin 23
39
FL_2
O
FIFO Limit - channel 2:
See description of pin 22
40
AGND
****
Analog Ground
41
AVDD
****
Analog Power Supply = 5V±5% or 3.3V±5%
42
NC
43
GND
****
44
RRCLK_2
O
No Connection
Digital Ground
Received Recovered Output (De-jittered) Clock - channel 2:
See description of pin 4
45
RRPOS_2
O
Received Recovered Positive Data (De-Jittered) Output - channel 2:
See description of pin 5
46
RRNEG_2
O
Received Recovered Negative Data (De-Jittered) Output - channel 2:
See description of pin 6
47
NC
48
FSS
No Connection
I
FIFO Size Select Input:
When “High”: Selects 32 bits FIFO.
When “Low”: Selects 16 bits FIFO.
Internal 50 K Ohm pull-down resistor.
6
XRT71D04
4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
áç
REV. 1.1.1
PIN DESCRIPTION
PIN #
NAME
TYPE
49
SDO
O
DESCRIPTION
Serial Data Output:
This pin will serially output the contents of the specified Command Register, during “Read” Operations. The data, on this pin, will be updated on the falling edge of
the SCLK input signal. This pin will be tri-stated upon completion of data transfer.
50
DS3/E3_2
I
DS3/E3 Select Input - channel 2:
See description pin 10.
Internal 50 K Ohm pull-down resistor.
51
VDD
****
52
NC
I
No Connection
53
RCLKES
I
Received Clock Edge Select Input:
Digital Power Supply = 5V±5% or 3.3V±5%
Hardware Mode
1. When RCLKES = “0”, then RPOS and RNEG are updated on the falling edge
of RCLK
2. When RCLKES = “1”, then RPOS and RNEG are updated on the rising edge
of RCLK
NOTE: This applies to all channels.
Host Mode
Connect this pin to GND when the 71D04 is configured in the Host Mode.
Internal 50 K Ohm pull-down resistor.
54
NC
55
RRNEG_1
No Connection
O
Received Recovered Negative Data (De-Jittered) Output - channel 1:
See description of pin 6
56
RRPOS_1
O
Received Recovered Positive Data (De-Jittered) Output - channel 1:
See description of pin 5
57
RRCLK_1
O
Received Recovered Output (De-jittered) Clock - channel 1:
See description of pin 4
58
GND
59
NC
60
AVDD
****
Analog Power Supply = 5V±5% or 3.3V±5%
61
AGND
****
Analog Ground
62
FL_1
O
****
Digital Ground
No Connection
FIFO Limit - channel 1:
See description of pin 22
63
STS1_1
I
SONET STS1 Mode Select - channel 1:
See description of pin 23
64
DS3/E3_3
I
DS3/E3 Select Input - channel 3:
See description pin 10.
Internal 50 K Ohm pull-down resistor.
65
DJA_3
I
Disable Jitter Attenuator Input - Channel 3:
See description of pin 25
Internal 50 K Ohm pull-down resistor.
7
áç
XRT71D04
4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
REV. 1.1.1
PIN DESCRIPTION
PIN #
NAME
TYPE
66
MCLK_1
I
DESCRIPTION
Master Clock Input - channel 1:
See description of pin 26.
Internal 50 K Ohm pull-up resistor.
67
GND
****
68
RCLK_1
I
Digital Ground
Received Clock (Jittery) - channel 1:
See description of pin 28.
Internal 50 K Ohm pull-up resistor.
69
RPOS_1
I
Received Positive Data (Jittery) Input: - channel 1:
See description of pin 29.
Internal 50 K Ohm pull-up resistor.
70
RNEG_1
I
Received Negative Data (Jittery) - channel 1:
See description of pin 30.
Internal 50 K Ohm pull-up resistor.
71
VDD
****
72
RNEG_0
I
Digital Power Supply = 5V±5% or 3.3V±5%
Received Negative Data (Jittery) - channel 0:
See description of pin 30.
Internal 50 K Ohm pull-up resistor.
73
RPOS_0
I
Received Positive Data (Jittery) Input: - channel 0:
See description of pin 29.
Internal 50 K Ohm pull-up resistor.
74
RCLK_0
I
Received Clock (Jittery) - channel 0:
See description of pin 28.
Internal 50 K Ohm pull-up resistor.
75
GND
****
76
MCLK_0
I
Digital Ground
Master Clock Input - channel 0:
See description of pin 26.
Internal 50 K Ohm pull-up resistor.
77
DJA_1/SDI
I
Harware Mode
Disable Jitter Attenuator Input - Channel 1:
See description of pin 25
Host Mode
Serial Data Input
The address value (of the command registers) or the data value is either Read or
Written through this pin.
The input data will be sampled on the rising edge of the SCLK pin.
Internal 50 K Ohm pull-down resistor.
78
STS1_3
I
SONET STS1 Mode Select - channel 3:
See description of pin 23
79
FL_3
O
FIFO Limit - channel 3:
See description of pin 22
80
AGND
****
Analog Ground
8
XRT71D04
4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
áç
REV. 1.1.1
ELECTRICAL CHARACTERISTICS
AC Electrical Characteristics
Electrical Characteristics (TA = 25°C, VDD = 3.3 V t0 5.0 V± 5 % unless otherwise specified)
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS.
30
50
70
%
MClk
Duty Cycle
MClk
Frequency E3 + 20 ppm
34.368
MHz
MClk
Frequency DS3 + 20 ppm
44.736
MHz
MClk
Frequency STS-1 + 20 ppm
RClk
Duty Cycle
RClk
RClk
51.84
30
50
MHz
70
%
Rise Time
5
ns
Fall Time
5
ns
tsu
RPOS/RNEG to RClk rise time setup
5
ns
th
RPOS/RNEG to RClk rising hold time
5
ns
td
RRPOS/RRNEG delay from RRClk rising
5
ns
te
RRPOS/RRNEG delay from RRClk falling
5
ns
FIGURE 3. INPUT/OUTPUT TIMING
tsu
RCLK
RCLK
th
td
RPOS/RNEG
RPOS/RNEG
RClkES = 0
tsu
RCLK
RCLK
th
te
RPOS/RNEG
RPOS/RNEG
RClkES = 1
9
áç
XRT71D04
4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
REV. 1.1.1
Microprocessor Serial Interface Timing ( see Figure 4 )
Electrical Characteristics (TA = 25°C, VDD = 3.3 V to 5.0 V ± 5 % unless otherwise specified)
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS.
t21
CS Low to Rising Edge of SClk Setup Time
50
ns
t22
SClk to CS Hold Time
20
ns
t23
SDI to Rising Edge of SClk Setup Time
50
ns
t24
SDI to Rising Edge of SClk Hold Time
50
ns
t25
SClk “Low” Time
240
ns
t26
SClk “High” Time
240
ns
t27
SClk Period
500
ns
t28
SClk to CS Hold Time
50
ns
t29
CSB “Inactive” Time
250
t30
Falling Edge of SClk to SDO Valid Time
200
ns
t31
Falling Edge of SClk to SDO Invalid Time
100
ns
t32
Falling Edge of SClk, or rising edge of CS to High Z
ns
100
ns
FIGURE 4. TIMING DIAGRAM FOR THE MICROPROCESSOR SERIAL INTERFACE
t29
t21
CS
t27
t22
t25
SClk
t26
t24
t23
SDI
t28
A0
R/W
A1
CS
SClk
t31
t30
SDO
SDI
Hi-Z
D0
t33
t32
D2
D1
Hi-Z
10
D7
XRT71D04
4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
áç
REV. 1.1.1
DC Electrical Characteristics (TA = 25°C, VDD = 3.3 V ± 5 % unless otherwise specified)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
Power Supply Voltage
VDD
3.135
3.3
3.465
V
Input High Voltage
VIH
2.0
5.25
V
Input Low Voltage
VIL
-0.5
0.8
V
Output High Voltage @ IOH=-5mA
VOH
2.4
Output Low Voltage @ IOL=5mA
VOL
Supply Current ( E3)
Icc
95
mA
Supply Current ( DS3 )
Icc
110
mA
Supply Current ( STS-1)
Icc
125
Input Leakage Current(except Input pins with Pull-up resistor.
IL
Input Capacitance
CI
Output Load Capacitance
CL
V
0.4
± 10
5.0
V
µA
pF
25
pF
DC Electrical Characteristics (TA = 25°C, VDD = 5.0 V ± 5 % unless otherwise specified)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
Power Supply Voltage
VDD
4.75
5.0
5.25
V
Input High Voltage
VIH
2.0
5.25
V
Input Low Voltage
VIL
-0.5
0.8
V
Output High Voltage @ IOH=-5mA
VOH
2.4
Output Low Voltage @ IOL=5mA
VOL
Supply Current ( E3)
Icc
140
mA
Supply Current ( DS3 )
Icc
170
mA
Supply Current ( STS-1)
Icc
190
Input Leakage Current(except Input pins with Pull-up resistor.
IL
Input Capacitance
CI
Output Load Capacitance
CL
V
0.4
± 10
5.0
Supply Range
-0.5 V to + 6.0 V
ESD Rating
> 2000 V on all pins
Operating Temperature
-400C to +850C
Storage Temperature
-65°C to + 150°C
11
µA
pF
25
ABSOLUTE MAXIMUM RATINGS:
V
pF
áç
XRT71D04
4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
REV. 1.1.1
SYSTEM DESCRIPTION
The XRT71D04 also meets the DS3 wander specification that apply to SONET and asynchronous interfaces as specified in the ANSI T1.105.03b 1997 standard.
The XRT71D04 is an integrated 4-channel E3/DS3/
STS-1 jitter attenuator that attenuates the jitter from
the input clock and data. The jitter attenuation performance meets the latest specifications such as Bellcore
GR-499 CORE,GR-253 CORE, ETSI TBR24,ITU-T
G.751,ITU-T G.752 and ITU-T G.755 standards.
For support of loop-timing applications, the
XRT71D04 can also be used to reduce and limit the
amount of jitter in the recovered line clock signal.
Figure 5 presents a simple block diagram of the
XRT71D04, when it is configured to operate in the
Hardware Mode and Figure 6 presents a simple block
diagram of the XRT71D04, when it is configured to
operate in the Host Mode.
The XRT71D04 also meets both the mapping and
pointer adjustment jitter generation criteria for both
Category I and Category II interfaces as specified in
Bellcore GR-253.
FIGURE 5. A TYPICAL CHANNEL_N OF THE XRT71D04
ICT
Jittery
Clock
CONFIGURED TO OPERATE IN THE
Timing Control Block /
Phase locked Loop
HARDWARE MODE
MCLK_n
Smoothed
Clock
DJA_n
RClk_n
RCLKES
RPOS_n
RNEG_n
Write Clock
Read Clock
16/32 Bit FIFO
RRCLK_n
RRPOS_n
RRNEG_n
RRCLKES
FL_n
FSS
HOST
Reset
DS3/E3_n
12
XRT71D04
4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
áç
REV. 1.1.1
FIGURE 6. A TYPICAL CHANNEL_N OF THE XRT71D04 CONFIGURED TO OPERATE IN THE HOST MODE
ICT
Jittery
Clock
RCLK_n
Timing Control Block /
Phase locked Loop
Write Clock
MClkn
Smoothed
Clock
Read Clock
RRCLK_n
RRPOS_n
16/32 Bit FIFO
RPOS_n
RNEG_n
RRNEG_n
RRCLKES
FL_n
HOST
Reset
Microprocessor Serial
Interface
CS
SDI
SDO SClk
The XRT71D04 DS3/E3 Jitter Attenuator IC consists
of the following functional blocks:
2) Cross-talk noise
• The Jitter-Attenuator PLL
• Timing Control Block
1.1.2 SONET STS-1 to DS3 Mapping
SONET equipment jitter criteria are specified as:
• The 2-Channel 16/32 Bit FIFO
i) Jitter Transfer
• Serial Microprocessor Interface
ii) Jitter Tolerance
3) Inter-symbol interference/Signal Distortion
1.0 JITTER ATTENUATOR PLL
iii) Jitter Generation
1.1 BACKGROUND INFORMATION
1.2 JITTER TRANSFER CHARACTERISTICS
The primary purpose of jitter transfer requirements is
to prevent performance degradations by limiting the
accummulation of jitter through the system such that
it does not exceed the network interface jitter requirements. Thus, it is more important that a system meet
the jitter transfer criteria for relatively high input jitter
amplitudes. The jitter transferred through the system
must be under the jitter mask for any input jitter amplitude within the range as shown in Figure 7
1.1.1 Definition of Jitter
One of the most important and least understood measures of clock performance is jitter. The International
Telecommunication Union defines jitter as short term
variations of the significant instants of a digita signal
from their ideal positions in time. Jitter can occur due
to any of the following:
1) Imperfect timing recovery circuit in the system
13
áç
XRT71D04
4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
REV. 1.1.1
FIGURE 7. CATEGORY 1 DS3 JITTER TRANSFER MASK
Jitter Gain
(dB)
0.1
slope = -20 dB/decade
Acceptable
Range
40
Frequency (Hz)
1.2.1 Jitter Tolerance
The jitter tolerance in the network element is defined
as the maximum amount of jitter in the incoming signal that it can receive in an error-free manner.
In Figure 5and Figure 6, this de-jittered clock is labeled Smoothed Clock. This Smoothed Clock is now
used to Read Out the Recovered Data from the 16/32
bit FIFO. This Smoothed Clock will also be output to
the Terminal Equipment via the RRClk output pin.
Likewise, the Smoothed Recovered Data will output
to the Terminal Equipment via the RRPOS and
RRNEG output pins.
1.2.2 Jitter Generation
Jitter generation is defined in Section 7.3.3 of GR499-CORE. Jitter generation criteria exists for both
Category I and II interfaces, which consist of mapping
and pointer adjustment jitter generation.
The XRT71D04 is designed to work as a companion
device with XRT73L04 (STS-1/DS3/E3) Line Interface Unit.
Mapping jitter is the sum of the intrinsic payload mapping jitter and the jitter that is generated as a result of
the bit stuffing mechnisms used in all of the asynchronous DSn mapping into STS SPE.
ETSI TBR24 specifies the maximum output jitter in
loop timing must be no more than 0.4UIpp when measured between 100Hz to 800KHzwith upto 1.5UI input
jitter at 100Hz. This means a jitter attenuator with
bandwidth less than 100Hz is required to be compliant with the standard. ITU G.751 is another application where low bandwidth jitter attenuator is needed
to smooth the gapped clock output in the de-multiplexer system.
1.2.3 Jitter Attenuation
A digital Jitter Attenuation loop combined with the
FIFO provides Jitter attenuation. The Jitter Attenuator
requires no external components except for the reference clock.
Data is clocked into the FIFO with the associated
clock signal (TClk or RClk) and clocked out of the
FIFO with the dejittered clock and data. When the
FIFO is within 2 bits of being completely full, the FIFO
Limit (FL) will be set.
1.2.4 SONET STS-1 DS3 Mapping
Bellcore GR-253 section 3.4.2 and the ANSI T1.105199 describes the asynchronous mapping for DS3 into STS-1 SPE.
14
XRT71D04
4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
áç
REV. 1.1.1
block diagram of the Desynchronizer is shown in
Figure 8.
An asynchronous mapping for DS3 into STS-1 SPE is
defined for clear-channel transport of DS3 signals
that meet the DSX-3 requirements in the GR-499CORE.
The elastic store accepts the STS-1 data stream and
a gapped clock. The gaps in the input clock inhibit the
elastic store from writing all but DS3 payload data.
When the input data has a rate lower than the output
data rate, the positive stuffing will occur. The stuffing
mechanism that generates the C-bits is implemented in a desynchronizer that has the jitter output less
than 0.4 UIpp assuming no jitter or wander at the input of the synchronizer and no pointer adjustments. A
The bit leaking circuit stores incoming STS-1 pointer
adjustments into a queue and leaks them out of the
desynchronizer one bit at a time.
STS-Nc signal is used to transport higher rate signals. However,the digital signals that SONET carries
do not fit in the SPE perfectly.
FIGURE 8. XRT71D04 DESYNCHRONIZER BLOCK DIAGRAM
STS-1
reference clock
STS- N
Clock
STS-N
STS-1
OH
Processing
Clock
Recovery
Descramble/
Demux
STS-1
gapped clock
XRT71D04
DS3 payload
(dejittered)
STS-1
STS-1
Pointer
Processing
Elastic
Store
Section &
Line Overhead
STS- N
Nth STS-1
STS-1
gapped clock
15
Dejittering &
Pointer
Adjustment
Stuff Control
áç
XRT71D04
4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
REV. 1.1.1
1.3 XRT71DO4 JITTER TRANSFER CHARACTERISTICS
Table 1 summarizes the results of jitter transfer characteristics testing, performed on the XRT71D04.
Table 2 summarizes the results of jitter tolerance testing, performed on the XRT71D04.
TABLE 1: XRT71D04 JITTER TRANSFER FUNCTION
APPLICATION
INPUT JITTER
FREQ. (HZ)
DS3
1UIPP
E3
10UIPP
1UIPP
Jitter Gain (dB)
STS-1
10UIPP
Jitter Gain (dB)
5
0.02
0.36
0.44
0.83
10
-0.10
-0.30
-0.15
-0.22
20
-2.04
-2.24
-3.16
-3.24
30
-3.63
-4.33
-5.51
-5.93
40
-5.98
-6.16
-7.68
-7.99
50
-7.55
-7.82
-10.36
-9.61
60
-9.57
-9.17
-12.50
-11.27
80
-12.54
-11.28
-15.20
-13.59
100
-14.67
-13.36
-16.22
-15.51
125
-16.67
-14.91
-17.38
-17.07
150
-17.32
-16.78
-19.45
-18.75
200
-18.77
-18.96
-20.36
-21.11
300
-21.43
-21.81
-22.96
-24.46
500
-22.22
-26.09
-23.78
-28.84
>1000
-25.42
-33.44
-23.51
-35.77
16
1UIPP
10UIPP
Jitter Gain (dB)
XRT71D04
4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
áç
REV. 1.1.1
TABLE 2: XRT71D04 MAXIMUM JITTER TOLERANCE
APPLICATION
FIFO SIZE
FREQ. (HZ)
DS3
16
E3
32
16
UI (PEAK TO PEAK)
STS-1
32
UI (PEAK TO PEAK)
10
34.313
>64
26.689
53.313
20
21.439
43.188
18.564
37.438
30
18.314
36.813
16.689
33.938
40
16.939
34.313
16.064
32.688
50
16.314
33.188
15.689
32.063
60
16.064
32.563
15.564
31.689
80
15.689
31.814
15.314
31.314
100
15.439
31.439
15.314
31.189
125
15.439
31.314
15.189
31.064
150
15.314
31.189
15.189
31.064
200
15.314
31.064
15.189
30.939
300
15.189
30.939
15.064
30.939
500
15.189
30.939
15.064
30.939
>1000
15.0189
30.939
15.189
30.939
2.1 HARDWARE MODE
The HOST pin is used to select the operating mode of
the XRT71D04. In Hardware mode (connect this pin
to ground), the serial processor interface is disabled
and hard-wired pins are used to control configuration
and report status.
FUNCTION, WHILE IN THE
HARDWARE MODE
25
DJA0/SCLK
DJA0
37
DJA2/(CS)
DJA2
77
DJA1/(SDI)
DJA1
UI (PEAK TO PEAK)
A listing of these Command Registers, their Addresses, and their bit-formats are listed below in Table 4.
TABLE 3: FUNCTIONS OF DUAL MODE PINS IN
HARDWARE MODE CONFIGURATION
PIN NAME
32
2.2 HOST MODE:
In Host mode (connect this pin to VDD), the serial
port interface pins are used to control configuration
and status report. In this mode, serial interface pins :
SDI, SDO,SCLK and CS are used.
2.0 OPERATING MODES
PIN #
16
17
áç
XRT71D04
4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
REV. 1.1.1
TABLE 4: ADDRESS AND BIT FORMATS OF THE COMMAND REGISTERS
ADDR
COMMAND
REGISTER
TYPE
D7
D6
D5
D4
D3
D2
D1
D0
0X06
CR6
R/W
***
***
STS-1_0
DS3/E3_0
DJA_0
RRClkES_0
RClkES_0
FSS_0
0x07
CR7
RO
***
***
***
***
***
***
***
FL_0
0x0E
CR14
R/W
***
***
STS-1_1
DS3/E3_1
DJA_1
RRClkES_1
RClkES_1
FSS_1
0x0F
CR15
RO
***
***
***
***
***
***
***
FL_1
0x16
CR22
R/W
***
***
STS-1_2
DS3/E3_2
DJA_2
RRClkES_2
RClkES_2
FSS_2
0x17
CR23
RO
***
***
***
***
***
***
***
FL_2
0x1E
CR30
R/W
***
***
STS-1_3
DS3/E3_3
DJA_3
RRClkES_3
RCLKES_3
FSS_3
0x1F
CR31
RO
***
***
***
***
***
***
***
FL_3
3.1.3 Bit 7—A5
A5 must be set to “0”, as shown in Figure 9.
3.0 MICROPROCESSOR SERIAL INTERFACE
The serial interface for the XRT71D04 and the
XRT73L00 family of E3/DS3/STS-1 LIU’s are the
same, which makes it easy to configure both the
XRT71D04 and the LIU with a single CS, SDI, SDO
and SClk input and output pins.
3.1.4 Bit 8—A6
The value of A6 is a don’t care.
Once these first 8 bits have been written into the Serial Interface, the subsequent action depends upon
whether the current operation is a Read or Write operation.
3.1 SERIAL INTERFACE OPERATION.
Serial interface data structure and timings are provided in Figure 5 and 6 respectively.
3.1.5 Read Operation
Once the last address bit (A4) has been clocked into
the SDI input, the Read operation will proceed
through an idle period, lasting three SClk periods. On
the falling edge of SClk Cycle #8 (see Figure 9) the
serial data output signal (SDO) becomes active. At
this point the user can begin reading the data contents of the addressed Command Register (at Address [A4,A3, A2, A1, A0]) via the SDO output pin.
The Serial Interface will output this eight bit data word
(D0 through D7) in ascending order (with the LSB
first), on the falling edges of the SClk . The data (on
the SDO output pin) is stable for reading on the very
next rising edge of the SClk .
The clock signal is provided to the SClk and the CS is
asserted for 50 ns prior to the first rising edge of the
SClk.
3.1.1 Bit 1—R/W (Read/Write) Bit
This bit will be clocked into the SDI input, on the first
rising edge of SClk (after CS has been asserted).
This bit indicates whether the current operation is a
Read or Write operation. A “1” in this bit specifies a
Read operation; whereas, a “0” in this bit specifies a
Write operation.
3.1.2 Bits 2 through 6—A0, A1, A2 ,A3, and A4
The five (5) bit Address Values.
The next five rising edges of the SClk signal will clock
in the 5-bit address value for this particular Read (or
Write) operation. The address selects the Command
Register for reading data from, or writing data to. The
address bits to the SDI input pin is applied in ascending order with the LSB (least significant bit) first.
3.1.6 Write Operation
Once the last address bit (A4) has been clocked into
the SDI input, the Write operation will proceed
through an idle period, lasting three SClk periods. Prior to the rising edge of SClk Cycle #9 , the eight bit
data word is applied to SDI input. Data on SDI is
latched on the rising edge of SClk.
18
áç
XRT71D04
4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
REV. 1.1.1
FIGURE 9. MICROPROCESSOR SERIAL INTERFACE DATA STRUCTURE
CS
SClk
1
SDI
R/W
2
A0
3
A1
4
A2
5
A3
6
A4
7
0
8
A6
9
10
11
12
13
14
15
16
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
High Z
High Z
SDO
NOTES:
1.
2.
3.
4.
3.1.7 Simplified Interface Option
The user can simplify the design of the circuitry connecting to the Microprocessor Serial Interface by tying both the SDO and SDI pins together, and reading
data from and/or writing data to this combined signal.
This simplification is possible because only one of
these signals are active at any given time. The inactive signal will be tri-stated.
A5 is always “0”.
R/W = “1” for Read Operations
R/W = “0” for Write Operations
Denotes a “don’t care” value (shaded areas)
FIGURE 10. TIMING DIAGRAM FOR THE MICROPROCESSOR SERIAL INTERFACE
t29
t21
CS
t27
t22
t25
SClk
t26
t24
t23
SDI
t28
A0
R/W
A1
CS
SClk
t31
t30
SDO
SDI
Hi-Z
D0
t33
t32
D2
D1
Hi-Z
19
D7
áç
XRT71D04
4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
PRELIMINARY
REV. 1.1.1
ORDERING INFORMATION
PART #
PACKAGE
OPERATING TEMPERATURE RANGE
XRT71D04IV
80 Pin TQFP
-40oC to +85oC
THERMAL INFORMATION
Theta - JA = ° C/W
Theta JC = ° C/W
PACKAGE DIMENSIONS
80 LEAD THIN QUAD FLAT PACK
(14X14X1.4mm, TQFP)
Rev. 1.0
D
D1
41
60
40
61
D1
80
D
21
A2
1
20
e
B
C
A
α
L
A1
SYMBOL
INCHES
MIN
MAX
MILLIMETERS
MIN
MAX
A
A1
A2
B
C
D
D1
e
L
α
0.055
0.063
0.002
0.006
0.053
0.057
0.009
0.015
0.004
0.008
0.622
0.638
0.547
0.555
0.0256BSC
0.018
0.030
0o
7o
1.40
1.60
0.05
0.15
1.35
1.45
0.22
0.38
0.09
0.20
15.80
16.20
13.90
14.10
0.65BSC
0.45
0.75
0o
7o
Note: the control dimension is the millimeter column
20
XRT71D04
áç
4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
REV. 1.1.1
REVISION HISTORY
Rev. P1.0.1; Revised pull-up/pull-down resistors on various pins.
Rev. P1.0.2; Corrected block diagram and made minor edits.
Rev. P1.0.3 Modified pin list and figures to reflect channel designation by _n (example; MCLK0 to
MCLK_0). Changed from VSS to GND.
Rev. 1.1.0: Remved Preliminary designation. Added electrical characteristics tables.
Rev. 1.1.1: Corrected Table 4 adding RRClkES_n as data D2, STS-1_n as D5, added D7. Corrected the
description of the section 3 Serial Microprocessor Interface. Moved figure 9 into Electrical Characteristics
Section. Moved Jitter Transfer/Tolerance tables into Jitter Attenuator Section 1.
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order
to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of
any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for
illustration purposes and may vary depending upon a user’s specific application. While the information in
this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where
the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury
or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances.
Copyright 2001 EXAR Corporation
Datasheet April 2001.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
21
工商网监
湘ICP备2023018690号
